--- block/ETHERNET_DMA: description: "Ethernet: DMA mode register (DMA)" items: - name: DMAMR description: DMA mode register byte_offset: 0 fieldset: DMAMR - name: DMASBMR description: System bus mode register byte_offset: 4 fieldset: DMASBMR - name: DMAISR description: Interrupt status register byte_offset: 8 access: Read fieldset: DMAISR - name: DMADSR description: Debug status register byte_offset: 12 access: Read fieldset: DMADSR - name: DMACCR description: Channel control register byte_offset: 256 fieldset: DMACCR - name: DMACTxCR description: Channel transmit control register byte_offset: 260 fieldset: DMACTxCR - name: DMACRxCR description: Channel receive control register byte_offset: 264 fieldset: DMACRxCR - name: DMACTxDLAR description: Channel Tx descriptor list address register byte_offset: 276 fieldset: DMACTxDLAR - name: DMACRxDLAR description: Channel Rx descriptor list address register byte_offset: 284 fieldset: DMACRxDLAR - name: DMACTxDTPR description: Channel Tx descriptor tail pointer register byte_offset: 288 fieldset: DMACTxDTPR - name: DMACRxDTPR description: Channel Rx descriptor tail pointer register byte_offset: 296 fieldset: DMACRxDTPR - name: DMACTxRLR description: Channel Tx descriptor ring length register byte_offset: 300 fieldset: DMACTxRLR - name: DMACRxRLR description: Channel Rx descriptor ring length register byte_offset: 304 fieldset: DMACRxRLR - name: DMACIER description: Channel interrupt enable register byte_offset: 308 fieldset: DMACIER - name: DMACRxIWTR description: Channel Rx interrupt watchdog timer register byte_offset: 312 fieldset: DMACRxIWTR - name: DMACCATxDR description: Channel current application transmit descriptor register byte_offset: 324 access: Read fieldset: DMACCATxDR - name: DMACCARxDR description: Channel current application receive descriptor register byte_offset: 332 access: Read fieldset: DMACCARxDR - name: DMACCATxBR description: Channel current application transmit buffer register byte_offset: 340 access: Read fieldset: DMACCATxBR - name: DMACCARxBR description: Channel current application receive buffer register byte_offset: 348 access: Read fieldset: DMACCARxBR - name: DMACSR description: Channel status register byte_offset: 352 fieldset: DMACSR - name: DMACMFCR description: Channel missed frame count register byte_offset: 364 access: Read fieldset: DMACMFCR fieldset/DMACCARxBR: description: Channel current application receive buffer register fields: - name: CURRBUFAPTR description: Application Receive Buffer Address Pointer bit_offset: 0 bit_size: 32 fieldset/DMACCARxDR: description: Channel current application receive descriptor register fields: - name: CURRDESAPTR description: Application Receive Descriptor Address Pointer bit_offset: 0 bit_size: 32 fieldset/DMACCATxBR: description: Channel current application transmit buffer register fields: - name: CURTBUFAPTR description: Application Transmit Buffer Address Pointer bit_offset: 0 bit_size: 32 fieldset/DMACCATxDR: description: Channel current application transmit descriptor register fields: - name: CURTDESAPTR description: Application Transmit Descriptor Address Pointer bit_offset: 0 bit_size: 32 fieldset/DMACCR: description: Channel control register fields: - name: MSS description: Maximum Segment Size bit_offset: 0 bit_size: 14 - name: PBLX8 description: 8xPBL mode bit_offset: 16 bit_size: 1 - name: DSL description: Descriptor Skip Length bit_offset: 18 bit_size: 3 fieldset/DMACIER: description: Channel interrupt enable register fields: - name: TIE description: Transmit Interrupt Enable bit_offset: 0 bit_size: 1 - name: TXSE description: Transmit Stopped Enable bit_offset: 1 bit_size: 1 - name: TBUE description: Transmit Buffer Unavailable Enable bit_offset: 2 bit_size: 1 - name: RIE description: Receive Interrupt Enable bit_offset: 6 bit_size: 1 - name: RBUE description: Receive Buffer Unavailable Enable bit_offset: 7 bit_size: 1 - name: RSE description: Receive Stopped Enable bit_offset: 8 bit_size: 1 - name: RWTE description: Receive Watchdog Timeout Enable bit_offset: 9 bit_size: 1 - name: ETIE description: Early Transmit Interrupt Enable bit_offset: 10 bit_size: 1 - name: ERIE description: Early Receive Interrupt Enable bit_offset: 11 bit_size: 1 - name: FBEE description: Fatal Bus Error Enable bit_offset: 12 bit_size: 1 - name: CDEE description: Context Descriptor Error Enable bit_offset: 13 bit_size: 1 - name: AIE description: Abnormal Interrupt Summary Enable bit_offset: 14 bit_size: 1 - name: NIE description: Normal Interrupt Summary Enable bit_offset: 15 bit_size: 1 fieldset/DMACMFCR: description: Channel missed frame count register fields: - name: MFC description: Dropped Packet Counters bit_offset: 0 bit_size: 11 - name: MFCO description: Overflow status of the MFC Counter bit_offset: 15 bit_size: 1 fieldset/DMACRxCR: description: Channel receive control register fields: - name: SR description: Start or Stop Receive Command bit_offset: 0 bit_size: 1 - name: RBSZ description: Receive Buffer size bit_offset: 1 bit_size: 14 - name: RXPBL description: RXPBL bit_offset: 16 bit_size: 6 - name: RPF description: DMA Rx Channel Packet Flush bit_offset: 31 bit_size: 1 fieldset/DMACRxDLAR: description: Channel Rx descriptor list address register fields: - name: RDESLA description: Start of Receive List bit_offset: 2 bit_size: 30 fieldset/DMACRxDTPR: description: Channel Rx descriptor tail pointer register fields: - name: RDT description: Receive Descriptor Tail Pointer bit_offset: 2 bit_size: 30 fieldset/DMACRxIWTR: description: Channel Rx interrupt watchdog timer register fields: - name: RWT description: Receive Interrupt Watchdog Timer Count bit_offset: 0 bit_size: 8 fieldset/DMACRxRLR: description: Channel Rx descriptor ring length register fields: - name: RDRL description: Receive Descriptor Ring Length bit_offset: 0 bit_size: 10 fieldset/DMACSR: description: Channel status register fields: - name: TI description: Transmit Interrupt bit_offset: 0 bit_size: 1 - name: TPS description: Transmit Process Stopped bit_offset: 1 bit_size: 1 - name: TBU description: Transmit Buffer Unavailable bit_offset: 2 bit_size: 1 - name: RI description: Receive Interrupt bit_offset: 6 bit_size: 1 - name: RBU description: Receive Buffer Unavailable bit_offset: 7 bit_size: 1 - name: RPS description: Receive Process Stopped bit_offset: 8 bit_size: 1 - name: RWT description: Receive Watchdog Timeout bit_offset: 9 bit_size: 1 - name: ET description: Early Transmit Interrupt bit_offset: 10 bit_size: 1 - name: ER description: Early Receive Interrupt bit_offset: 11 bit_size: 1 - name: FBE description: Fatal Bus Error bit_offset: 12 bit_size: 1 - name: CDE description: Context Descriptor Error bit_offset: 13 bit_size: 1 - name: AIS description: Abnormal Interrupt Summary bit_offset: 14 bit_size: 1 - name: NIS description: Normal Interrupt Summary bit_offset: 15 bit_size: 1 - name: TEB description: Tx DMA Error Bits bit_offset: 16 bit_size: 3 - name: REB description: Rx DMA Error Bits bit_offset: 19 bit_size: 3 fieldset/DMACTxCR: description: Channel transmit control register fields: - name: ST description: Start or Stop Transmission Command bit_offset: 0 bit_size: 1 - name: OSF description: Operate on Second Packet bit_offset: 4 bit_size: 1 - name: TSE description: TCP Segmentation Enabled bit_offset: 12 bit_size: 1 - name: TXPBL description: Transmit Programmable Burst Length bit_offset: 16 bit_size: 6 fieldset/DMACTxDLAR: description: Channel Tx descriptor list address register fields: - name: TDESLA description: Start of Transmit List bit_offset: 2 bit_size: 30 fieldset/DMACTxDTPR: description: Channel Tx descriptor tail pointer register fields: - name: TDT description: Transmit Descriptor Tail Pointer bit_offset: 2 bit_size: 30 fieldset/DMACTxRLR: description: Channel Tx descriptor ring length register fields: - name: TDRL description: Transmit Descriptor Ring Length bit_offset: 0 bit_size: 10 fieldset/DMADSR: description: Debug status register fields: - name: AXWHSTS description: AHB Master Write Channel bit_offset: 0 bit_size: 1 - name: RPS0 description: DMA Channel Receive Process State bit_offset: 8 bit_size: 4 - name: TPS0 description: DMA Channel Transmit Process State bit_offset: 12 bit_size: 4 fieldset/DMAISR: description: Interrupt status register fields: - name: DC0IS description: DMA Channel Interrupt Status bit_offset: 0 bit_size: 1 - name: MTLIS description: MTL Interrupt Status bit_offset: 16 bit_size: 1 - name: MACIS description: MAC Interrupt Status bit_offset: 17 bit_size: 1 fieldset/DMAMR: description: DMA mode register fields: - name: SWR description: Software Reset bit_offset: 0 bit_size: 1 - name: DA description: DMA Tx or Rx Arbitration Scheme bit_offset: 1 bit_size: 1 - name: TXPR description: Transmit priority bit_offset: 11 bit_size: 1 - name: PR description: Priority ratio bit_offset: 12 bit_size: 3 - name: INTM description: Interrupt Mode bit_offset: 16 bit_size: 2 fieldset/DMASBMR: description: System bus mode register fields: - name: FB description: Fixed Burst Length bit_offset: 0 bit_size: 1 - name: AAL description: Address-Aligned Beats bit_offset: 12 bit_size: 1 - name: MB description: Mixed Burst bit_offset: 14 bit_size: 1 - name: RB description: Rebuild INCRx Burst bit_offset: 15 bit_size: 1