block/RCC: description: Reset and clock control items: - name: CR description: Clock control register byte_offset: 0 fieldset: CR - name: ICSCR description: Internal clock sources calibration register byte_offset: 4 fieldset: ICSCR - name: CFGR description: Clock configuration register byte_offset: 8 fieldset: CFGR - name: PLLCFGR description: PLL configuration register byte_offset: 12 fieldset: PLLCFGR - name: CIER description: Clock interrupt enable register byte_offset: 24 fieldset: CIER - name: CIFR description: Clock interrupt flag register byte_offset: 28 access: Read fieldset: CIFR - name: CICR description: Clock interrupt clear register byte_offset: 32 access: Write fieldset: CICR - name: AHB1RSTR description: AHB1 peripheral reset register byte_offset: 40 fieldset: AHB1RSTR - name: AHB2RSTR description: AHB2 peripheral reset register byte_offset: 44 fieldset: AHB2RSTR - name: AHB3RSTR description: AHB3 peripheral reset register byte_offset: 48 fieldset: AHB3RSTR - name: APB1RSTR1 description: APB1 peripheral reset register 1 byte_offset: 56 fieldset: APB1RSTR1 - name: APB1RSTR2 description: APB1 peripheral reset register 2 byte_offset: 60 fieldset: APB1RSTR2 - name: APB2RSTR description: APB2 peripheral reset register byte_offset: 64 fieldset: APB2RSTR - name: APB3RSTR description: APB3 peripheral reset register byte_offset: 68 fieldset: APB3RSTR - name: AHB1ENR description: AHB1 peripheral clock enable register byte_offset: 72 fieldset: AHB1ENR - name: AHB2ENR description: AHB2 peripheral clock enable register byte_offset: 76 fieldset: AHB2ENR - name: AHB3ENR description: AHB3 peripheral clock enable register byte_offset: 80 fieldset: AHB3ENR - name: APB1ENR1 description: APB1 peripheral clock enable register 1 byte_offset: 88 fieldset: APB1ENR1 - name: APB1ENR2 description: APB1 peripheral clock enable register 2 byte_offset: 92 fieldset: APB1ENR2 - name: APB2ENR description: APB2 peripheral clock enable register byte_offset: 96 fieldset: APB2ENR - name: APB3ENR description: APB3 peripheral clock enable register byte_offset: 100 fieldset: APB3ENR - name: AHB1SMENR description: AHB1 peripheral clocks enable in Sleep modes register byte_offset: 104 fieldset: AHB1SMENR - name: AHB2SMENR description: AHB2 peripheral clocks enable in Sleep modes register byte_offset: 108 fieldset: AHB2SMENR - name: AHB3SMENR description: AHB3 peripheral clocks enable in Sleep and Stop modes register byte_offset: 112 fieldset: AHB3SMENR - name: APB1SMENR1 description: APB1 peripheral clocks enable in Sleep mode register 1 byte_offset: 120 fieldset: APB1SMENR1 - name: APB1SMENR2 description: APB1 peripheral clocks enable in Sleep mode register 2 byte_offset: 124 fieldset: APB1SMENR2 - name: APB2SMENR description: APB2 peripheral clocks enable in Sleep mode register byte_offset: 128 fieldset: APB2SMENR - name: APB3SMENR description: APB3 peripheral clock enable in Sleep mode register byte_offset: 132 fieldset: APB3SMENR - name: CCIPR description: Peripherals independent clock configuration register byte_offset: 136 fieldset: CCIPR - name: BDCR description: Backup domain control register byte_offset: 144 fieldset: BDCR - name: CSR description: Control/status register byte_offset: 148 fieldset: CSR - name: EXTCFGR description: Extended clock recovery register byte_offset: 264 fieldset: EXTCFGR - name: C2AHB1ENR description: CPU2 AHB1 peripheral clock enable register byte_offset: 328 fieldset: C2AHB1ENR - name: C2AHB2ENR description: CPU2 AHB2 peripheral clock enable register byte_offset: 332 fieldset: C2AHB2ENR - name: C2AHB3ENR description: CPU2 AHB3 peripheral clock enable register [dual core device only] byte_offset: 336 fieldset: C2AHB3ENR - name: C2APB1ENR1 description: CPU2 APB1 peripheral clock enable register 1 [dual core device only] byte_offset: 344 fieldset: C2APB1ENR1 - name: C2APB1ENR2 description: CPU2 APB1 peripheral clock enable register 2 [dual core device only] byte_offset: 348 fieldset: C2APB1ENR2 - name: C2APB2ENR description: CPU2 APB2 peripheral clock enable register [dual core device only] byte_offset: 352 fieldset: C2APB2ENR - name: C2APB3ENR description: CPU2 APB3 peripheral clock enable register [dual core device only] byte_offset: 356 fieldset: C2APB3ENR - name: C2AHB1SMENR description: CPU2 AHB1 peripheral clocks enable in Sleep modes register [dual core device only] byte_offset: 360 fieldset: C2AHB1SMENR - name: C2AHB2SMENR description: CPU2 AHB2 peripheral clocks enable in Sleep modes register [dual core device only] byte_offset: 364 fieldset: C2AHB2SMENR - name: C2AHB3SMENR description: CPU2 AHB3 peripheral clocks enable in Sleep mode register [dual core device only] byte_offset: 368 fieldset: C2AHB3SMENR - name: C2APB1SMENR1 description: CPU2 APB1 peripheral clocks enable in Sleep mode register 1 [dual core device only] byte_offset: 376 fieldset: C2APB1SMENR1 - name: C2APB1SMENR2 description: CPU2 APB1 peripheral clocks enable in Sleep mode register 2 [dual core device only] byte_offset: 380 fieldset: C2APB1SMENR2 - name: C2APB2SMENR description: CPU2 APB2 peripheral clocks enable in Sleep mode register [dual core device only] byte_offset: 384 fieldset: C2APB2SMENR - name: C2APB3SMENR description: CPU2 APB3 peripheral clock enable in Sleep mode register [dual core device only] byte_offset: 388 fieldset: C2APB3SMENR fieldset/AHB1ENR: description: AHB1 peripheral clock enable register fields: - name: DMA1EN description: CPU1 DMA1 clock enable bit_offset: 0 bit_size: 1 - name: DMA2EN description: CPU1 DMA2 clock enable bit_offset: 1 bit_size: 1 - name: DMAMUX1EN description: CPU1 DMAMUX1 clock enable bit_offset: 2 bit_size: 1 - name: CRCEN description: CPU1 CRC clock enable bit_offset: 12 bit_size: 1 fieldset/AHB1RSTR: description: AHB1 peripheral reset register fields: - name: DMA1RST description: DMA1 reset bit_offset: 0 bit_size: 1 - name: DMA2RST description: DMA2 reset bit_offset: 1 bit_size: 1 - name: DMAMUX1RST description: DMAMUX1 reset bit_offset: 2 bit_size: 1 - name: CRCRST description: CRC reset bit_offset: 12 bit_size: 1 fieldset/AHB1SMENR: description: AHB1 peripheral clocks enable in Sleep modes register fields: - name: DMA1SMEN description: DMA1 clock enable during CPU1 CSleep mode. bit_offset: 0 bit_size: 1 - name: DMA2SMEN description: DMA2 clock enable during CPU1 CSleep mode bit_offset: 1 bit_size: 1 - name: DMAMUX1SMEN description: DMAMUX1 clock enable during CPU1 CSleep mode. bit_offset: 2 bit_size: 1 - name: CRCSMEN description: CRC clock enable during CPU1 CSleep mode. bit_offset: 12 bit_size: 1 fieldset/AHB2ENR: description: AHB2 peripheral clock enable register fields: - name: GPIOAEN description: CPU1 IO port A clock enable bit_offset: 0 bit_size: 1 - name: GPIOBEN description: CPU1 IO port B clock enable bit_offset: 1 bit_size: 1 - name: GPIOCEN description: CPU1 IO port C clock enable bit_offset: 2 bit_size: 1 - name: GPIOHEN description: CPU1 IO port H clock enable bit_offset: 7 bit_size: 1 fieldset/AHB2RSTR: description: AHB2 peripheral reset register fields: - name: GPIOARST description: IO port A reset bit_offset: 0 bit_size: 1 - name: GPIOBRST description: IO port B reset bit_offset: 1 bit_size: 1 - name: GPIOCRST description: IO port C reset bit_offset: 2 bit_size: 1 - name: GPIOHRST description: IO port H reset bit_offset: 7 bit_size: 1 fieldset/AHB2SMENR: description: AHB2 peripheral clocks enable in Sleep modes register fields: - name: GPIOASMEN description: IO port A clock enable during CPU1 CSleep mode. bit_offset: 0 bit_size: 1 - name: GPIOBSMEN description: IO port B clock enable during CPU1 CSleep mode. bit_offset: 1 bit_size: 1 - name: GPIOCSMEN description: IO port C clock enable during CPU1 CSleep mode. bit_offset: 2 bit_size: 1 - name: GPIOHSMEN description: IO port H clock enable during CPU1 CSleep mode. bit_offset: 7 bit_size: 1 fieldset/AHB3ENR: description: AHB3 peripheral clock enable register fields: - name: PKAEN description: PKAEN bit_offset: 16 bit_size: 1 - name: AESEN description: AESEN bit_offset: 17 bit_size: 1 - name: RNGEN description: RNGEN bit_offset: 18 bit_size: 1 - name: HSEMEN description: HSEMEN bit_offset: 19 bit_size: 1 - name: IPCCEN description: IPCCEN bit_offset: 20 bit_size: 1 - name: FLASHEN description: CPU1 Flash interface clock enable bit_offset: 25 bit_size: 1 fieldset/AHB3RSTR: description: AHB3 peripheral reset register fields: - name: PKARST description: PKARST bit_offset: 16 bit_size: 1 - name: AESRST description: AESRST bit_offset: 17 bit_size: 1 - name: RNGRST description: RNGRST bit_offset: 18 bit_size: 1 - name: HSEMRST description: HSEMRST bit_offset: 19 bit_size: 1 - name: IPCCRST description: IPCCRST bit_offset: 20 bit_size: 1 - name: FLASHRST description: Flash interface reset bit_offset: 25 bit_size: 1 fieldset/AHB3SMENR: description: AHB3 peripheral clocks enable in Sleep and Stop modes register fields: - name: PKASMEN description: PKA accelerator clock enable during CPU1 CSleep mode. bit_offset: 16 bit_size: 1 - name: AESSMEN description: AES accelerator clock enable during CPU1 CSleep mode. bit_offset: 17 bit_size: 1 - name: RNGSMEN description: True RNG clocks enable during CPU1 Csleep and CStop modes bit_offset: 18 bit_size: 1 - name: SRAM1SMEN description: SRAM1 interface clock enable during CPU1 CSleep mode. bit_offset: 23 bit_size: 1 - name: SRAM2SMEN description: SRAM2 memory interface clock enable during CPU1 CSleep mode bit_offset: 24 bit_size: 1 - name: FLASHSMEN description: Flash interface clock enable during CPU1 CSleep mode. bit_offset: 25 bit_size: 1 fieldset/APB1ENR1: description: APB1 peripheral clock enable register 1 fields: - name: TIM2EN description: CPU1 TIM2 timer clock enable bit_offset: 0 bit_size: 1 - name: RTCAPBEN description: CPU1 RTC APB clock enable bit_offset: 10 bit_size: 1 - name: WWDGEN description: CPU1 Window watchdog clock enable bit_offset: 11 bit_size: 1 - name: SPI2EN description: CPU1 SPI2 clock enable bit_offset: 14 bit_size: 1 - name: USART2EN description: CPU1 USART2 clock enable bit_offset: 17 bit_size: 1 - name: I2C1EN description: CPU1 I2C1 clocks enable bit_offset: 21 bit_size: 1 - name: I2C2EN description: CPU1 I2C2 clocks enable bit_offset: 22 bit_size: 1 - name: I2C3EN description: CPU1 I2C3 clocks enable bit_offset: 23 bit_size: 1 - name: DAC1EN description: CPU1 DAC1 clock enable bit_offset: 29 bit_size: 1 - name: LPTIM1EN description: CPU1 Low power timer 1 clocks enable bit_offset: 31 bit_size: 1 fieldset/APB1ENR2: description: APB1 peripheral clock enable register 2 fields: - name: LPUART1EN description: CPU1 Low power UART 1 clocks enable bit_offset: 0 bit_size: 1 - name: LPTIM2EN description: CPU1 Low power timer 2 clocks enable bit_offset: 5 bit_size: 1 - name: LPTIM3EN description: CPU1 Low power timer 3 clocks enable bit_offset: 6 bit_size: 1 fieldset/APB1RSTR1: description: APB1 peripheral reset register 1 fields: - name: TIM2RST description: TIM2 timer reset bit_offset: 0 bit_size: 1 - name: SPI2RST description: SPI2 reset bit_offset: 14 bit_size: 1 - name: USART2RST description: USART2 reset bit_offset: 17 bit_size: 1 - name: I2C1RST description: I2C1 reset bit_offset: 21 bit_size: 1 - name: I2C2RST description: I2C2 reset bit_offset: 22 bit_size: 1 - name: I2C3RST description: I2C3 reset bit_offset: 23 bit_size: 1 - name: DACRST description: DAC1 reset bit_offset: 29 bit_size: 1 - name: LPTIM1RST description: Low Power Timer 1 reset bit_offset: 31 bit_size: 1 fieldset/APB1RSTR2: description: APB1 peripheral reset register 2 fields: - name: LPUART1RST description: Low-power UART 1 reset bit_offset: 0 bit_size: 1 - name: LPTIM2RST description: Low-power timer 2 reset bit_offset: 5 bit_size: 1 - name: LPTIM3RST description: Low-power timer 3 reset bit_offset: 6 bit_size: 1 fieldset/APB1SMENR1: description: APB1 peripheral clocks enable in Sleep mode register 1 fields: - name: TIM2SMEN description: TIM2 timer clock enable during CPU1 CSleep mode. bit_offset: 0 bit_size: 1 - name: RTCAPBSMEN description: RTC bus clock enable during CPU1 CSleep mode. bit_offset: 10 bit_size: 1 - name: WWDGSMEN description: Window watchdog clocks enable during CPU1 CSleep mode. bit_offset: 11 bit_size: 1 - name: SPI2SMEN description: SPI2 clock enable during CPU1 CSleep mode. bit_offset: 14 bit_size: 1 - name: USART2SMEN description: USART2 clock enable during CPU1 CSleep mode. bit_offset: 17 bit_size: 1 - name: I2C1SMEN description: I2C1 clock enable during CPU1 Csleep and CStop modes bit_offset: 21 bit_size: 1 - name: I2C2SMEN description: I2C2 clock enable during CPU1 Csleep and CStop modes bit_offset: 22 bit_size: 1 - name: I2C3SMEN description: I2C3 clock enable during CPU1 Csleep and CStop modes bit_offset: 23 bit_size: 1 - name: DACSMEN description: DAC1 clock enable during CPU1 CSleep mode. bit_offset: 29 bit_size: 1 - name: LPTIM1SMEN description: Low power timer 1 clock enable during CPU1 Csleep and CStop mode bit_offset: 31 bit_size: 1 fieldset/APB1SMENR2: description: APB1 peripheral clocks enable in Sleep mode register 2 fields: - name: LPUART1SMEN description: Low power UART 1 clock enable during CPU1 Csleep and CStop modes. bit_offset: 0 bit_size: 1 - name: LPTIM2SMEN description: Low power timer 2 clock enable during CPU1 Csleep and CStop modes bit_offset: 5 bit_size: 1 - name: LPTIM3SMEN description: Low power timer 3 clock enable during CPU1 Csleep and CStop modes bit_offset: 6 bit_size: 1 fieldset/APB2ENR: description: APB2 peripheral clock enable register fields: - name: ADCEN description: CPU1 ADC clocks enable bit_offset: 9 bit_size: 1 - name: TIM1EN description: CPU1 TIM1 timer clock enable bit_offset: 11 bit_size: 1 - name: SPI1EN description: CPU1 SPI1 clock enable bit_offset: 12 bit_size: 1 - name: USART1EN description: CPU1 USART1clocks enable bit_offset: 14 bit_size: 1 - name: TIM16EN description: CPU1 TIM16 timer clock enable bit_offset: 17 bit_size: 1 - name: TIM17EN description: CPU1 TIM17 timer clock enable bit_offset: 18 bit_size: 1 fieldset/APB2RSTR: description: APB2 peripheral reset register fields: - name: ADCRST description: ADC reset bit_offset: 9 bit_size: 1 - name: TIM1RST description: TIM1 timer reset bit_offset: 11 bit_size: 1 - name: SPI1RST description: SPI1 reset bit_offset: 12 bit_size: 1 - name: USART1RST description: USART1 reset bit_offset: 14 bit_size: 1 - name: TIM16RST description: TIM16 timer reset bit_offset: 17 bit_size: 1 - name: TIM17RST description: TIM17 timer reset bit_offset: 18 bit_size: 1 fieldset/APB2SMENR: description: APB2 peripheral clocks enable in Sleep mode register fields: - name: ADCSMEN description: ADC clocks enable during CPU1 Csleep and CStop modes bit_offset: 9 bit_size: 1 - name: TIM1SMEN description: TIM1 timer clock enable during CPU1 CSleep mode. bit_offset: 11 bit_size: 1 - name: SPI1SMEN description: SPI1 clock enable during CPU1 CSleep mode. bit_offset: 12 bit_size: 1 - name: USART1SMEN description: USART1 clock enable during CPU1 Csleep and CStop modes. bit_offset: 14 bit_size: 1 - name: TIM16SMEN description: TIM16 timer clock enable during CPU1 CSleep mode. bit_offset: 17 bit_size: 1 - name: TIM17SMEN description: TIM17 timer clock enable during CPU1 CSleep mode. bit_offset: 18 bit_size: 1 fieldset/APB3ENR: description: APB3 peripheral clock enable register fields: - name: SUBGHZSPIEN description: sub-GHz radio SPI clock enable bit_offset: 0 bit_size: 1 fieldset/APB3RSTR: description: APB3 peripheral reset register fields: - name: SUBGHZSPIRST description: Sub-GHz radio SPI reset bit_offset: 0 bit_size: 1 fieldset/APB3SMENR: description: APB3 peripheral clock enable in Sleep mode register fields: - name: SUBGHZSPISMEN description: Sub-GHz radio SPI clock enable during Sleep and Stop modes bit_offset: 0 bit_size: 1 fieldset/BDCR: description: Backup domain control register fields: - name: LSEON description: LSE oscillator enable bit_offset: 0 bit_size: 1 - name: LSERDY description: LSE oscillator ready bit_offset: 1 bit_size: 1 - name: LSEBYP description: LSE oscillator bypass bit_offset: 2 bit_size: 1 - name: LSEDRV description: LSE oscillator drive capability bit_offset: 3 bit_size: 2 enum: LSEDRV - name: LSECSSON description: CSS on LSE enable bit_offset: 5 bit_size: 1 - name: LSECSSD description: CSS on LSE failure Detection bit_offset: 6 bit_size: 1 - name: LSESYSEN description: LSE system clock enable bit_offset: 7 bit_size: 1 - name: RTCSEL description: RTC clock source selection bit_offset: 8 bit_size: 2 enum: RTCSEL - name: LSESYSRDY description: LSE system clock ready bit_offset: 11 bit_size: 1 - name: RTCEN description: RTC clock enable bit_offset: 15 bit_size: 1 - name: BDRST description: Backup domain software reset bit_offset: 16 bit_size: 1 - name: LSCOEN description: Low speed clock output enable bit_offset: 24 bit_size: 1 - name: LSCOSEL description: Low speed clock output selection bit_offset: 25 bit_size: 1 fieldset/C2AHB1ENR: description: CPU2 AHB1 peripheral clock enable register fields: - name: DMA1EN description: CPU2 DMA1 clock enable bit_offset: 0 bit_size: 1 - name: DMA2EN description: CPU2 DMA2 clock enable bit_offset: 1 bit_size: 1 - name: DMAMUX1EN description: CPU2 DMAMUX1 clock enable bit_offset: 2 bit_size: 1 - name: CRCEN description: CPU2 CRC clock enable bit_offset: 12 bit_size: 1 fieldset/C2AHB1SMENR: description: CPU2 AHB1 peripheral clocks enable in Sleep modes register [dual core device only] fields: - name: DMA1SMEN description: DMA1 clock enable during CPU2 CSleep mode. bit_offset: 0 bit_size: 1 - name: DMA2SMEN description: DMA2 clock enable during CPU2 CSleep mode. bit_offset: 1 bit_size: 1 - name: DMAMUX1SMEN description: DMAMUX1 clock enable during CPU2 CSleep mode. bit_offset: 2 bit_size: 1 - name: CRCSMEN description: CRC clock enable during CPU2 CSleep mode. bit_offset: 12 bit_size: 1 fieldset/C2AHB2ENR: description: CPU2 AHB2 peripheral clock enable register fields: - name: GPIOAEN description: CPU2 IO port A clock enable bit_offset: 0 bit_size: 1 - name: GPIOBEN description: CPU2 IO port B clock enable bit_offset: 1 bit_size: 1 - name: GPIOCEN description: CPU2 IO port C clock enable bit_offset: 2 bit_size: 1 - name: GPIOHEN description: CPU2 IO port H clock enable bit_offset: 7 bit_size: 1 fieldset/C2AHB2SMENR: description: CPU2 AHB2 peripheral clocks enable in Sleep modes register [dual core device only] fields: - name: GPIOASMEN description: IO port A clock enable during CPU2 CSleep mode. bit_offset: 0 bit_size: 1 - name: GPIOBSMEN description: IO port B clock enable during CPU2 CSleep mode. bit_offset: 1 bit_size: 1 - name: GPIOCSMEN description: IO port C clock enable during CPU2 CSleep mode. bit_offset: 2 bit_size: 1 - name: GPIOHSMEN description: IO port H clock enable during CPU2 CSleep mode. bit_offset: 7 bit_size: 1 fieldset/C2AHB3ENR: description: CPU2 AHB3 peripheral clock enable register [dual core device only] fields: - name: PKAEN description: CPU2 PKA accelerator clock enable bit_offset: 16 bit_size: 1 - name: AESEN description: CPU2 AES accelerator clock enable bit_offset: 17 bit_size: 1 - name: RNGEN description: CPU2 True RNG clocks enable bit_offset: 18 bit_size: 1 - name: HSEMEN description: CPU2 HSEM clock enable bit_offset: 19 bit_size: 1 - name: IPCCEN description: CPU2 IPCC interface clock enable bit_offset: 20 bit_size: 1 - name: FLASHEN description: CPU2 Flash interface clock enable bit_offset: 25 bit_size: 1 fieldset/C2AHB3SMENR: description: CPU2 AHB3 peripheral clocks enable in Sleep mode register [dual core device only] fields: - name: PKASMEN description: PKA accelerator clock enable during CPU2 CSleep mode. bit_offset: 16 bit_size: 1 - name: AESSMEN description: AES accelerator clock enable during CPU2 CSleep mode. bit_offset: 17 bit_size: 1 - name: RNGSMEN description: True RNG clock enable during CPU2 CSleep and CStop mode. bit_offset: 18 bit_size: 1 - name: SRAM1SMEN description: SRAM1 interface clock enable during CPU2 CSleep mode. bit_offset: 23 bit_size: 1 - name: SRAM2SMEN description: SRAM2 memory interface clock enable during CPU2 CSleep mode. bit_offset: 24 bit_size: 1 - name: FLASHSMEN description: Flash interface clock enable during CPU2 CSleep mode. bit_offset: 25 bit_size: 1 fieldset/C2APB1ENR1: description: CPU2 APB1 peripheral clock enable register 1 [dual core device only] fields: - name: TIM2EN description: CPU2 TIM2 timer clock enable bit_offset: 0 bit_size: 1 - name: RTCAPBEN description: CPU2 RTC APB clock enable bit_offset: 10 bit_size: 1 - name: SPI2EN description: CPU2 SPI2 clock enable bit_offset: 14 bit_size: 1 - name: USART2EN description: CPU2 USART2 clock enable bit_offset: 17 bit_size: 1 - name: I2C1EN description: CPU2 I2C1 clocks enable bit_offset: 21 bit_size: 1 - name: I2C2EN description: CPU2 I2C2 clocks enable bit_offset: 22 bit_size: 1 - name: I2C3EN description: CPU2 I2C3 clocks enable bit_offset: 23 bit_size: 1 - name: DAC1EN description: CPU2 DAC1 clock enable bit_offset: 29 bit_size: 1 - name: LPTIM1EN description: CPU2 Low power timer 1 clocks enable bit_offset: 31 bit_size: 1 fieldset/C2APB1ENR2: description: CPU2 APB1 peripheral clock enable register 2 [dual core device only] fields: - name: LPUART1EN description: CPU2 Low power UART 1 clocks enable bit_offset: 0 bit_size: 1 - name: LPTIM2EN description: CPU2 Low power timer 2 clocks enable bit_offset: 5 bit_size: 1 - name: LPTIM3EN description: CPU2 Low power timer 3 clocks enable bit_offset: 6 bit_size: 1 fieldset/C2APB1SMENR1: description: CPU2 APB1 peripheral clocks enable in Sleep mode register 1 [dual core device only] fields: - name: TIM2SMEN description: TIM2 timer clock enable during CPU2 CSleep mode. bit_offset: 0 bit_size: 1 - name: RTCAPBSMEN description: RTC bus clock enable during CPU2 CSleep mode. bit_offset: 10 bit_size: 1 - name: SPI2SMEN description: SPI2 clock enable during CPU2 CSleep mode. bit_offset: 14 bit_size: 1 - name: USART2SMEN description: USART2 clock enable during CPU2 CSleep mode. bit_offset: 17 bit_size: 1 - name: I2C1SMEN description: I2C1 clock enable during CPU2 CSleep and CStop modes bit_offset: 21 bit_size: 1 - name: I2C2SMEN description: I2C2 clock enable during CPU2 CSleep and CStop modes bit_offset: 22 bit_size: 1 - name: I2C3SMEN description: I2C3 clock enable during CPU2 CSleep and CStop modes bit_offset: 23 bit_size: 1 - name: DAC1SMEN description: DAC1 clock enable during CPU2 CSleep mode. bit_offset: 29 bit_size: 1 - name: LPTIM1SMEN description: Low power timer 1 clock enable during CPU2 CSleep and CStop mode bit_offset: 31 bit_size: 1 fieldset/C2APB1SMENR2: description: CPU2 APB1 peripheral clocks enable in Sleep mode register 2 [dual core device only] fields: - name: LPUART1SMEN description: Low power UART 1 clock enable during CPU2 CSleep and CStop mode bit_offset: 0 bit_size: 1 - name: LPTIM2SMEN description: Low power timer 2 clocks enable during CPU2 CSleep and CStop modes. bit_offset: 5 bit_size: 1 - name: LPTIM3SMEN description: Low power timer 3 clocks enable during CPU2 CSleep and CStop modes. bit_offset: 6 bit_size: 1 fieldset/C2APB2ENR: description: CPU2 APB2 peripheral clock enable register [dual core device only] fields: - name: ADCEN description: ADC clocks enable bit_offset: 9 bit_size: 1 - name: TIM1EN description: CPU2 TIM1 timer clock enable bit_offset: 11 bit_size: 1 - name: SPI1EN description: CPU2 SPI1 clock enable bit_offset: 12 bit_size: 1 - name: USART1EN description: CPU2 USART1clocks enable bit_offset: 14 bit_size: 1 - name: TIM16EN description: CPU2 TIM16 timer clock enable bit_offset: 17 bit_size: 1 - name: TIM17EN description: CPU2 TIM17 timer clock enable bit_offset: 18 bit_size: 1 fieldset/C2APB2SMENR: description: CPU2 APB2 peripheral clocks enable in Sleep mode register [dual core device only] fields: - name: ADCSMEN description: ADC clocks enable during CPU2 Csleep and CStop modes bit_offset: 9 bit_size: 1 - name: TIM1SMEN description: TIM1 timer clock enable during CPU2 CSleep mode bit_offset: 11 bit_size: 1 - name: SPI1SMEN description: SPI1 clock enable during CPU2 CSleep mode bit_offset: 12 bit_size: 1 - name: USART1SMEN description: USART1clock enable during CPU2 CSleep and CStop mode bit_offset: 14 bit_size: 1 - name: TIM16SMEN description: TIM16 timer clock enable during CPU2 CSleep mode bit_offset: 17 bit_size: 1 - name: TIM17SMEN description: TIM17 timer clock enable during CPU2 CSleep mode bit_offset: 18 bit_size: 1 fieldset/C2APB3ENR: description: CPU2 APB3 peripheral clock enable register [dual core device only] fields: - name: SUBGHZSPIEN description: CPU2 sub-GHz radio SPI clock enable bit_offset: 0 bit_size: 1 fieldset/C2APB3SMENR: description: CPU2 APB3 peripheral clock enable in Sleep mode register [dual core device only] fields: - name: SUBGHZSPISMEN description: sub-GHz radio SPI clock enable during CPU2 CSleep and CStop modes bit_offset: 0 bit_size: 1 fieldset/CCIPR: description: Peripherals independent clock configuration register fields: - name: USART1SEL description: USART1 clock source selection bit_offset: 0 bit_size: 2 - name: USART2SEL description: USART2 clock source selection bit_offset: 2 bit_size: 2 - name: SPI2SEL description: SPI2 I2S clock source selection bit_offset: 8 bit_size: 2 - name: LPUART1SEL description: LPUART1 clock source selection bit_offset: 10 bit_size: 2 - name: I2C1SEL description: I2C1 clock source selection bit_offset: 12 bit_size: 2 - name: I2C2SEL description: I2C2 clock source selection bit_offset: 14 bit_size: 2 - name: I2C3SEL description: I2C3 clock source selection bit_offset: 16 bit_size: 2 - name: LPTIM1SEL description: Low power timer 1 clock source selection bit_offset: 18 bit_size: 2 - name: LPTIM2SEL description: Low power timer 2 clock source selection bit_offset: 20 bit_size: 2 - name: LPTIM3SEL description: Low power timer 3 clock source selection bit_offset: 22 bit_size: 2 - name: ADCSEL description: ADC clock source selection bit_offset: 28 bit_size: 2 enum: ADCSEL - name: RNGSEL description: RNG clock source selection bit_offset: 30 bit_size: 2 fieldset/CFGR: description: Clock configuration register fields: - name: SW description: System clock switch bit_offset: 0 bit_size: 2 - name: SWS description: System clock switch status bit_offset: 2 bit_size: 2 - name: HPRE description: HCLK1 prescaler (CPU1, AHB1, AHB2, and SRAM1.) bit_offset: 4 bit_size: 4 enum: HPRE - name: PPRE1 description: PCLK1 low-speed prescaler (APB1) bit_offset: 8 bit_size: 3 enum: PPRE - name: PPRE2 description: PCLK2 high-speed prescaler (APB2) bit_offset: 11 bit_size: 3 enum: PPRE - name: STOPWUCK description: Wakeup from Stop and CSS backup clock selection bit_offset: 15 bit_size: 1 - name: HPREF description: HCLK1 prescaler flag (CPU1, AHB1, AHB2, and SRAM1) bit_offset: 16 bit_size: 1 - name: PPRE1F description: PCLK1 prescaler flag (APB1) bit_offset: 17 bit_size: 1 - name: PPRE2F description: PCLK2 prescaler flag (APB2) bit_offset: 18 bit_size: 1 - name: MCOSEL description: Microcontroller clock output bit_offset: 24 bit_size: 4 enum: MCOSEL - name: MCOPRE description: Microcontroller clock output prescaler bit_offset: 28 bit_size: 3 enum: MCOPRE fieldset/CICR: description: Clock interrupt clear register fields: - name: LSIRDYC description: LSI ready interrupt clear bit_offset: 0 bit_size: 1 - name: LSERDYC description: LSE ready interrupt clear bit_offset: 1 bit_size: 1 - name: MSIRDYC description: MSI ready interrupt clear bit_offset: 2 bit_size: 1 - name: HSIRDYC description: HSI16 ready interrupt clear bit_offset: 3 bit_size: 1 - name: HSERDYC description: HSE32 ready interrupt clear bit_offset: 4 bit_size: 1 - name: PLLRDYC description: PLL ready interrupt clear bit_offset: 5 bit_size: 1 - name: CSSC description: HSE32 Clock security system interrupt clear bit_offset: 8 bit_size: 1 - name: LSECSSC description: LSE Clock security system interrupt clear bit_offset: 9 bit_size: 1 fieldset/CIER: description: Clock interrupt enable register fields: - name: LSIRDYIE description: LSI ready interrupt enable bit_offset: 0 bit_size: 1 - name: LSERDYIE description: LSE ready interrupt enable bit_offset: 1 bit_size: 1 - name: MSIRDYIE description: MSI ready interrupt enable bit_offset: 2 bit_size: 1 - name: HSIRDYIE description: HSI16 ready interrupt enable bit_offset: 3 bit_size: 1 - name: HSERDYIE description: HSE32 ready interrupt enable bit_offset: 4 bit_size: 1 - name: PLLRDYIE description: PLL ready interrupt enable bit_offset: 5 bit_size: 1 - name: LSECSSIE description: LSE clock security system interrupt enable bit_offset: 9 bit_size: 1 fieldset/CIFR: description: Clock interrupt flag register fields: - name: LSIRDYF description: LSI ready interrupt flag bit_offset: 0 bit_size: 1 - name: LSERDYF description: LSE ready interrupt flag bit_offset: 1 bit_size: 1 - name: MSIRDYF description: MSI ready interrupt flag bit_offset: 2 bit_size: 1 - name: HSIRDYF description: HSI16 ready interrupt flag bit_offset: 3 bit_size: 1 - name: HSERDYF description: HSE32 ready interrupt flag bit_offset: 4 bit_size: 1 - name: PLLRDYF description: PLL ready interrupt flag bit_offset: 5 bit_size: 1 - name: CSSF description: HSE32 Clock security system interrupt flag bit_offset: 8 bit_size: 1 - name: LSECSSF description: LSE Clock security system interrupt flag bit_offset: 9 bit_size: 1 fieldset/CR: description: Clock control register fields: - name: MSION description: MSI clock enable bit_offset: 0 bit_size: 1 - name: MSIRDY description: MSI clock ready flag (After reset this bit will be read 1 once the MSI is ready) bit_offset: 1 bit_size: 1 - name: MSIPLLEN description: MSI clock PLL enable bit_offset: 2 bit_size: 1 - name: MSIRGSEL description: MSI range control selection bit_offset: 3 bit_size: 1 - name: MSIRANGE description: MSI clock ranges bit_offset: 4 bit_size: 4 - name: HSION description: HSI16 clock enable bit_offset: 8 bit_size: 1 - name: HSIKERON description: HSI16 always enable for peripheral kernel clocks. bit_offset: 9 bit_size: 1 - name: HSIRDY description: HSI16 clock ready flag. (After wakeup from Stop this bit will be read 1 once the HSI16 is ready) bit_offset: 10 bit_size: 1 - name: HSIASFS description: HSI16 automatic start from Stop bit_offset: 11 bit_size: 1 - name: HSIKERDY description: HSI16 kernel clock ready flag for peripherals requests. bit_offset: 12 bit_size: 1 - name: HSEON description: HSE32 clock enable bit_offset: 16 bit_size: 1 - name: HSERDY description: HSE32 clock ready flag bit_offset: 17 bit_size: 1 - name: CSSON description: HSE32 Clock security system enable bit_offset: 19 bit_size: 1 - name: HSEPRE description: HSE32 sysclk prescaler bit_offset: 20 bit_size: 1 - name: HSEBYPPWR description: Enable HSE32 VDDTCXO output on package pin PB0-VDDTCXO. bit_offset: 21 bit_size: 1 - name: PLLON description: Main PLL enable bit_offset: 24 bit_size: 1 - name: PLLRDY description: Main PLL clock ready flag bit_offset: 25 bit_size: 1 fieldset/CSR: description: Control/status register fields: - name: LSION description: LSI oscillator enable bit_offset: 0 bit_size: 1 - name: LSIRDY description: LSI oscillator ready bit_offset: 1 bit_size: 1 - name: LSIPRE description: LSI frequency prescaler bit_offset: 4 bit_size: 1 - name: MSISRANGE description: MSI clock ranges bit_offset: 8 bit_size: 4 - name: RFRSTF description: Radio in reset status flag bit_offset: 14 bit_size: 1 - name: RFRST description: Radio reset bit_offset: 15 bit_size: 1 - name: RMVF description: Remove reset flag bit_offset: 23 bit_size: 1 - name: RFILARSTF description: Radio illegal access flag bit_offset: 24 bit_size: 1 - name: OBLRSTF description: Option byte loader reset flag bit_offset: 25 bit_size: 1 - name: PINRSTF description: Pin reset flag bit_offset: 26 bit_size: 1 - name: BORRSTF description: BOR flag bit_offset: 27 bit_size: 1 - name: SFTRSTF description: Software reset flag bit_offset: 28 bit_size: 1 - name: IWDGRSTF description: Independent window watchdog reset flag bit_offset: 29 bit_size: 1 - name: WWDGRSTF description: Window watchdog reset flag bit_offset: 30 bit_size: 1 - name: LPWRRSTF description: Low-power reset flag bit_offset: 31 bit_size: 1 fieldset/EXTCFGR: description: Extended clock recovery register fields: - name: SHDHPRE description: HCLK3 shared prescaler (AHB3, Flash, and SRAM2) bit_offset: 0 bit_size: 4 - name: C2HPRE description: '[dual core device only] HCLK2 prescaler (CPU2)' bit_offset: 4 bit_size: 4 - name: SHDHPREF description: HCLK3 shared prescaler flag (AHB3, Flash, and SRAM2) bit_offset: 16 bit_size: 1 - name: C2HPREF description: CLK2 prescaler flag (CPU2) bit_offset: 17 bit_size: 1 fieldset/ICSCR: description: Internal clock sources calibration register fields: - name: MSICAL description: MSI clock calibration bit_offset: 0 bit_size: 8 - name: MSITRIM description: MSI clock trimming bit_offset: 8 bit_size: 8 - name: HSICAL description: HSI16 clock calibration bit_offset: 16 bit_size: 8 - name: HSITRIM description: HSI16 clock trimming bit_offset: 24 bit_size: 7 fieldset/PLLCFGR: description: PLL configuration register fields: - name: PLLSRC description: Main PLL entry clock source bit_offset: 0 bit_size: 2 - name: PLLM description: Division factor for the main PLL input clock bit_offset: 4 bit_size: 3 - name: PLLN description: Main PLL multiplication factor for VCO bit_offset: 8 bit_size: 7 - name: PLLPEN description: Main PLL PLLPCLK output enable bit_offset: 16 bit_size: 1 - name: PLLP description: Main PLL division factor for PLLPCLK. bit_offset: 17 bit_size: 5 - name: PLLQEN description: Main PLL PLLQCLK output enable bit_offset: 24 bit_size: 1 - name: PLLQ description: Main PLL division factor for PLLQCLK bit_offset: 25 bit_size: 3 - name: PLLREN description: Main PLL PLLRCLK output enable bit_offset: 28 bit_size: 1 - name: PLLR description: Main PLL division factor for PLLRCLK bit_offset: 29 bit_size: 3 enum/ADCSEL: bit_size: 2 variants: - name: HSI16 description: HSI16 used as ADC clock source value: 1 - name: PLLPCLK description: PLLPCLK used as ADC clock source value: 2 - name: SYSCLK description: SYSCLK used as ADC clock source value: 3 enum/HPRE: bit_size: 4 variants: - name: Div1 description: DCLK not divided value: 0 - name: Div3 description: hclk = SYSCLK divided by 3 value: 1 - name: Div5 description: hclk = SYSCLK divided by 5 value: 2 - name: Div6 description: hclk = SYSCLK divided by 6 value: 5 - name: Div10 description: hclk = SYSCLK divided by 8 value: 6 - name: Div32 description: hclk = SYSCLK divided by 32 value: 7 - name: Div2 description: hclk = SYSCLK divided by 2 value: 8 - name: Div4 description: hclk = SYSCLK divided by 4 value: 9 - name: Div8 description: hclk = SYSCLK divided by 8 value: 10 - name: Div16 description: hclk = SYSCLK divided by 16 value: 11 - name: Div64 description: hclk = SYSCLK divided by 64 value: 12 - name: Div128 description: hclk = SYSCLK divided by 128 value: 13 - name: Div256 description: hclk = SYSCLK divided by 256 value: 14 - name: Div512 description: hclk = SYSCLK divided by 256 value: 15 enum/MCOPRE: bit_size: 3 variants: - name: Div1 description: No division value: 0 - name: Div2 description: Division by 2 value: 1 - name: Div4 description: Division by 4 value: 2 - name: Div8 description: Division by 8 value: 3 - name: Div16 description: Division by 16 value: 4 enum/MCOSEL: bit_size: 4 variants: - name: NoClock description: No clock value: 0 - name: SYSCLK description: SYSCLK clock selected value: 1 - name: MSI description: MSI oscillator clock selected value: 2 - name: HSI16 description: HSI oscillator clock selected value: 3 - name: HSE32 description: HSE32 oscillator clock selected value: 4 - name: PLLRCLK description: Main PLLRCLK clock selected value: 5 - name: LSI description: LSI oscillator clock selected value: 6 - name: LSE description: LSE oscillator clock selected value: 8 - name: PLLPCLK description: Main PLLCLK oscillator clock selected value: 13 - name: PLLQCLK description: Main PLLQCLK oscillator clock selected value: 14 enum/PPRE: bit_size: 3 variants: - name: Div1 description: HCLK not divided value: 0 - name: Div2 description: HCLK divided by 2 value: 4 - name: Div4 description: HCLK divided by 4 value: 5 - name: Div8 description: HCLK divided by 8 value: 6 - name: Div16 description: HCLK divided by 16 value: 7 enum/RTCSEL: bit_size: 2 variants: - name: NoClock description: No clock selected value: 0 - name: LSE description: LSE oscillator clock selected value: 1 - name: LSI description: LSI oscillator clock selected value: 2 - name: HSE description: HSE oscillator clock divided by 32 selected value: 3 enum/LSEDRV: bit_size: 2 variants: - name: Low description: Low driving capability value: 0 - name: MediumLow description: Medium low driving capability value: 1 - name: MediumHigh description: Medium high driving capability value: 2 - name: High description: High driving capability value: 3