block/ADC_COMMON: description: ADC common registers items: - name: CSR description: common status register byte_offset: 0 fieldset: CSR - name: CCR description: common control register byte_offset: 8 fieldset: CCR - name: CDR description: common regular data register for dual mode byte_offset: 12 fieldset: CDR - name: HWCFGR0 description: hardware configuration register byte_offset: 240 fieldset: HWCFGR0 - name: VERR description: version register byte_offset: 244 fieldset: VERR - name: IPDR description: identification register byte_offset: 248 fieldset: IPDR - name: SIDR description: size identification register byte_offset: 252 fieldset: SIDR fieldset/CSR: description: common status register fields: - name: ADRDY_MST description: Master ADC ready This bit is a copy of the ADRDY bit in the corresponding ADC_ISR register. bit_offset: 0 bit_size: 1 - name: EOSMP_MST description: End of Sampling phase flag of the master ADC This bit is a copy of the EOSMP bit in the corresponding ADC_ISR register. bit_offset: 1 bit_size: 1 - name: EOC_MST description: End of regular conversion of the master ADC This bit is a copy of the EOC bit in the corresponding ADC_ISR register. bit_offset: 2 bit_size: 1 - name: EOS_MST description: End of regular sequence flag of the master ADC This bit is a copy of the EOS bit in the corresponding ADC_ISR register. bit_offset: 3 bit_size: 1 - name: OVR_MST description: Overrun flag of the master ADC This bit is a copy of the OVR bit in the corresponding ADC_ISR register. bit_offset: 4 bit_size: 1 - name: JEOC_MST description: End of injected conversion flag of the master ADC This bit is a copy of the JEOC bit in the corresponding ADC_ISR register. bit_offset: 5 bit_size: 1 - name: JEOS_MST description: End of injected sequence flag of the master ADC This bit is a copy of the JEOS bit in the corresponding ADC_ISR register. bit_offset: 6 bit_size: 1 - name: AWD1_MST description: Analog watchdog 1 flag of the master ADC This bit is a copy of the AWD1 bit in the corresponding ADC_ISR register. bit_offset: 7 bit_size: 1 - name: AWD2_MST description: Analog watchdog 2 flag of the master ADC This bit is a copy of the AWD2 bit in the corresponding ADC_ISR register. bit_offset: 8 bit_size: 1 - name: AWD3_MST description: Analog watchdog 3 flag of the master ADC This bit is a copy of the AWD3 bit in the corresponding ADC_ISR register. bit_offset: 9 bit_size: 1 - name: JQOVF_MST description: Injected Context Queue Overflow flag of the master ADC This bit is a copy of the JQOVF bit in the corresponding ADC_ISR register. bit_offset: 10 bit_size: 1 - name: ADRDY_SLV description: Slave ADC ready This bit is a copy of the ADRDY bit in the corresponding ADC_ISR register. bit_offset: 16 bit_size: 1 - name: EOSMP_SLV description: End of Sampling phase flag of the slave ADC This bit is a copy of the EOSMP2 bit in the corresponding ADC_ISR register. bit_offset: 17 bit_size: 1 - name: EOC_SLV description: End of regular conversion of the slave ADC This bit is a copy of the EOC bit in the corresponding ADC_ISR register. bit_offset: 18 bit_size: 1 - name: EOS_SLV description: End of regular sequence flag of the slave ADC. This bit is a copy of the EOS bit in the corresponding ADC_ISR register. bit_offset: 19 bit_size: 1 - name: OVR_SLV description: Overrun flag of the slave ADC This bit is a copy of the OVR bit in the corresponding ADC_ISR register. bit_offset: 20 bit_size: 1 - name: JEOC_SLV description: End of injected conversion flag of the slave ADC This bit is a copy of the JEOC bit in the corresponding ADC_ISR register. bit_offset: 21 bit_size: 1 - name: JEOS_SLV description: End of injected sequence flag of the slave ADC This bit is a copy of the JEOS bit in the corresponding ADC_ISR register. bit_offset: 22 bit_size: 1 - name: AWD1_SLV description: Analog watchdog 1 flag of the slave ADC This bit is a copy of the AWD1 bit in the corresponding ADC_ISR register. bit_offset: 23 bit_size: 1 - name: AWD2_SLV description: Analog watchdog 2 flag of the slave ADC This bit is a copy of the AWD2 bit in the corresponding ADC_ISR register. bit_offset: 24 bit_size: 1 - name: AWD3_SLV description: Analog watchdog 3 flag of the slave ADC This bit is a copy of the AWD3 bit in the corresponding ADC_ISR register. bit_offset: 25 bit_size: 1 - name: JQOVF_SLV description: Injected Context Queue Overflow flag of the slave ADC This bit is a copy of the JQOVF bit in the corresponding ADC_ISR register. bit_offset: 26 bit_size: 1 fieldset/CCR: description: common control register fields: - name: CKMODE description: 'ADC clock mode These bits are set and cleared by software to define the ADC clock scheme (which is common to both master and slave ADCs): In all synchronous clock modes, there is no jitter in the delay from a timer trigger to the start of a conversion. Note: The software is allowed to write these bits only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0).' bit_offset: 16 bit_size: 2 - name: PRESC description: 'ADC prescaler These bits are set and cleared by software to select the frequency of the clock to the ADC. The clock is common for all the ADCs. other: reserved Note: The software is allowed to write these bits only when the ADC is disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0). The ADC prescaler value is applied only when CKMODE[1:0] = 0b00.' bit_offset: 18 bit_size: 4 - name: VREFEN description: VREFINT enable This bit is set and cleared by software to enable/disable the VREFINT channel bit_offset: 22 bit_size: 1 - name: TSEN description: VSENSE enable This bit is set and cleared by software to control VSENSE bit_offset: 23 bit_size: 1 - name: VBATEN description: VBAT enable This bit is set and cleared by software to control bit_offset: 24 bit_size: 1 fieldset/CDR: description: common regular data register for dual mode fields: - name: RDATA_MST description: Regular data of the master ADC. In dual mode, these bits contain the regular data of the master ADC. Refer to . The data alignment is applied as described in offset (ADC_DR, OFFSET, OFFSET_CH, ALIGN)) In MDMA = 0b11 mode, bits 15:8 contains SLV_ADC_DR[7:0], bits 7:0 contains MST_ADC_DR[7:0]. bit_offset: 0 bit_size: 16 - name: RDATA_SLV description: Regular data of the slave ADC In dual mode, these bits contain the regular data of the slave ADC. Refer to Dual ADC modes. The data alignment is applied as described in offset (ADC_DR, OFFSET, OFFSET_CH, ALIGN)). bit_offset: 16 bit_size: 16 fieldset/HWCFGR0: description: hardware configuration register fields: - name: ADCNUM description: Number of ADCs implemented bit_offset: 0 bit_size: 4 - name: MULPIPE description: Number of pipeline stages bit_offset: 4 bit_size: 4 - name: OPBITS description: 'Number of option bits 0002: 2 option bits implemented in the ADC option register (ADC_OR) at address offset 0xC8.' bit_offset: 8 bit_size: 4 - name: IDLEVALUE description: Idle value for non-selected channels bit_offset: 12 bit_size: 4 fieldset/VERR: description: version register fields: - name: MINREV description: 'Minor revision These bits returns the ADC IP minor revision 0002: Major revision = X.2.' bit_offset: 0 bit_size: 4 - name: MAJREV description: Major revision These bits returns the ADC IP major revision bit_offset: 4 bit_size: 4 fieldset/IPDR: description: identification register fields: - name: ID description: 'Peripheral identifier These bits returns the ADC identifier. ID[31:0] = 0x0011 0006: c7amba_aditf5_90_v1.' bit_offset: 0 bit_size: 32 fieldset/SIDR: description: size identification register fields: - name: SID description: 'Size Identification SID[31:8]: fixed code that characterizes the ADC_SIDR register. This field is always read at 0xA3C5DD. SID[7:0]: read-only numeric field that returns the address offset (in Kbytes) of the identification registers from the IP base address:.' bit_offset: 0 bit_size: 32