--- block/RCC: description: Reset and clock control items: - name: CR description: "RCC clock control register " byte_offset: 0 fieldset: CR - name: ICSCR1 description: "RCC internal clock sources calibration register 1 " byte_offset: 8 fieldset: ICSCR1 - name: ICSCR2 description: "RCC internal clock sources calibration register 2 " byte_offset: 12 fieldset: ICSCR2 - name: ICSCR3 description: "RCC internal clock sources calibration register 3 " byte_offset: 16 fieldset: ICSCR3 - name: CRRCR description: "RCC clock recovery RC register " byte_offset: 20 fieldset: CRRCR - name: CFGR1 description: "RCC clock configuration register 1 " byte_offset: 28 fieldset: CFGR1 - name: CFGR2 description: "RCC clock configuration register 2 " byte_offset: 32 fieldset: CFGR2 - name: CFGR3 description: "RCC clock configuration register 3 " byte_offset: 36 fieldset: CFGR3 - name: PLL1CFGR description: "RCC PLL1 configuration register " byte_offset: 40 fieldset: PLL1CFGR - name: PLL2CFGR description: "RCC PLL2 configuration register " byte_offset: 44 fieldset: PLL2CFGR - name: PLL3CFGR description: "RCC PLL3 configuration register " byte_offset: 48 fieldset: PLL3CFGR - name: PLL1DIVR description: "RCC PLL1 dividers register " byte_offset: 52 fieldset: PLL1DIVR - name: PLL1FRACR description: "RCC PLL1 fractional divider register " byte_offset: 56 fieldset: PLL1FRACR - name: PLL2DIVR description: "RCC PLL2 dividers configuration register " byte_offset: 60 fieldset: PLL2DIVR - name: PLL2FRACR description: "RCC PLL2 fractional divider register " byte_offset: 64 fieldset: PLL2FRACR - name: PLL3DIVR description: "RCC PLL3 dividers configuration register " byte_offset: 68 fieldset: PLL3DIVR - name: PLL3FRACR description: "RCC PLL3 fractional divider register " byte_offset: 72 fieldset: PLL3FRACR - name: CIER description: "RCC clock interrupt enable register " byte_offset: 80 fieldset: CIER - name: CIFR description: "RCC clock interrupt flag register " byte_offset: 84 fieldset: CIFR - name: CICR description: "RCC clock interrupt clear register " byte_offset: 88 fieldset: CICR - name: AHB1RSTR description: "RCC AHB1 peripheral reset register " byte_offset: 96 fieldset: AHB1RSTR - name: AHB2RSTR1 description: "RCC AHB2 peripheral reset register 1 " byte_offset: 100 fieldset: AHB2RSTR1 - name: AHB2RSTR2 description: "RCC AHB2 peripheral reset register 2 " byte_offset: 104 fieldset: AHB2RSTR2 - name: AHB3RSTR description: "RCC AHB3 peripheral reset register " byte_offset: 108 fieldset: AHB3RSTR - name: APB1RSTR1 description: "RCC APB1 peripheral reset register 1 " byte_offset: 116 fieldset: APB1RSTR1 - name: APB1RSTR2 description: "RCC APB1 peripheral reset register 2 " byte_offset: 120 fieldset: APB1RSTR2 - name: APB2RSTR description: "RCC APB2 peripheral reset register " byte_offset: 124 fieldset: APB2RSTR - name: APB3RSTR description: "RCC APB3 peripheral reset register " byte_offset: 128 fieldset: APB3RSTR - name: AHB1ENR description: "RCC AHB1 peripheral clock enable register " byte_offset: 136 fieldset: AHB1ENR - name: AHB2ENR1 description: "RCC AHB2 peripheral clock enable register 1 " byte_offset: 140 fieldset: AHB2ENR1 - name: AHB2ENR2 description: "RCC AHB2 peripheral clock enable register 2 " byte_offset: 144 fieldset: AHB2ENR2 - name: AHB3ENR description: "RCC AHB3 peripheral clock enable register " byte_offset: 148 fieldset: AHB3ENR - name: APB1ENR1 description: "RCC APB1 peripheral clock enable register 1 " byte_offset: 156 fieldset: APB1ENR1 - name: APB1ENR2 description: "RCC APB1 peripheral clock enable register 2 " byte_offset: 160 fieldset: APB1ENR2 - name: APB2ENR description: "RCC APB2 peripheral clock enable register " byte_offset: 164 fieldset: APB2ENR - name: APB3ENR description: "RCC APB3 peripheral clock enable register " byte_offset: 168 fieldset: APB3ENR - name: AHB1SMENR description: "RCC AHB1 peripheral clocks enable in Sleep and Stop modes register\t" byte_offset: 176 fieldset: AHB1SMENR - name: AHB2SMENR1 description: "RCC AHB2 peripheral clocks enable in Sleep and\tStop modes register 1 " byte_offset: 180 fieldset: AHB2SMENR1 - name: AHB2SMENR2 description: "RCC AHB2 peripheral clocks enable in Sleep and\tStop modes register 2 " byte_offset: 184 fieldset: AHB2SMENR2 - name: AHB3SMENR description: "RCC AHB3 peripheral clocks enable in Sleep and Stop modes register\t" byte_offset: 188 fieldset: AHB3SMENR - name: APB1SMENR1 description: "RCC APB1 peripheral clocks enable in Sleep and Stop modes\tregister 1 " byte_offset: 196 fieldset: APB1SMENR1 - name: APB1SMENR2 description: "RCC APB1 peripheral clocks enable in Sleep and\tStop modes register 2 " byte_offset: 200 fieldset: APB1SMENR2 - name: APB2SMENR description: "RCC APB2 peripheral clocks enable in Sleep and Stop modes register\t" byte_offset: 204 fieldset: APB2SMENR - name: APB3SMENR description: "RCC APB3 peripheral clock enable in Sleep and Stop modes register\t" byte_offset: 208 fieldset: APB3SMENR - name: SRDAMR description: "RCC SmartRun domain peripheral autonomous mode register\t" byte_offset: 216 fieldset: SRDAMR - name: CCIPR1 description: "RCC peripherals independent clock configuration register 1\t" byte_offset: 224 fieldset: CCIPR1 - name: CCIPR2 description: "RCC peripherals independent clock configuration register 2\t" byte_offset: 228 fieldset: CCIPR2 - name: CCIPR3 description: "RCC peripherals independent clock configuration register 3\t" byte_offset: 232 fieldset: CCIPR3 - name: BDCR description: "RCC Backup domain control register " byte_offset: 240 fieldset: BDCR - name: CSR description: "RCC control/status register " byte_offset: 244 fieldset: CSR - name: SECCFGR description: "RCC secure configuration register " byte_offset: 272 fieldset: SECCFGR - name: PRIVCFGR description: "RCC privilege configuration register " byte_offset: 276 fieldset: PRIVCFGR fieldset/AHB1ENR: description: "RCC AHB1 peripheral clock enable register " fields: - name: GPDMA1EN description: "GPDMA1 clock enable\r Set and cleared by software." bit_offset: 0 bit_size: 1 - name: CORDICEN description: "CORDIC clock enable\r Set and cleared by software." bit_offset: 1 bit_size: 1 - name: FMACEN description: "FMAC clock enable\r Set and reset by software." bit_offset: 2 bit_size: 1 - name: MDF1EN description: "MDF1 clock enable\r Set and reset by software." bit_offset: 3 bit_size: 1 - name: FLASHEN description: "FLASH clock enable\r Set and cleared by software. This bit can be disabled only when the Flash memory is in power down mode." bit_offset: 8 bit_size: 1 - name: CRCEN description: "CRC clock enable\r Set and cleared by software." bit_offset: 12 bit_size: 1 - name: TSCEN description: "Touch sensing controller clock enable\r Set and cleared by software." bit_offset: 16 bit_size: 1 - name: RAMCFGEN description: "RAMCFG clock enable\r Set and cleared by software." bit_offset: 17 bit_size: 1 - name: DMA2DEN description: "DMA2D clock enable\r Set and cleared by software." bit_offset: 18 bit_size: 1 - name: GTZC1EN description: "GTZC1 clock enable\r Set and reset by software." bit_offset: 24 bit_size: 1 - name: BKPSRAMEN description: "BKPSRAM clock enable\r Set and reset by software." bit_offset: 28 bit_size: 1 - name: DCACHE1EN description: "DCACHE1 clock enable\r Set and reset by software.\r Note: DCACHE1 clock must be enabled when external memories are accessed through OCTOSPI1, OCTOSPI2 or FSMC, even if the DCACHE1 is bypassed." bit_offset: 30 bit_size: 1 - name: SRAM1EN description: "SRAM1 clock enable\r Set and reset by software." bit_offset: 31 bit_size: 1 fieldset/AHB1RSTR: description: "RCC AHB1 peripheral reset register " fields: - name: GPDMA1RST description: "GPDMA1 reset\r Set and cleared by software." bit_offset: 0 bit_size: 1 - name: CORDICRST description: "CORDIC reset\r Set and cleared by software." bit_offset: 1 bit_size: 1 - name: FMACRST description: "FMAC reset\r Set and cleared by software." bit_offset: 2 bit_size: 1 - name: MDF1RST description: "MDF1 reset\r Set and cleared by software." bit_offset: 3 bit_size: 1 - name: CRCRST description: "CRC reset\r Set and cleared by software." bit_offset: 12 bit_size: 1 - name: TSCRST description: "TSC reset\r Set and cleared by software." bit_offset: 16 bit_size: 1 - name: RAMCFGRST description: "RAMCFG reset\r Set and cleared by software." bit_offset: 17 bit_size: 1 - name: DMA2DRST description: "DMA2D reset\r Set and cleared by software." bit_offset: 18 bit_size: 1 fieldset/AHB1SMENR: description: "RCC AHB1 peripheral clocks enable in Sleep and Stop modes register\t" fields: - name: GPDMA1SMEN description: "GPDMA1 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." bit_offset: 0 bit_size: 1 - name: CORDICSMEN description: "CORDIC clocks enable during Sleep and Stop modes\r Set and cleared by software during Sleep mode." bit_offset: 1 bit_size: 1 - name: FMACSMEN description: "FMAC clocks enable during Sleep and Stop modes.\r Set and cleared by software." bit_offset: 2 bit_size: 1 - name: MDF1SMEN description: "MDF1 clocks enable during Sleep and Stop modes.\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." bit_offset: 3 bit_size: 1 - name: FLASHSMEN description: "FLASH clocks enable during Sleep and Stop modes\r Set and cleared by software." bit_offset: 8 bit_size: 1 - name: CRCSMEN description: "CRC clocks enable during Sleep and Stop modes\r Set and cleared by software." bit_offset: 12 bit_size: 1 - name: TSCSMEN description: "TSC clocks enable during Sleep and Stop modes\r Set and cleared by software." bit_offset: 16 bit_size: 1 - name: RAMCFGSMEN description: "RAMCFG clocks enable during Sleep and Stop modes\r Set and cleared by software." bit_offset: 17 bit_size: 1 - name: DMA2DSMEN description: "DMA2D clocks enable during Sleep and Stop modes\r Set and cleared by software." bit_offset: 18 bit_size: 1 - name: GTZC1SMEN description: "GTZC1 clocks enable during Sleep and Stop modes\r Set and cleared by software." bit_offset: 24 bit_size: 1 - name: BKPSRAMSMEN description: "BKPSRAM clocks enable during Sleep and Stop modes\r Set and cleared by software" bit_offset: 28 bit_size: 1 - name: ICACHESMEN description: "ICACHE clocks enable during Sleep and Stop modes\r Set and cleared by software." bit_offset: 29 bit_size: 1 - name: DCACHE1SMEN description: "DCACHE1 clocks enable during Sleep and Stop modes\r Set and cleared by software." bit_offset: 30 bit_size: 1 - name: SRAM1SMEN description: "SRAM1 clocks enable during Sleep and Stop modes\r Set and cleared by software." bit_offset: 31 bit_size: 1 fieldset/AHB2ENR1: description: "RCC AHB2 peripheral clock enable register 1 " fields: - name: GPIOAEN description: "IO port A clock enable\r Set and cleared by software." bit_offset: 0 bit_size: 1 - name: GPIOBEN description: "IO port B clock enable\r Set and cleared by software." bit_offset: 1 bit_size: 1 - name: GPIOCEN description: "IO port C clock enable\r Set and cleared by software." bit_offset: 2 bit_size: 1 - name: GPIODEN description: "IO port D clock enable\r Set and cleared by software." bit_offset: 3 bit_size: 1 - name: GPIOEEN description: "IO port E clock enable\r Set and cleared by software." bit_offset: 4 bit_size: 1 - name: GPIOFEN description: "IO port F clock enable\r Set and cleared by software." bit_offset: 5 bit_size: 1 - name: GPIOGEN description: "IO port G clock enable\r Set and cleared by software." bit_offset: 6 bit_size: 1 - name: GPIOHEN description: "IO port H clock enable\r Set and cleared by software." bit_offset: 7 bit_size: 1 - name: GPIOIEN description: "IO port I clock enable\r Set and cleared by software." bit_offset: 8 bit_size: 1 - name: ADC1EN description: "ADC1 clock enable\r Set and cleared by software." bit_offset: 10 bit_size: 1 - name: DCMI_PSSIEN description: "DCMI and PSSI clock enable\r Set and cleared by software." bit_offset: 12 bit_size: 1 - name: OTGEN description: "OTG_FS clock enable\r Set and cleared by software." bit_offset: 14 bit_size: 1 - name: AESEN description: "AES clock enable\r Set and cleared by software." bit_offset: 16 bit_size: 1 - name: HASHEN description: "HASH clock enable\r Set and cleared by software" bit_offset: 17 bit_size: 1 - name: RNGEN description: "RNG clock enable\r Set and cleared by software." bit_offset: 18 bit_size: 1 - name: PKAEN description: "PKA clock enable\r Set and cleared by software." bit_offset: 19 bit_size: 1 - name: SAESEN description: "SAES clock enable\r Set and cleared by software." bit_offset: 20 bit_size: 1 - name: OCTOSPIMEN description: "OCTOSPIM clock enable\r Set and cleared by software." bit_offset: 21 bit_size: 1 - name: OTFDEC1EN description: "OTFDEC1 clock enable\r Set and cleared by software." bit_offset: 23 bit_size: 1 - name: OTFDEC2EN description: "OTFDEC2 clock enable\r Set and cleared by software." bit_offset: 24 bit_size: 1 - name: SDMMC1EN description: "SDMMC1 clock enable\r Set and cleared by software." bit_offset: 27 bit_size: 1 - name: SDMMC2EN description: "SDMMC2 clock enable\r Set and cleared by software." bit_offset: 28 bit_size: 1 - name: SRAM2EN description: "SRAM2 clock enable\r Set and reset by software." bit_offset: 30 bit_size: 1 - name: SRAM3EN description: "SRAM3 clock enable\r Set and reset by software." bit_offset: 31 bit_size: 1 fieldset/AHB2ENR2: description: "RCC AHB2 peripheral clock enable register 2 " fields: - name: FSMCEN description: "FSMC clock enable\r Set and cleared by software." bit_offset: 0 bit_size: 1 - name: OCTOSPI1EN description: "OCTOSPI1 clock enable\r Set and cleared by software." bit_offset: 4 bit_size: 1 - name: OCTOSPI2EN description: "OCTOSPI2 clock enable\r Set and cleared by software." bit_offset: 8 bit_size: 1 fieldset/AHB2RSTR1: description: "RCC AHB2 peripheral reset register 1 " fields: - name: GPIOARST description: "IO port A reset\r Set and cleared by software." bit_offset: 0 bit_size: 1 - name: GPIOBRST description: "IO port B reset\r Set and cleared by software." bit_offset: 1 bit_size: 1 - name: GPIOCRST description: "IO port C reset\r Set and cleared by software." bit_offset: 2 bit_size: 1 - name: GPIODRST description: "IO port D reset\r Set and cleared by software." bit_offset: 3 bit_size: 1 - name: GPIOERST description: "IO port E reset\r Set and cleared by software." bit_offset: 4 bit_size: 1 - name: GPIOFRST description: "IO port F reset\r Set and cleared by software." bit_offset: 5 bit_size: 1 - name: GPIOGRST description: "IO port G reset\r Set and cleared by software." bit_offset: 6 bit_size: 1 - name: GPIOHRST description: "IO port H reset\r Set and cleared by software." bit_offset: 7 bit_size: 1 - name: GPIOIRST description: "IO port I reset\r Set and cleared by software." bit_offset: 8 bit_size: 1 - name: ADC1RST description: "ADC1 reset\r Set and cleared by software." bit_offset: 10 bit_size: 1 - name: DCMI_PSSIRST description: "DCMI and PSSI reset\r Set and cleared by software." bit_offset: 12 bit_size: 1 - name: OTGRST description: "OTG_FS reset\r Set and cleared by software." bit_offset: 14 bit_size: 1 - name: AESRST description: "AES hardware accelerator reset\r Set and cleared by software." bit_offset: 16 bit_size: 1 - name: HASHRST description: "Hash reset\r Set and cleared by software." bit_offset: 17 bit_size: 1 - name: RNGRST description: "Random number generator reset\r Set and cleared by software." bit_offset: 18 bit_size: 1 - name: PKARST description: "PKA reset\r Set and cleared by software." bit_offset: 19 bit_size: 1 - name: SAESRST description: "SAES hardware accelerator reset\r Set and cleared by software." bit_offset: 20 bit_size: 1 - name: OCTOSPIMRST description: "OCTOSPIM reset\r Set and cleared by software." bit_offset: 21 bit_size: 1 - name: OTFDEC1RST description: "OTFDEC1 reset\r Set and cleared by software." bit_offset: 23 bit_size: 1 - name: OTFDEC2RST description: "OTFDEC2 reset\r Set and cleared by software." bit_offset: 24 bit_size: 1 - name: SDMMC1RST description: "SDMMC1 reset\r Set and cleared by software." bit_offset: 27 bit_size: 1 - name: SDMMC2RST description: "SDMMC2 reset\r Set and cleared by software." bit_offset: 28 bit_size: 1 fieldset/AHB2RSTR2: description: "RCC AHB2 peripheral reset register 2 " fields: - name: FSMCRST description: "Flexible memory controller reset\r Set and cleared by software." bit_offset: 0 bit_size: 1 - name: OCTOSPI1RST description: "OCTOSPI1 reset\r Set and cleared by software." bit_offset: 4 bit_size: 1 - name: OCTOSPI2RST description: "OCTOSPI2 reset\r Set and cleared by software." bit_offset: 8 bit_size: 1 fieldset/AHB2SMENR1: description: "RCC AHB2 peripheral clocks enable in Sleep and\tStop modes register 1 " fields: - name: GPIOASMEN description: "IO port A clocks enable during Sleep and Stop modes\r Set and cleared by software." bit_offset: 0 bit_size: 1 - name: GPIOBSMEN description: "IO port B clocks enable during Sleep and Stop modes\r Set and cleared by software." bit_offset: 1 bit_size: 1 - name: GPIOCSMEN description: "IO port C clocks enable during Sleep and Stop modes\r Set and cleared by software." bit_offset: 2 bit_size: 1 - name: GPIODSMEN description: "IO port D clocks enable during Sleep and Stop modes\r Set and cleared by software." bit_offset: 3 bit_size: 1 - name: GPIOESMEN description: "IO port E clocks enable during Sleep and Stop modes\r Set and cleared by software." bit_offset: 4 bit_size: 1 - name: GPIOFSMEN description: "IO port F clocks enable during Sleep and Stop modes\r Set and cleared by software." bit_offset: 5 bit_size: 1 - name: GPIOGSMEN description: "IO port G clocks enable during Sleep and Stop modes\r Set and cleared by software." bit_offset: 6 bit_size: 1 - name: GPIOHSMEN description: "IO port H clocks enable during Sleep and Stop modes\r Set and cleared by software." bit_offset: 7 bit_size: 1 - name: GPIOISMEN description: "IO port I clocks enable during Sleep and Stop modes\r Set and cleared by software." bit_offset: 8 bit_size: 1 - name: ADC1SMEN description: "ADC1 clocks enable during Sleep and Stop modes\r Set and cleared by software." bit_offset: 10 bit_size: 1 - name: DCMI_PSSISMEN description: "DCMI and PSSI clocks enable during Sleep and Stop modes\r Set and cleared by software." bit_offset: 12 bit_size: 1 - name: OTGSMEN description: "OTG_FS clocks enable during Sleep and Stop modes\r Set and cleared by software." bit_offset: 14 bit_size: 1 - name: AESSMEN description: "AES clock enable during Sleep and Stop modes\r Set and cleared by software" bit_offset: 16 bit_size: 1 - name: HASHSMEN description: "HASH clock enable during Sleep and Stop modes\r Set and cleared by software" bit_offset: 17 bit_size: 1 - name: RNGSMEN description: "Random number generator (RNG) clocks enable during Sleep and Stop modes\r Set and cleared by software." bit_offset: 18 bit_size: 1 - name: PKASMEN description: "PKA clocks enable during Sleep and Stop modes\r Set and cleared by software." bit_offset: 19 bit_size: 1 - name: SAESSMEN description: "SAES accelerator clocks enable during Sleep and Stop modes\r Set and cleared by software." bit_offset: 20 bit_size: 1 - name: OCTOSPIMSMEN description: "OCTOSPIM clocks enable during Sleep and Stop modes\r Set and cleared by software." bit_offset: 21 bit_size: 1 - name: OTFDEC1SMEN description: "OTFDEC1 clocks enable during Sleep and Stop modes\r Set and cleared by software." bit_offset: 23 bit_size: 1 - name: OTFDEC2SMEN description: "OTFDEC2 clocks enable during Sleep and Stop modes\r Set and cleared by software." bit_offset: 24 bit_size: 1 - name: SDMMC1SMEN description: "SDMMC1 clocks enable during Sleep and Stop modes\r Set and cleared by software." bit_offset: 27 bit_size: 1 - name: SDMMC2SMEN description: "SDMMC2 clocks enable during Sleep and Stop modes\r Set and cleared by software." bit_offset: 28 bit_size: 1 - name: SRAM2SMEN description: "SRAM2 clocks enable during Sleep and Stop modes\r Set and cleared by software." bit_offset: 30 bit_size: 1 - name: SRAM3SMEN description: "SRAM3 clocks enable during Sleep and Stop modes\r Set and cleared by software." bit_offset: 31 bit_size: 1 fieldset/AHB2SMENR2: description: "RCC AHB2 peripheral clocks enable in Sleep and\tStop modes register 2 " fields: - name: FSMCSMEN description: "FSMC clocks enable during Sleep and Stop modes\r Set and cleared by software." bit_offset: 0 bit_size: 1 - name: OCTOSPI1SMEN description: "OCTOSPI1 clocks enable during Sleep and Stop modes\r Set and cleared by software." bit_offset: 4 bit_size: 1 - name: OCTOSPI2SMEN description: "OCTOSPI2 clocks enable during Sleep and Stop modes\r Set and cleared by software." bit_offset: 8 bit_size: 1 fieldset/AHB3ENR: description: "RCC AHB3 peripheral clock enable register " fields: - name: LPGPIO1EN description: "LPGPIO1 enable\r Set and cleared by software." bit_offset: 0 bit_size: 1 - name: PWREN description: "PWR clock enable\r Set and cleared by software." bit_offset: 2 bit_size: 1 - name: ADC4EN description: "ADC4 clock enable\r Set and cleared by software." bit_offset: 5 bit_size: 1 - name: DAC1EN description: "DAC1 clock enable\r Set and cleared by software." bit_offset: 6 bit_size: 1 - name: LPDMA1EN description: "LPDMA1 clock enable\r Set and cleared by software." bit_offset: 9 bit_size: 1 - name: ADF1EN description: "ADF1 clock enable\r Set and cleared by software." bit_offset: 10 bit_size: 1 - name: GTZC2EN description: "GTZC2 clock enable\r Set and cleared by software." bit_offset: 12 bit_size: 1 - name: SRAM4EN description: "SRAM4 clock enable\r Set and reset by software." bit_offset: 31 bit_size: 1 fieldset/AHB3RSTR: description: "RCC AHB3 peripheral reset register " fields: - name: LPGPIO1RST description: "LPGPIO1 reset\r Set and cleared by software." bit_offset: 0 bit_size: 1 - name: ADC4RST description: "ADC4 reset\r Set and cleared by software." bit_offset: 5 bit_size: 1 - name: DAC1RST description: "DAC1 reset\r Set and cleared by software." bit_offset: 6 bit_size: 1 - name: LPDMA1RST description: "LPDMA1 reset\r Set and cleared by software." bit_offset: 9 bit_size: 1 - name: ADF1RST description: "ADF1 reset\r Set and cleared by software." bit_offset: 10 bit_size: 1 fieldset/AHB3SMENR: description: "RCC AHB3 peripheral clocks enable in Sleep and Stop modes register\t" fields: - name: LPGPIO1SMEN description: "LPGPIO1 enable during Sleep and Stop modes\r Set and cleared by software." bit_offset: 0 bit_size: 1 - name: PWRSMEN description: "PWR clock enable during Sleep and Stop modes\r Set and cleared by software." bit_offset: 2 bit_size: 1 - name: ADC4SMEN description: "ADC4 clock enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." bit_offset: 5 bit_size: 1 - name: DAC1SMEN description: "DAC1 clock enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." bit_offset: 6 bit_size: 1 - name: LPDMA1SMEN description: "LPDMA1 clock enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." bit_offset: 9 bit_size: 1 - name: ADF1SMEN description: "ADF1 clock enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." bit_offset: 10 bit_size: 1 - name: GTZC2SMEN description: "GTZC2 clock enable during Sleep and Stop modes\r Set and cleared by software." bit_offset: 12 bit_size: 1 - name: SRAM4SMEN description: "SRAM4 clocks enable during Sleep and Stop modes\r Set and cleared by software." bit_offset: 31 bit_size: 1 fieldset/APB1ENR1: description: "RCC APB1 peripheral clock enable register 1 " fields: - name: TIM2EN description: "TIM2 clock enable\r Set and cleared by software." bit_offset: 0 bit_size: 1 - name: TIM3EN description: "TIM3 clock enable\r Set and cleared by software." bit_offset: 1 bit_size: 1 - name: TIM4EN description: "TIM4 clock enable\r Set and cleared by software." bit_offset: 2 bit_size: 1 - name: TIM5EN description: "TIM5 clock enable\r Set and cleared by software." bit_offset: 3 bit_size: 1 - name: TIM6EN description: "TIM6 clock enable\r Set and cleared by software." bit_offset: 4 bit_size: 1 - name: TIM7EN description: "TIM7 clock enable\r Set and cleared by software." bit_offset: 5 bit_size: 1 - name: WWDGEN description: "WWDG clock enable\r Set by software to enable the window watchdog clock. Reset by hardware system reset.\r This bit can also be set by hardware if the WWDG_SW option bit is reset." bit_offset: 11 bit_size: 1 - name: SPI2EN description: "SPI2 clock enable\r Set and cleared by software." bit_offset: 14 bit_size: 1 - name: USART2EN description: "USART2 clock enable\r Set and cleared by software." bit_offset: 17 bit_size: 1 - name: USART3EN description: "USART3 clock enable\r Set and cleared by software." bit_offset: 18 bit_size: 1 - name: UART4EN description: "UART4 clock enable\r Set and cleared by software." bit_offset: 19 bit_size: 1 - name: UART5EN description: "UART5 clock enable\r Set and cleared by software." bit_offset: 20 bit_size: 1 - name: I2C1EN description: "I2C1 clock enable\r Set and cleared by software." bit_offset: 21 bit_size: 1 - name: I2C2EN description: "I2C2 clock enable\r Set and cleared by software." bit_offset: 22 bit_size: 1 - name: CRSEN description: "CRS clock enable\r Set and cleared by software." bit_offset: 24 bit_size: 1 fieldset/APB1ENR2: description: "RCC APB1 peripheral clock enable register 2 " fields: - name: I2C4EN description: "I2C4 clock enable\r Set and cleared by software" bit_offset: 1 bit_size: 1 - name: LPTIM2EN description: "LPTIM2 clock enable\r Set and cleared by software." bit_offset: 5 bit_size: 1 - name: FDCAN1EN description: "FDCAN1 clock enable\r Set and cleared by software." bit_offset: 9 bit_size: 1 - name: UCPD1EN description: "UCPD1 clock enable\r Set and cleared by software." bit_offset: 23 bit_size: 1 fieldset/APB1RSTR1: description: "RCC APB1 peripheral reset register 1 " fields: - name: TIM2RST description: "TIM2 reset\r Set and cleared by software." bit_offset: 0 bit_size: 1 - name: TIM3RST description: "TIM3 reset\r Set and cleared by software." bit_offset: 1 bit_size: 1 - name: TIM4RST description: "TIM4 reset\r Set and cleared by software." bit_offset: 2 bit_size: 1 - name: TIM5RST description: "TIM5 reset\r Set and cleared by software." bit_offset: 3 bit_size: 1 - name: TIM6RST description: "TIM6 reset\r Set and cleared by software." bit_offset: 4 bit_size: 1 - name: TIM7RST description: "TIM7 reset\r Set and cleared by software." bit_offset: 5 bit_size: 1 - name: SPI2RST description: "SPI2 reset\r Set and cleared by software." bit_offset: 14 bit_size: 1 - name: USART2RST description: "USART2 reset\r Set and cleared by software." bit_offset: 17 bit_size: 1 - name: USART3RST description: "USART3 reset\r Set and cleared by software." bit_offset: 18 bit_size: 1 - name: UART4RST description: "UART4 reset\r Set and cleared by software." bit_offset: 19 bit_size: 1 - name: UART5RST description: "UART5 reset\r Set and cleared by software." bit_offset: 20 bit_size: 1 - name: I2C1RST description: "I2C1 reset\r Set and cleared by software." bit_offset: 21 bit_size: 1 - name: I2C2RST description: "I2C2 reset\r Set and cleared by software." bit_offset: 22 bit_size: 1 - name: CRSRST description: "CRS reset\r Set and cleared by software." bit_offset: 24 bit_size: 1 fieldset/APB1RSTR2: description: "RCC APB1 peripheral reset register 2 " fields: - name: I2C4RST description: "I2C4 reset\r Set and cleared by software" bit_offset: 1 bit_size: 1 - name: LPTIM2RST description: "LPTIM2 reset\r Set and cleared by software." bit_offset: 5 bit_size: 1 - name: FDCAN1RST description: "FDCAN1 reset\r Set and cleared by software." bit_offset: 9 bit_size: 1 - name: UCPD1RST description: "UCPD1 reset\r Set and cleared by software." bit_offset: 23 bit_size: 1 fieldset/APB1SMENR1: description: "RCC APB1 peripheral clocks enable in Sleep and Stop modes\tregister 1 " fields: - name: TIM2SMEN description: "TIM2 clocks enable during Sleep and Stop modes\r Set and cleared by software." bit_offset: 0 bit_size: 1 - name: TIM3SMEN description: "TIM3 clocks enable during Sleep and Stop modes\r Set and cleared by software." bit_offset: 1 bit_size: 1 - name: TIM4SMEN description: "TIM4 clocks enable during Sleep and Stop modes\r Set and cleared by software." bit_offset: 2 bit_size: 1 - name: TIM5SMEN description: "TIM5 clocks enable during Sleep and Stop modes\r Set and cleared by software." bit_offset: 3 bit_size: 1 - name: TIM6SMEN description: "TIM6 clocks enable during Sleep and Stop modes\r Set and cleared by software." bit_offset: 4 bit_size: 1 - name: TIM7SMEN description: "TIM7 clocks enable during Sleep and Stop modes\r Set and cleared by software." bit_offset: 5 bit_size: 1 - name: WWDGSMEN description: "Window watchdog clocks enable during Sleep and Stop modes\r Set and cleared by software. This bit is forced to 1 by hardware when the hardware WWDG option is activated." bit_offset: 11 bit_size: 1 - name: SPI2SMEN description: "SPI2 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." bit_offset: 14 bit_size: 1 - name: USART2SMEN description: "USART2 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." bit_offset: 17 bit_size: 1 - name: USART3SMEN description: "USART3 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." bit_offset: 18 bit_size: 1 - name: UART4SMEN description: "UART4 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." bit_offset: 19 bit_size: 1 - name: UART5SMEN description: "UART5 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." bit_offset: 20 bit_size: 1 - name: I2C1SMEN description: "I2C1 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." bit_offset: 21 bit_size: 1 - name: I2C2SMEN description: "I2C2 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." bit_offset: 22 bit_size: 1 - name: CRSSMEN description: "CRS clock enable during Sleep and Stop modes\r Set and cleared by software." bit_offset: 24 bit_size: 1 fieldset/APB1SMENR2: description: "RCC APB1 peripheral clocks enable in Sleep and\tStop modes register 2 " fields: - name: I2C4SMEN description: "I2C4 clocks enable during Sleep and Stop modes\r Set and cleared by software\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." bit_offset: 1 bit_size: 1 - name: LPTIM2SMEN description: "LPTIM2 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." bit_offset: 5 bit_size: 1 - name: FDCAN1SMEN description: "FDCAN1 clocks enable during Sleep and Stop modes\r Set and cleared by software." bit_offset: 9 bit_size: 1 - name: UCPD1SMEN description: "UCPD1 clocks enable during Sleep and Stop modes\r Set and cleared by software." bit_offset: 23 bit_size: 1 fieldset/APB2ENR: description: "RCC APB2 peripheral clock enable register " fields: - name: TIM1EN description: "TIM1 clock enable\r Set and cleared by software." bit_offset: 11 bit_size: 1 - name: SPI1EN description: "SPI1 clock enable\r Set and cleared by software." bit_offset: 12 bit_size: 1 - name: TIM8EN description: "TIM8 clock enable\r Set and cleared by software." bit_offset: 13 bit_size: 1 - name: USART1EN description: "USART1clock enable\r Set and cleared by software." bit_offset: 14 bit_size: 1 - name: TIM15EN description: "TIM15 clock enable\r Set and cleared by software." bit_offset: 16 bit_size: 1 - name: TIM16EN description: "TIM16 clock enable\r Set and cleared by software." bit_offset: 17 bit_size: 1 - name: TIM17EN description: "TIM17 clock enable\r Set and cleared by software." bit_offset: 18 bit_size: 1 - name: SAI1EN description: "SAI1 clock enable\r Set and cleared by software." bit_offset: 21 bit_size: 1 - name: SAI2EN description: "SAI2 clock enable\r Set and cleared by software." bit_offset: 22 bit_size: 1 fieldset/APB2RSTR: description: "RCC APB2 peripheral reset register " fields: - name: TIM1RST description: "TIM1 reset\r Set and cleared by software." bit_offset: 11 bit_size: 1 - name: SPI1RST description: "SPI1 reset\r Set and cleared by software." bit_offset: 12 bit_size: 1 - name: TIM8RST description: "TIM8 reset\r Set and cleared by software." bit_offset: 13 bit_size: 1 - name: USART1RST description: "USART1 reset\r Set and cleared by software." bit_offset: 14 bit_size: 1 - name: TIM15RST description: "TIM15 reset\r Set and cleared by software." bit_offset: 16 bit_size: 1 - name: TIM16RST description: "TIM16 reset\r Set and cleared by software." bit_offset: 17 bit_size: 1 - name: TIM17RST description: "TIM17 reset\r Set and cleared by software." bit_offset: 18 bit_size: 1 - name: SAI1RST description: "SAI1 reset\r Set and cleared by software." bit_offset: 21 bit_size: 1 - name: SAI2RST description: "SAI2 reset\r Set and cleared by software." bit_offset: 22 bit_size: 1 fieldset/APB2SMENR: description: "RCC APB2 peripheral clocks enable in Sleep and Stop modes register\t" fields: - name: TIM1SMEN description: "TIM1 clocks enable during Sleep and Stop modes\r Set and cleared by software." bit_offset: 11 bit_size: 1 - name: SPI1SMEN description: "SPI1 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." bit_offset: 12 bit_size: 1 - name: TIM8SMEN description: "TIM8 clocks enable during Sleep and Stop modes\r Set and cleared by software." bit_offset: 13 bit_size: 1 - name: USART1SMEN description: "USART1clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." bit_offset: 14 bit_size: 1 - name: TIM15SMEN description: "TIM15 clocks enable during Sleep and Stop modes\r Set and cleared by software." bit_offset: 16 bit_size: 1 - name: TIM16SMEN description: "TIM16 clocks enable during Sleep and Stop modes\r Set and cleared by software." bit_offset: 17 bit_size: 1 - name: TIM17SMEN description: "TIM17 clocks enable during Sleep and Stop modes\r Set and cleared by software." bit_offset: 18 bit_size: 1 - name: SAI1SMEN description: "SAI1 clocks enable during Sleep and Stop modes\r Set and cleared by software." bit_offset: 21 bit_size: 1 - name: SAI2SMEN description: "SAI2 clocks enable during Sleep and Stop modes\r Set and cleared by software." bit_offset: 22 bit_size: 1 fieldset/APB3ENR: description: "RCC APB3 peripheral clock enable register " fields: - name: SYSCFGEN description: "SYSCFG clock enable\r Set and cleared by software." bit_offset: 1 bit_size: 1 - name: SPI3EN description: "SPI3 clock enable\r Set and cleared by software." bit_offset: 5 bit_size: 1 - name: LPUART1EN description: "LPUART1 clock enable\r Set and cleared by software." bit_offset: 6 bit_size: 1 - name: I2C3EN description: "I2C3 clock enable\r Set and cleared by software." bit_offset: 7 bit_size: 1 - name: LPTIM1EN description: "LPTIM1 clock enable\r Set and cleared by software." bit_offset: 11 bit_size: 1 - name: LPTIM3EN description: "LPTIM3 clock enable\r Set and cleared by software." bit_offset: 12 bit_size: 1 - name: LPTIM4EN description: "LPTIM4 clock enable\r Set and cleared by software." bit_offset: 13 bit_size: 1 - name: OPAMPEN description: "OPAMP clock enable\r Set and cleared by software." bit_offset: 14 bit_size: 1 - name: COMPEN description: "COMP clock enable\r Set and cleared by software." bit_offset: 15 bit_size: 1 - name: VREFEN description: "VREFBUF clock enable\r Set and cleared by software." bit_offset: 20 bit_size: 1 - name: RTCAPBEN description: "RTC and TAMP APB clock enable\r Set and cleared by software." bit_offset: 21 bit_size: 1 fieldset/APB3RSTR: description: "RCC APB3 peripheral reset register " fields: - name: SYSCFGRST description: "SYSCFG reset\r Set and cleared by software." bit_offset: 1 bit_size: 1 - name: SPI3RST description: "SPI3 reset\r Set and cleared by software." bit_offset: 5 bit_size: 1 - name: LPUART1RST description: "LPUART1 reset\r Set and cleared by software." bit_offset: 6 bit_size: 1 - name: I2C3RST description: "I2C3 reset\r Set and cleared by software." bit_offset: 7 bit_size: 1 - name: LPTIM1RST description: "LPTIM1 reset\r Set and cleared by software." bit_offset: 11 bit_size: 1 - name: LPTIM3RST description: "LPTIM3 reset\r Set and cleared by software." bit_offset: 12 bit_size: 1 - name: LPTIM4RST description: "LPTIM4 reset\r Set and cleared by software." bit_offset: 13 bit_size: 1 - name: OPAMPRST description: "OPAMP reset\r Set and cleared by software." bit_offset: 14 bit_size: 1 - name: COMPRST description: "COMP reset\r Set and cleared by software." bit_offset: 15 bit_size: 1 - name: VREFRST description: "VREFBUF reset\r Set and cleared by software." bit_offset: 20 bit_size: 1 fieldset/APB3SMENR: description: "RCC APB3 peripheral clock enable in Sleep and Stop modes register\t" fields: - name: SYSCFGSMEN description: "SYSCFG clocks enable during Sleep and Stop modes\r Set and cleared by software." bit_offset: 1 bit_size: 1 - name: SPI3SMEN description: "SPI3 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." bit_offset: 5 bit_size: 1 - name: LPUART1SMEN description: "LPUART1 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." bit_offset: 6 bit_size: 1 - name: I2C3SMEN description: "I2C3 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." bit_offset: 7 bit_size: 1 - name: LPTIM1SMEN description: "LPTIM1 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." bit_offset: 11 bit_size: 1 - name: LPTIM3SMEN description: "LPTIM3 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." bit_offset: 12 bit_size: 1 - name: LPTIM4SMEN description: "LPTIM4 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." bit_offset: 13 bit_size: 1 - name: OPAMPSMEN description: "OPAMP clocks enable during Sleep and Stop modes\r Set and cleared by software." bit_offset: 14 bit_size: 1 - name: COMPSMEN description: "COMP clocks enable during Sleep and Stop modes\r Set and cleared by software." bit_offset: 15 bit_size: 1 - name: VREFSMEN description: "VREFBUF clocks enable during Sleep and Stop modes\r Set and cleared by software." bit_offset: 20 bit_size: 1 - name: RTCAPBSMEN description: "RTC and TAMP APB clock enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." bit_offset: 21 bit_size: 1 fieldset/BDCR: description: "RCC Backup domain control register " fields: - name: LSEON description: "LSE oscillator enable\r Set and cleared by software." bit_offset: 0 bit_size: 1 - name: LSERDY description: "LSE oscillator ready\r Set and cleared by hardware to indicate when the external 32 kHz oscillator is stable. After the LSEON bit is cleared, LSERDY goes low after six external low-speed oscillator clock cycles." bit_offset: 1 bit_size: 1 enum: LSERDY - name: LSEBYP description: "LSE oscillator bypass\r Set and cleared by software to bypass oscillator in debug mode. This bit can be written only when the external 32 kHz oscillator is disabled (LSEON = 0 and LSERDY = 0)." bit_offset: 2 bit_size: 1 enum: LSEBYP - name: LSEDRV description: "LSE oscillator drive capability\r Set by software to modulate the drive capability of the LSE oscillator. This field can be written only when the external 32 kHz oscillator is disabled (LSEON = 0 and LSERDY = 0).\r Note: The oscillator is in 'Xtal mode when it is not in bypass mode." bit_offset: 3 bit_size: 2 enum: LSEDRV - name: LSECSSON description: "CSS on LSE enable\r Set by software to enable the CSS on LSE. LSECSSON must be enabled after the LSE oscillator is enabled (LSEON bit enabled) and ready (LSERDY flag set by hardware), and after the RTCSEL bit is selected.\r Once enabled, this bit cannot be disabled, except after a LSE failure detection (LSECSSD = 1). In that case, the software must disable the LSECSSON bit." bit_offset: 5 bit_size: 1 - name: LSECSSD description: "CSS on LSE failure Detection\r Set by hardware to indicate when a failure is detected by the CCS on the external 32 kHz oscillator (LSE)." bit_offset: 6 bit_size: 1 enum: LSECSSD - name: LSESYSEN description: "LSE system clock (LSESYS) enable\r Set by software to enable always the LSE system clock generated by RCC. This clock can be used by any peripheral when its source clock is the LSE or at system level in case of one of the LSCOSEL, MCO, MSI PLL mode or CSS on LSE is needed.\r The LSESYS clock can be generated even if LSESYSEN= 0 if the LSE clock is requested by the CSS on LSE, by a peripheral or any other source clock using LSE." bit_offset: 7 bit_size: 1 - name: RTCSEL description: "RTC and TAMP clock source selection\r Set by software to select the clock source for the RTC and TAMP . Once the RTC and TAMP clock source has been selected, it cannot be changed anymore unless the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is set). The BDRST bit can be used to reset them." bit_offset: 8 bit_size: 2 enum: RTCSEL - name: LSESYSRDY description: "LSE system clock (LSESYS) ready\r Set and cleared by hardware to indicate when the LSE system clock is stable.When the LSESYSEN bit is set, the LSESYSRDY flag is set after two LSE clock cycles.\r The LSE clock must be already enabled and stable (LSEON and LSERDY are set).\r When the LSEON bit is cleared, LSERDY goes low after six external low-speed oscillator clock cycles." bit_offset: 11 bit_size: 1 enum: LSESYSRDY - name: LSEGFON description: "LSE clock glitch filter enable\r Set and cleared by hardware to enable the LSE glitch filter. This bit can be written only when the LSE is disabled (LSEON = 0 and LSERDY = 0)" bit_offset: 12 bit_size: 1 - name: RTCEN description: "RTC and TAMP clock enable\r Set and cleared by software." bit_offset: 15 bit_size: 1 - name: BDRST description: "Backup domain software reset\r Set and cleared by software." bit_offset: 16 bit_size: 1 - name: LSCOEN description: "Low-speed clock output (LSCO) enable\r Set and cleared by software." bit_offset: 24 bit_size: 1 - name: LSCOSEL description: "Low-speed clock output selection\r Set and cleared by software." bit_offset: 25 bit_size: 1 enum: LSCOSEL - name: LSION description: "LSI oscillator enable\r Set and cleared by software." bit_offset: 26 bit_size: 1 - name: LSIRDY description: "LSI oscillator ready\r Set and cleared by hardware to indicate when the LSI oscillator is stable. After the LSION bit is cleared, LSIRDY goes low after three internal low-speed oscillator clock cycles. This bit is set when the LSI is used by IWDG or RTC, even if LSION = 0." bit_offset: 27 bit_size: 1 enum: LSIRDY - name: LSIPREDIV description: "Low-speed clock divider configuration\r Set and cleared by software to enable the LSI division. This bit can be written only when the LSI is disabled (LSION = 0 and LSIRDY = 0). If the LSI was previously enabled, it is necessary to wait for at least 60 μs after clearing LSION bit (synchronization time for LSI to be really disabled), before writing LSIPREDIV. The LSIPREDIV cannot be changed if the LSI is used by the IWDG or by the RTC." bit_offset: 28 bit_size: 1 enum: LSIPREDIV fieldset/CCIPR1: description: "RCC peripherals independent clock configuration register 1\t" fields: - name: USART1SEL description: "USART1 kernel clock source selection\r This bits are used to select the USART1 kernel clock source.\r Note: The USART1 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI16 or LSE." bit_offset: 0 bit_size: 2 enum: USARTSEL - name: USART2SEL description: "USART2 kernel clock source selection\r This bits are used to select the USART2 kernel clock source.\r Note: The USART2 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI16 or LSE." bit_offset: 2 bit_size: 2 enum: USARTSEL - name: USART3SEL description: "USART3 kernel clock source selection\r This bits are used to select the USART3 kernel clock source.\r Note: The USART3 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI16 or LSE." bit_offset: 4 bit_size: 2 enum: USARTSEL - name: UART4SEL description: "UART4 kernel clock source selection\r This bits are used to select the UART4 kernel clock source.\r Note: The UART4 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI16 or LSE." bit_offset: 6 bit_size: 2 enum: UARTSEL - name: UART5SEL description: "UART5 kernel clock source selection\r These bits are used to select the UART5 kernel clock source.\r Note: The UART5 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI16 or LSE." bit_offset: 8 bit_size: 2 enum: UARTSEL - name: I2C1SEL description: "I2C1 kernel clock source selection\r These bits are used to select the I2C1 kernel clock source.\r Note: The I2C1 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI16 or MSIK." bit_offset: 10 bit_size: 2 enum: ICSEL - name: I2C2SEL description: "I2C2 kernel clock source selection\r These bits are used to select the I2C2 kernel clock source.\r Note: The I2C2 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI16 or MSIK." bit_offset: 12 bit_size: 2 enum: ICSEL - name: I2C4SEL description: "I2C4 kernel clock source selection\r These bits are used to select the I2C4 kernel clock source.\r Note: The I2C4 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI16 or MSIK." bit_offset: 14 bit_size: 2 enum: ICSEL - name: SPI2SEL description: "SPI2 kernel clock source selection\r These bits are used to select the SPI2 kernel clock source.\r Note: The SPI2 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI16 or MSIK." bit_offset: 16 bit_size: 2 enum: SPISEL - name: LPTIM2SEL description: "Low-power timer 2 kernel clock source selection\r These bits are used to select the LPTIM2 kernel clock source.\r Note: The LPTIM2 is functional in Stop 0 and Stop 1 mode only when the kernel clock is LSI, LSE or HSI16 if HSIKERON = 1." bit_offset: 18 bit_size: 2 enum: LPTIMSEL - name: SPI1SEL description: "SPI1 kernel clock source selection\r These bits are used to select the SPI1 kernel clock source.\r Note: The SPI1 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI16 or MSIK." bit_offset: 20 bit_size: 2 enum: SPISEL - name: SYSTICKSEL description: "SysTick clock source selection\r These bits are used to select the SysTick clock source.\r Note: When LSE or LSI is selected, the AHB frequency must be at least four times higher than the LSI or LSE frequency. In addition, a jitter up to one HCLK cycle is introduced, due to the LSE or LSI sampling with HCLK in the SysTick circuitry." bit_offset: 22 bit_size: 2 enum: SYSTICKSEL - name: FDCAN1SEL description: "FDCAN1 kernel clock source selection\r These bits are used to select the FDCAN1 kernel clock source." bit_offset: 24 bit_size: 2 enum: FDCANSEL - name: ICLKSEL description: "intermediate clock source selection\r These bits are used to select the clock source used by OTG_FS and SDMMC." bit_offset: 26 bit_size: 2 enum: ICLKSEL - name: TIMICSEL description: "Clocks sources for TIM16,TIM17 and LPTIM2 internal input capture\r When the TIMICSEL2 bit is set, the TIM16, TIM17 and LPTIM2 internal input capture can be connected either to HSI/256, MSI/4 or MSI/1024. Depending on TIMICSEL[1:0] value, MSI is either MSIK or MSIS.\r When TIMICSEL2 is cleared, the HSI, MSIK and MSIS clock sources cannot be selected as TIM16, TIM17 or LPTIM2 internal input capture.\r 0xx: HSI, MSIK and MSIS dividers disabled\r Note: The clock division must be disabled (TIMICSEL configured to 0xx) before selecting or changing a clock sources division." bit_offset: 29 bit_size: 3 enum: TIMICSEL fieldset/CCIPR2: description: "RCC peripherals independent clock configuration register 2\t" fields: - name: MDF1SEL description: "MDF1 kernel clock source selection\r These bits are used to select the MDF1 kernel clock source.\r others: reserved" bit_offset: 0 bit_size: 3 enum: MDFSEL - name: SAI1SEL description: "SAI1 kernel clock source selection\r These bits are used to select the SAI1 kernel clock source.\r others: reserved\r Note: If the selected clock is the external clock and this clock is stopped, a switch to another clock is impossible." bit_offset: 5 bit_size: 3 enum: SAISEL - name: SAI2SEL description: "SAI2 kernel clock source selection\r These bits are used to select the SAI2 kernel clock source.\r others: reserved\r Note: If the selected clock is the external clock and this clock is stopped, a switch to another clock is impossible." bit_offset: 8 bit_size: 3 enum: SAISEL - name: SAESSEL description: "SAES kernel clock source selection\r This bit is used to select the SAES kernel clock source." bit_offset: 11 bit_size: 1 enum: SAESSEL - name: RNGSEL description: "RNGSEL kernel clock source selection\r These bits are used to select the RNG kernel clock source." bit_offset: 12 bit_size: 2 enum: RNGSEL - name: SDMMCSEL description: "SDMMC1 and SDMMC2 kernel clock source selection\r This bit is used to select the SDMMC kernel clock source. It is recommended to change this bit only after reset and before enabling the SDMMC." bit_offset: 14 bit_size: 1 enum: SDMMCSEL - name: OCTOSPISEL description: "OCTOSPI1 and OCTOSPI2 kernel clock source selection\r These bits are used to select the OCTOSPI1 and OCTOSPI2 kernel clock source." bit_offset: 20 bit_size: 2 enum: OCTOSPISEL fieldset/CCIPR3: description: "RCC peripherals independent clock configuration register 3\t" fields: - name: LPUART1SEL description: "LPUART1 kernel clock source selection\r These bits are used to select the LPUART1 kernel clock source.\r others: reserved\r Note: The LPUART1 is functional in Stop 0, Stop 1 and Stop 2 modes only when the kernel clock is HSI16, LSE or MSIK." bit_offset: 0 bit_size: 3 enum: LPUARTSEL - name: SPI3SEL description: "SPI3 kernel clock source selection\r These bits are used to select the SPI3 kernel clock source.\r Note: The SPI3 is functional in Stop 0, Stop 1 and Stop 2 modes only when the kernel clock is HSI16 or MSIK." bit_offset: 3 bit_size: 2 enum: SPISEL - name: I2C3SEL description: "I2C3 kernel clock source selection\r These bits are used to select the I2C3 kernel clock source.\r Note: The I2C3 is functional in Stop 0, Stop 1 and Stop 2 modes only when the kernel clock is HSI16 or MSIK." bit_offset: 6 bit_size: 2 enum: ICSEL - name: LPTIM34SEL description: "LPTIM3 and LPTIM4 kernel clock source selection\r These bits are used to select the LPTIM3 and LPTIM4 kernel clock source.\r Note: The LPTIM3 and LPTIM4 are functional in Stop 0, Stop 1 and Stop 2 modes only when the kernel clock is LSI, LSE, HSI16 with HSIKERON = 1 or MSIK with MSIKERON = 1." bit_offset: 8 bit_size: 2 enum: LPTIMSEL - name: LPTIM1SEL description: "LPTIM1 kernel clock source selection\r These bits are used to select the LPTIM1 kernel clock source.\r Note: The LPTIM1 is functional in Stop 0, Stop 1 and Stop 2 modes only when the kernel clock is LSI, LSE, HSI16 with HSIKERON = 1 or MSIK with MSIKERON = 1." bit_offset: 10 bit_size: 2 enum: LPTIMSEL - name: ADCDACSEL description: "ADC1, ADC4 and DAC1 kernel clock source selection\r These bits are used to select the ADC1, ADC4 and DAC1 kernel clock source.\r others: reserved\r Note: The ADC1, ADC4 and DAC1 are functional in Stop 0, Stop 1 and Stop 2 modes only when the kernel clock is HSI16 or MSIK (only ADC4 and DAC1 are functional in Stop 2 mode)." bit_offset: 12 bit_size: 3 enum: ADCDACSEL - name: DAC1SEL description: "DAC1 sample and hold clock source selection\r This bit is used to select the DAC1 sample and hold clock source." bit_offset: 15 bit_size: 1 enum: DACSEL - name: ADF1SEL description: "ADF1 kernel clock source selection\r These bits are used to select the ADF1 kernel clock source.\r others: reserved\r Note: The ADF1 is functional in Stop 0, Stop 1 and Stop 2 modes only when the kernel clock is AUDIOCLK or MSIK." bit_offset: 16 bit_size: 3 enum: ADFSEL fieldset/CFGR1: description: "RCC clock configuration register 1 " fields: - name: SW description: "system clock switch\r Set and cleared by software to select system clock source (SYSCLK).\r Configured by hardware to force MSIS oscillator selection when exiting Standby or Shutdown mode. Configured by hardware to force MSIS or HSI16 oscillator selection when exiting Stop mode or in case of HSE oscillator failure, depending on STOPWUCK value." bit_offset: 0 bit_size: 2 enum: SW - name: SWS description: "system clock switch status\r Set and cleared by hardware to indicate which clock source is used as system clock." bit_offset: 2 bit_size: 2 enum: SWS - name: STOPWUCK description: "wakeup from Stop and CSS backup clock selection\r Set and cleared by software to select the system clock used when exiting Stop mode.\r The selected clock is also used as emergency clock for the clock security system on HSE. Warning: STOPWUCK must not be modified when the CSS is enabled by HSECSSON bit in RCC_CR and the system clock is HSE (SWS = 10) or a switch on HSE is requested (SW = 10)." bit_offset: 4 bit_size: 1 enum: STOPWUCK - name: STOPKERWUCK description: "wakeup from Stop kernel clock automatic enable selection\r Set and cleared by software to enable automatically another oscillator when exiting Stop mode. This oscillator can be used as independent kernel clock by peripherals." bit_offset: 5 bit_size: 1 enum: STOPKERWUCK - name: MCOSEL description: "microcontroller clock output\r Set and cleared by software.\r Others: reserved\r Note: This clock output may have some truncated cycles at startup or during MCO clock source switching." bit_offset: 24 bit_size: 4 enum: MCOSEL - name: MCOPRE description: "microcontroller clock output prescaler\r Set and cleared by software.\r It is highly recommended to change this prescaler before MCO output is enabled.\r Others: not allowed" bit_offset: 28 bit_size: 3 enum: MCOPRE fieldset/CFGR2: description: "RCC clock configuration register 2 " fields: - name: HPRE description: "AHB prescaler\r Set and cleared by software to control the division factor of the AHB clock (HCLK).\r Depending on the device voltage range, the software must set these bits correctly to ensure that the system frequency does not exceed the maximum allowed frequency (for more details, refer to ). After a write operation to these bits and before decreasing the voltage range, this register must be read to be sure that the new value is taken into account.\r 0xxx: SYSCLK not divided" bit_offset: 0 bit_size: 4 enum: HPRE - name: PPRE1 description: "APB1 prescaler\r Set and cleared by software to control the division factor of the APB1 clock (PCLK1).\r 0xx: HCLK not divided" bit_offset: 4 bit_size: 3 enum: PPRE - name: PPRE2 description: "APB2 prescaler\r Set and cleared by software to control the division factor of the APB2 clock (PCLK2).\r 0xx: HCLK not divided" bit_offset: 8 bit_size: 3 enum: PPRE - name: AHB1DIS description: "AHB1 clock disable\r This bit can be set in order to further reduce power consumption, when none of the AHB1 peripherals (except those listed hereafter) are used and when their clocks are disabled in RCC_AHB1ENR. When this bit is set, all the AHB1 peripherals clocks are off, except for FLASH, BKPSRAM, ICACHE, DCACHE1 and SRAM1." bit_offset: 16 bit_size: 1 enum: AHBDIS - name: AHB2DIS1 description: "AHB2_1 clock disable\r This bit can be set in order to further reduce power consumption, when none of the AHB2 peripherals from RCC_AHB2ENR1 (except SRAM2 and SRAM3) are used and when their clocks are disabled in RCC_AHB2ENR1. When this bit is set, all the AHB2 peripherals clocks from RCC_AHB2ENR1 are off, except for SRAM2 and SRAM3." bit_offset: 17 bit_size: 1 enum: AHBDIS - name: AHB2DIS2 description: "AHB2_2 clock disable\r This bit can be set in order to further reduce power consumption, when none of the AHB2 peripherals from RCC_AHB2ENR2 are used and when their clocks are disabled in RCC_AHB2ENR2. When this bit is set, all the AHB2 peripherals clocks from RCC_AHB2EBNR2 are off." bit_offset: 18 bit_size: 1 enum: AHBDIS - name: APB1DIS description: "APB1 clock disable\r This bit can be set in order to further reduce power consumption, when none of the APB1 peripherals (except IWDG) are used and when their clocks are disabled in RCC_APB1ENR. When this bit is set, all the APB1 peripherals clocks are off, except for IWDG." bit_offset: 19 bit_size: 1 enum: APBDIS - name: APB2DIS description: "APB2 clock disable\r This bit can be set in order to further reduce power consumption, when none of the APB2 peripherals are used and when their clocks are disabled in RCC_APB2ENR. When this bit is set, all the APB2 peripherals clocks are off." bit_offset: 20 bit_size: 1 enum: APBDIS fieldset/CFGR3: description: "RCC clock configuration register 3 " fields: - name: PPRE3 description: "APB3 prescaler\r Set and cleared by software to control the division factor of the APB3 clock (PCLK3).\r 0xx: HCLK not divided" bit_offset: 4 bit_size: 3 enum: PPRE - name: AHB3DIS description: "AHB3 clock disable\r This bit can be set in order to further reduce power consumption, when none of the AHB3 peripherals (except SRAM4) are used and when their clocks are disabled in RCC_AHB3ENR. When this bit is set, all the AHB3 peripherals clocks are off, except for SRAM4." bit_offset: 16 bit_size: 1 enum: AHBDIS - name: APB3DIS description: "APB3 clock disable\r This bit can be set in order to further reduce power consumption, when none of the APB3 peripherals from RCC_APB3ENR are used and when their clocks are disabled in RCC_APB3ENR. When this bit is set, all the APB3 peripherals clocks are off." bit_offset: 17 bit_size: 1 enum: APBDIS fieldset/CICR: description: "RCC clock interrupt clear register " fields: - name: LSIRDYC description: "LSI ready interrupt clear\r Writing this bit to 1 clears the LSIRDYF flag. Writing 0 has no effect." bit_offset: 0 bit_size: 1 - name: LSERDYC description: "LSE ready interrupt clear\r Writing this bit to 1 clears the LSERDYF flag. Writing 0 has no effect." bit_offset: 1 bit_size: 1 - name: MSISRDYC description: "MSIS ready interrupt clear\r Writing this bit to 1 clears the MSISRDYF flag. Writing 0 has no effect." bit_offset: 2 bit_size: 1 - name: HSIRDYC description: "HSI16 ready interrupt clear\r Writing this bit to 1 clears the HSIRDYF flag. Writing 0 has no effect." bit_offset: 3 bit_size: 1 - name: HSERDYC description: "HSE ready interrupt clear\r Writing this bit to 1 clears the HSERDYF flag. Writing 0 has no effect." bit_offset: 4 bit_size: 1 - name: HSI48RDYC description: "HSI48 ready interrupt clear\r Writing this bit to 1 clears the HSI48RDYF flag. Writing 0 has no effect." bit_offset: 5 bit_size: 1 - name: PLLRDYC description: "PLL1 ready interrupt clear\r Writing this bit to 1 clears the PLL1RDYF flag. Writing 0 has no effect." bit_offset: 6 bit_size: 1 array: len: 3 stride: 1 - name: CSSC description: "Clock security system interrupt clear\r Writing this bit to 1 clears the CSSF flag. Writing 0 has no effect." bit_offset: 10 bit_size: 1 - name: MSIKRDYC description: "MSIK oscillator ready interrupt clear\r Writing this bit to 1 clears the MSIKRDYF flag. Writing 0 has no effect." bit_offset: 11 bit_size: 1 - name: SHSIRDYC description: "SHSI oscillator ready interrupt clear\r Writing this bit to 1 clears the SHSIRDYF flag. Writing 0 has no effect." bit_offset: 12 bit_size: 1 fieldset/CIER: description: "RCC clock interrupt enable register " fields: - name: LSIRDYIE description: "LSI ready interrupt enable\r Set and cleared by software to enable/disable interrupt caused by the LSI oscillator stabilization." bit_offset: 0 bit_size: 1 enum: LSIRDYIE - name: LSERDYIE description: "LSE ready interrupt enable\r Set and cleared by software to enable/disable interrupt caused by the LSE oscillator stabilization." bit_offset: 1 bit_size: 1 enum: LSERDYIE - name: MSISRDYIE description: "MSIS ready interrupt enable\r Set and cleared by software to enable/disable interrupt caused by the MSIS oscillator stabilization." bit_offset: 2 bit_size: 1 enum: MSISRDYIE - name: HSIRDYIE description: "HSI16 ready interrupt enable\r Set and cleared by software to enable/disable interrupt caused by the HSI16 oscillator stabilization." bit_offset: 3 bit_size: 1 enum: HSIRDYIE - name: HSERDYIE description: "HSE ready interrupt enable\r Set and cleared by software to enable/disable interrupt caused by the HSE oscillator stabilization." bit_offset: 4 bit_size: 1 enum: HSERDYIE - name: HSI48RDYIE description: "HSI48 ready interrupt enable\r Set and cleared by software to enable/disable interrupt caused by the HSI48 oscillator stabilization." bit_offset: 5 bit_size: 1 enum: HSIRDYIE - name: PLLRDYIE description: "PLL ready interrupt enable\r Set and cleared by software to enable/disable interrupt caused by PLL1 lock." bit_offset: 6 bit_size: 1 array: len: 3 stride: 1 enum: PLLRDYIE - name: MSIKRDYIE description: "MSIK ready interrupt enable\r Set and cleared by software to enable/disable interrupt caused by the MSIK oscillator stabilization." bit_offset: 11 bit_size: 1 enum: MSIKRDYIE - name: SHSIRDYIE description: "SHSI ready interrupt enable\r Set and cleared by software to enable/disable interrupt caused by the SHSI oscillator stabilization." bit_offset: 12 bit_size: 1 enum: SHSIRDYIE fieldset/CIFR: description: "RCC clock interrupt flag register " fields: - name: LSIRDYF description: "LSI ready interrupt flag\r Set by hardware when the LSI clock becomes stable and LSIRDYIE is set.\r Cleared by software setting the LSIRDYC bit." bit_offset: 0 bit_size: 1 enum: LSIRDYF - name: LSERDYF description: "LSE ready interrupt flag\r Set by hardware when the LSE clock becomes stable and LSERDYIE is set.\r Cleared by software setting the LSERDYC bit." bit_offset: 1 bit_size: 1 enum: LSERDYF - name: MSISRDYF description: "MSIS ready interrupt flag\r Set by hardware when the MSIS clock becomes stable and MSISRDYIE is set.\r Cleared by software setting the MSISRDYC bit." bit_offset: 2 bit_size: 1 enum: MSISRDYF - name: HSIRDYF description: "HSI16 ready interrupt flag\r Set by hardware when the HSI16 clock becomes stable and HSIRDYIE is set in a response to setting the HSION (see RCC_CR). When HSION is not set but the HSI16 oscillator is enabled by the peripheral through a clock request, this bit is not set and no interrupt is generated.\r Cleared by software setting the HSIRDYC bit." bit_offset: 3 bit_size: 1 enum: HSIRDYF - name: HSERDYF description: "HSE ready interrupt flag\r Set by hardware when the HSE clock becomes stable and HSERDYIE is set.\r Cleared by software setting the HSERDYC bit." bit_offset: 4 bit_size: 1 enum: HSERDYF - name: HSI48RDYF description: "HSI48 ready interrupt flag\r Set by hardware when the HSI48 clock becomes stable and HSI48RDYIE is set.\r Cleared by software setting the HSI48RDYC bit." bit_offset: 5 bit_size: 1 enum: HSIRDYF - name: PLLRDYF description: "PLL1 ready interrupt flag\r Set by hardware when the PLL1 locks and PLL1RDYIE is set.\r Cleared by software setting the PLL1RDYC bit." bit_offset: 6 bit_size: 1 array: len: 3 stride: 1 enum: PLLRDYF - name: CSSF description: "Clock security system interrupt flag\r Set by hardware when a failure is detected in the HSE oscillator.\r Cleared by software setting the CSSC bit." bit_offset: 10 bit_size: 1 enum: CSSF - name: MSIKRDYF description: "MSIK ready interrupt flag\r Set by hardware when the MSIK clock becomes stable and MSIKRDYIE is set.\r Cleared by software setting the MSIKRDYC bit." bit_offset: 11 bit_size: 1 enum: MSIKRDYF - name: SHSIRDYF description: "SHSI ready interrupt flag\r Set by hardware when the SHSI clock becomes stable and SHSIRDYIE is set.\r Cleared by software setting the SHSIRDYC bit." bit_offset: 12 bit_size: 1 enum: SHSIRDYF fieldset/CR: description: "RCC clock control register " fields: - name: MSISON description: "MSIS clock enable\r Set and cleared by software.\r Cleared by hardware to stop the MSIS oscillator when entering Stop, Standby or Shutdown mode.\r Set by hardware to force the MSIS oscillator ON when exiting Standby or Shutdown mode.\r Set by hardware to force the MSIS oscillator ON when STOPWUCK = 0 when exiting Stop modes or in case of a failure of the HSE oscillator.\r Set by hardware when used directly or indirectly as system clock." bit_offset: 0 bit_size: 1 - name: MSIKERON description: "MSI enable for some peripheral kernels\r Set and cleared by software to force MSI ON even in Stop modes. Keeping the MSI ON in Stop mode allows the communication speed not to be reduced by the MSI startup time. This bit has no effect on MSISON and MSIKON values (see autonomous mode for more details).\r The MSIKERON must be configured at 0 before entering Stop 3 mode." bit_offset: 1 bit_size: 1 - name: MSISRDY description: "MSIS clock ready flag\r Set by hardware to indicate that the MSIS oscillator is stable. This bit is set only when MSIS is enabled by software by setting MSISON.\r Note: Once the MSISON bit is cleared, MSISRDY goes low after six MSIS clock cycles." bit_offset: 2 bit_size: 1 enum: MSISRDY - name: MSIPLLEN description: "MSI clock PLL-mode enable\r Set and cleared by software to enable/disable the PLL part of the MSI clock source.\r MSIPLLEN must be enabled after LSE is enabled (LSEON enabled) and ready (LSERDY set by hardware). A hardware protection prevents from enabling MSIPLLEN if LSE is not ready.\r This bit is cleared by hardware when LSE is disabled (LSEON = 0) or when the CSS on LSE detects a LSE failure (see RCC_CSR)." bit_offset: 3 bit_size: 1 - name: MSIKON description: "MSIK clock enable\r Set and cleared by software.\r Cleared by hardware to stop the MSIK when entering Stop, Standby or Shutdown mode.\r Set by hardware to force the MSIK oscillator ON when exiting Standby or Shutdown mode.\r Set by hardware to force the MSIK oscillator ON when STOPWUCK = 0 or STOPKERWUCK = 0 when exiting Stop modes or in case of a failure of the HSE oscillator." bit_offset: 4 bit_size: 1 - name: MSIKRDY description: "MSIK clock ready flag\r Set by hardware to indicate that the MSIK is stable. This bit is set only when MSI kernel oscillator is enabled by software by setting MSIKON.\r Note: Once the MSIKON bit is cleared, MSIKRDY goes low after six MSIK oscillator clock cycles." bit_offset: 5 bit_size: 1 enum: MSIKRDY - name: MSIPLLSEL description: "MSI clock with PLL mode selection\r Set and cleared by software to select which MSI output clock uses the PLL mode. This bit can be written only when the MSI PLL mode is disabled (MSIPLLEN = 0).\r Note: If the MSI kernel clock output uses the same oscillator source than the MSI system clock output, then the PLL mode is applied to the both clocks outputs." bit_offset: 6 bit_size: 1 enum: MSIPLLSEL - name: MSIPLLFAST description: "MSI PLL mode fast startup\r Set and reset by software to enable/disable the fast PLL mode start-up of the MSI clock\r source. This bit is used only if PLL mode is selected (MSIPLLEN = 1).\r The fast start-up feature is not active the first time the PLL mode is selected. The fast start-up is active when the MSI in PLL mode returns from switch off." bit_offset: 7 bit_size: 1 enum: MSIPLLFAST - name: HSION description: "HSI16 clock enable\r Set and cleared by software.\r Cleared by hardware to stop the HSI16 oscillator when entering Stop, Standby or Shutdown mode.\r Set by hardware to force the HSI16 oscillator ON when STOPWUCK = 1 when leaving Stop modes, or in case of failure of the HSE crystal oscillator.\r This bit is set by hardware if the HSI16 is used directly or indirectly as system clock." bit_offset: 8 bit_size: 1 - name: HSIKERON description: "HSI16 enable for some peripheral kernels\r Set and cleared by software to force HSI16 ON even in Stop modes. Keeping the HSI16 ON in Stop mode allows the communication speed not to be reduced by the HSI16 startup time. This bit has no effect on HSION value.\r Refer to for more details.\r The HSIKERON must be configured at 0 before entering Stop 3 mode." bit_offset: 9 bit_size: 1 - name: HSIRDY description: "HSI16 clock ready flag\r Set by hardware to indicate that HSI16 oscillator is stable. This bit is set only when HSI16 is enabled by software by setting HSION.\r Note: Once the HSION bit is cleared, HSIRDY goes low after six HSI16 clock cycles." bit_offset: 10 bit_size: 1 enum: HSIRDY - name: HSI48ON description: "HSI48 clock enable\r Set and cleared by software.\r Cleared by hardware to stop the HSI48 when entering in Stop, Standby or Shutdown modes." bit_offset: 12 bit_size: 1 - name: HSI48RDY description: "HSI48 clock ready flag\r Set by hardware to indicate that HSI48 oscillator is stable. This bit is set only when HSI48 is enabled by software by setting HSI48ON." bit_offset: 13 bit_size: 1 enum: HSIRDY - name: SHSION description: "SHSI clock enable\r Set and cleared by software.\r Cleared by hardware to stop the SHSI when entering in Stop, Standby or Shutdown modes." bit_offset: 14 bit_size: 1 - name: SHSIRDY description: "SHSI clock ready flag\r Set by hardware to indicate that the SHSI oscillator is stable. This bit is set only when SHSI is enabled by software by setting SHSION.\r Note: Once the SHSION bit is cleared, SHSIRDY goes low after six SHSI clock cycles." bit_offset: 15 bit_size: 1 enum: SHSIRDY - name: HSEON description: "HSE clock enable\r Set and cleared by software.\r Cleared by hardware to stop the HSE oscillator when entering Stop, Standby or Shutdown mode. This bit cannot be reset if the HSE oscillator is used directly or indirectly as the system clock." bit_offset: 16 bit_size: 1 - name: HSERDY description: "HSE clock ready flag\r Set by hardware to indicate that the HSE oscillator is stable.\r Note: Once the HSEON bit is cleared, HSERDY goes low after six HSE clock cycles." bit_offset: 17 bit_size: 1 enum: HSERDY - name: HSEBYP description: "HSE crystal oscillator bypass\r Set and cleared by software to bypass the oscillator with an external clock. The external clock must be enabled with the HSEON bit set, to be used by the device. The HSEBYP bit can be written only if the HSE oscillator is disabled." bit_offset: 18 bit_size: 1 enum: HSEBYP - name: CSSON description: "Clock security system enable\r Set by software to enable the clock security system. When CSSON is set, the clock detector is enabled by hardware when the HSE oscillator is ready, and disabled by hardware if a HSE clock failure is detected. This bit is set only and is cleared by reset." bit_offset: 19 bit_size: 1 - name: HSEEXT description: "HSE external clock bypass mode\r Set and reset by software to select the external clock mode in bypass mode. External clock mode must be configured with HSEON bit to be used by the device. This bit can be written only if the HSE oscillator is disabled. This bit is active only if the HSE bypass mode is enabled." bit_offset: 20 bit_size: 1 enum: HSEEXT - name: PLLON description: "PLL1 enable\r Set and cleared by software to enable the main PLL.\r Cleared by hardware when entering Stop, Standby or Shutdown mode. This bit cannot be reset if the PLL1 clock is used as the system clock." bit_offset: 24 bit_size: 1 array: len: 3 stride: 2 - name: PLLRDY description: "PLL1 clock ready flag\r Set by hardware to indicate that the PLL1 is locked." bit_offset: 25 bit_size: 1 array: len: 3 stride: 2 enum: PLLRDY fieldset/CRRCR: description: "RCC clock recovery RC register " fields: - name: HSI48CAL description: "HSI48 clock calibration\r These bits are initialized at startup with the factory-programmed HSI48 calibration trim value." bit_offset: 0 bit_size: 9 fieldset/CSR: description: "RCC control/status register " fields: - name: MSIKSRANGE description: "MSIK range after Standby mode\r Set by software to chose the MSIK frequency at startup. This range is used after exiting Standby mode until MSIRGSEL is set. After a NRST pin or a power-on reset or when exiting Shutdown mode, the range is always 4 MHz. MSIKSRANGE can be written only when MSIRGSEL = 1.\r others: reserved\r Note: Changing the MSIKSRANGE does not change the current MSIK frequency." bit_offset: 8 bit_size: 4 enum: MSIKSRANGE - name: MSISSRANGE description: "MSIS range after Standby mode\r Set by software to chose the MSIS frequency at startup. This range is used after exiting Standby mode until MSIRGSEL is set. After a NRST pin or a power-on reset or when exiting Shutdown mode, the range is always 4 MHz. MSISSRANGE can be written only when MSIRGSEL = 1.\r others: reserved\r Note: Changing the MSISSRANGE does not change the current MSIS frequency." bit_offset: 12 bit_size: 4 enum: MSISSRANGE - name: RMVF description: "Remove reset flag\r Set by software to clear the reset flags." bit_offset: 23 bit_size: 1 enum: RMVF - name: OBLRSTF description: "Option byte loader reset flag\r Set by hardware when a reset from the option byte loading occurs.\r Cleared by writing to the RMVF bit." bit_offset: 25 bit_size: 1 enum: OBLRSTF - name: PINRSTF description: "NRST pin reset flag\r Set by hardware when a reset from the NRST pin occurs.\r Cleared by writing to the RMVF bit." bit_offset: 26 bit_size: 1 enum: PINRSTF - name: BORRSTF description: "BOR flag\r Set by hardware when a BOR occurs.\r Cleared by writing to the RMVF bit." bit_offset: 27 bit_size: 1 enum: BORRSTF - name: SFTRSTF description: "Software reset flag\r Set by hardware when a software reset occurs.\r Cleared by writing to the RMVF bit." bit_offset: 28 bit_size: 1 enum: SFTRSTF - name: IWDGRSTF description: "Independent watchdog reset flag\r Set by hardware when an independent watchdog reset domain occurs.\r Cleared by writing to the RMVF bit." bit_offset: 29 bit_size: 1 enum: IWDGRSTF - name: WWDGRSTF description: "Window watchdog reset flag\r Set by hardware when a window watchdog reset occurs.\r Cleared by writing to the RMVF bit." bit_offset: 30 bit_size: 1 enum: WWDGRSTF - name: LPWRRSTF description: "Low-power reset flag\r Set by hardware when a reset occurs due to Stop, Standby or Shutdown mode entry, whereas the corresponding nRST_STOP, nRST_STBY or nRST_SHDW option bit is cleared.\r Cleared by writing to the RMVF bit." bit_offset: 31 bit_size: 1 enum: LPWRRSTF fieldset/ICSCR1: description: "RCC internal clock sources calibration register 1 " fields: - name: MSICAL3 description: "MSIRC3 clock calibration for MSI ranges 12 to 15\r These bits are initialized at startup with the factory-programmed MSIRC3 calibration trim value for ranges 12 to 15. When MSITRIM3 is written, MSICAL3 is updated with the sum of MSITRIM3[4:0] and the factory calibration trim value MSIRC2[4:0].\r There is no hardware protection to limit a potential overflow due to the addition of MSITRIM bitfield and factory program bitfield for this calibration value. Control must be managed by software at user level." bit_offset: 0 bit_size: 5 - name: MSICAL2 description: "MSIRC2 clock calibration for MSI ranges 8 to 11\r These bits are initialized at startup with the factory-programmed MSIRC2 calibration trim value for ranges 8 to 11. When MSITRIM2 is written, MSICAL2 is updated with the sum of MSITRIM2[4:0] and the factory calibration trim value MSIRC2[4:0].\r There is no hardware protection to limit a potential overflow due to the addition of MSITRIM bitfield and factory program bitfield for this calibration value. Control must be managed by software at user level." bit_offset: 5 bit_size: 5 - name: MSICAL1 description: "MSIRC1 clock calibration for MSI ranges 4 to 7\r These bits are initialized at startup with the factory-programmed MSIRC1 calibration trim value for ranges 4 to 7. When MSITRIM1 is written, MSICAL1 is updated with the sum of MSITRIM1[4:0] and the factory calibration trim value MSIRC1[4:0].\r There is no hardware protection to limit a potential overflow due to the addition of MSITRIM bitfield and factory program bitfield for this calibration value. Control must be managed by software at user level." bit_offset: 10 bit_size: 5 - name: MSICAL0 description: "MSIRC0 clock calibration for MSI ranges 0 to 3\r These bits are initialized at startup with the factory-programmed MSIRC0 calibration trim value for ranges 0 to 3. When MSITRIM0 is written, MSICAL0 is updated with the sum of MSITRIM0[4:0] and the factory-programmed calibration trim value MSIRC0[4:0]." bit_offset: 15 bit_size: 5 - name: MSIBIAS description: "MSI bias mode selection\r Set by software to select the MSI bias mode. By default, the MSI bias is in continuous mode in order to maintain the output clocks accuracy. Setting this bit reduces the MSI consumption under range 4 but decrease its accuracy." bit_offset: 22 bit_size: 1 enum: MSIBIAS - name: MSIRGSEL description: "MSI clock range selection\r Set by software to select the MSIS and MSIK clocks range with MSISRANGE[3:0] and MSIKRANGE[3:0]. Write 0 has no effect.\r After exiting Standby or Shutdown mode, or after a reset, this bit is at 0 and the MSIS and MSIK ranges are provided by MSISSRANGE[3:0] and MSIKSRANGE[3:0] in RCC_CSR." bit_offset: 23 bit_size: 1 enum: MSIRGSEL - name: MSIKRANGE description: "MSIK clock ranges\r These bits are configured by software to choose the frequency range of MSIK oscillator when MSIRGSEL is set. 16 frequency ranges are available:\r Note: MSIKRANGE can be modified when MSIK is OFF (MSISON = 0) or when MSIK is ready (MSIKRDY = 1). MSIKRANGE must NOT be modified when MSIK is ON and NOT ready (MSIKON = 1 and MSIKRDY = 0)\r MSIKRANGE is kept when the device wakes up from Stop mode, except when the MSIK range is above 24 MHz. In this case MSIKRANGE is changed by hardware into Range 2 (24 MHz)." bit_offset: 24 bit_size: 4 enum: MSIKRANGE - name: MSISRANGE description: "MSIS clock ranges\r These bits are configured by software to choose the frequency range of MSIS oscillator when MSIRGSEL is set. 16 frequency ranges are available:\r Note: MSISRANGE can be modified when MSIS is OFF (MSISON = 0) or when MSIS is ready (MSISRDY = 1). MSISRANGE must NOT be modified when MSIS is ON and NOT ready (MSISON = 1 and MSISRDY = 0)\r MSISRANGE is kept when the device wakes up from Stop mode, except when the MSIS range is above 24 MHz. In this case MSISRANGE is changed by hardware into Range 2 (24 MHz)." bit_offset: 28 bit_size: 4 enum: MSISRANGE fieldset/ICSCR2: description: "RCC internal clock sources calibration register 2 " fields: - name: MSITRIM3 description: "MSI clock trimming for ranges 12 to 15\r These bits provide an additional user-programmable trimming value that is added to the factory-programmed calibration trim value MSIRC3[4:0] bits. It can be programmed to adjust to voltage and temperature variations that influence the frequency of the MSI." bit_offset: 0 bit_size: 5 - name: MSITRIM2 description: "MSI clock trimming for ranges 8 to 11\r These bits provide an additional user-programmable trimming value that is added to the factory-programmed calibration trim value MSIRC2[4:0] bits. It can be programmed to adjust to voltage and temperature variations that influence the frequency of the MSI." bit_offset: 5 bit_size: 5 - name: MSITRIM1 description: "MSI clock trimming for ranges 4 to 7\r These bits provide an additional user-programmable trimming value that is added to the factory-programmed calibration trim value MSIRC1[4:0] bits. It can be programmed to adjust to voltage and temperature variations that influence the frequency of the MSI." bit_offset: 10 bit_size: 5 - name: MSITRIM0 description: "MSI clock trimming for ranges 0 to 3\r These bits provide an additional user-programmable trimming value that is added to the factory-programmed calibration trim value MSIRC0[4:0] bits. It can be programmed to adjust to voltage and temperature variations that influence the frequency of the MSI." bit_offset: 15 bit_size: 5 fieldset/ICSCR3: description: "RCC internal clock sources calibration register 3 " fields: - name: HSICAL description: "HSI clock calibration\r These bits are initialized at startup with the factory-programmed HSI calibration trim value. When HSITRIM is written, HSICAL is updated with the sum of HSITRIM and the factory trim value." bit_offset: 0 bit_size: 12 - name: HSITRIM description: "HSI clock trimming\r These bits provide an additional user-programmable trimming value that is added to the HSICAL[11:0] bits. It can be programmed to adjust to voltage and temperature variations that influence the frequency of the HSI." bit_offset: 16 bit_size: 5 fieldset/PLL1CFGR: description: "RCC PLL1 configuration register " fields: - name: PLLSRC description: "PLL1 entry clock source\r Set and cleared by software to select PLL1 clock source. These bits can be written only when the PLL1 is disabled.\r In order to save power, when no PLL1 is used, the value of PLL1SRC must be 0." bit_offset: 0 bit_size: 2 array: len: 1 stride: 0 enum: PLLSRC - name: PLLRGE description: "PLL1 input frequency range\r Set and reset by software to select the proper reference frequency range used for PLL1.\r This bit must be written before enabling the PLL1.\r 00-01-10: PLL1 input (ref1_ck) clock range frequency between 4 and 8 MHz" bit_offset: 2 bit_size: 2 array: len: 1 stride: 0 enum: PLLRGE - name: PLLFRACEN description: "PLL1 fractional latch enable\r Set and reset by software to latch the content of PLL1FRACN into the ΣΠmodulator.\r In order to latch the PLL1FRACN value into the ΣΠmodulator, PLL1FRACEN must be set to 0, then set to 1: the transition 0 to 1 transfers the content of PLL1FRACN into the modulator (see for details)." bit_offset: 4 bit_size: 1 array: len: 1 stride: 0 - name: PLLM description: "Prescaler for PLL1\r Set and cleared by software to configure the prescaler of the PLL1. The VCO1 input frequency is PLL1 input clock frequency/PLL1M.\r This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0).\r ..." bit_offset: 8 bit_size: 4 array: len: 1 stride: 0 enum: PLLM - name: PLLMBOOST description: "Prescaler for EPOD booster input clock\r Set and cleared by software to configure the prescaler of the PLL1, used for the EPOD booster. The EPOD booster input frequency is PLL1 input clock frequency/PLL1MBOOST.\r This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0) and EPOD Boost mode is disabled (see ).\r others: reserved" bit_offset: 12 bit_size: 4 array: len: 1 stride: 0 enum: PLLMBOOST - name: PLLPEN description: "PLL1 DIVP divider output enable\r Set and reset by software to enable the pll1_p_ck output of the PLL1.\r To save power, PLL1PEN and PLL1P bits must be set to 0 when the pll1_p_ck is not used.\r This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0)." bit_offset: 16 bit_size: 1 array: len: 1 stride: 0 - name: PLLQEN description: "PLL1 DIVQ divider output enable\r Set and reset by software to enable the pll1_q_ck output of the PLL1.\r To save power, PLL1QEN and PLL1Q bits must be set to 0 when the pll1_q_ck is not used.\r This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0)." bit_offset: 17 bit_size: 1 array: len: 1 stride: 0 - name: PLLREN description: "PLL1 DIVR divider output enable\r Set and reset by software to enable the pll1_r_ck output of the PLL1.\r To save power, PLL1RENPLL2REN and PLL1R bits must be set to 0 when the pll1_r_ck is not used.\r This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0)." bit_offset: 18 bit_size: 1 array: len: 1 stride: 0 fieldset/PLL1DIVR: description: "RCC PLL1 dividers register " fields: - name: PLLN description: "Multiplication factor for PLL1 VCO\r Set and reset by software to control the multiplication factor of the VCO.\r These bits can be written only when the PLL is disabled (PLL1ON = 0 and PLL1RDY = 0).\r ...\r ...\r Others: reserved\r VCO output frequency = Fref1_ck x PLL1N, when fractional value 0 has been loaded into PLL1FRACN, with:\r PLL1N between 4 and 512\r input frequency Fref1_ck between 4 and 16 MHz" bit_offset: 0 bit_size: 9 array: len: 1 stride: 0 enum: PLLN - name: PLLP description: "PLL1 DIVP division factor\r Set and reset by software to control the frequency of the pll1_p_ck clock.\r These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0).\r Note that odd division factors are not allowed.\r ..." bit_offset: 9 bit_size: 7 array: len: 1 stride: 0 enum: PLLP - name: PLLQ description: "PLL1 DIVQ division factor\r Set and reset by software to control the frequency of the pll1_q_ck clock.\r These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0).\r ..." bit_offset: 16 bit_size: 7 array: len: 1 stride: 0 enum: PLLQ - name: PLLR description: "PLL1 DIVR division factor\r Set and reset by software to control the frequency of the pll1_r_ck clock.\r These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0).\r ..." bit_offset: 24 bit_size: 7 array: len: 1 stride: 0 enum: PLLR fieldset/PLL1FRACR: description: "RCC PLL1 fractional divider register " fields: - name: PLLFRACN description: "Fractional part of the multiplication factor for PLL1 VCO\r Set and reset by software to control the fractional part of the multiplication factor of the VCO.\r These bits can be written at any time, allowing dynamic fine-tuning of the PLL1 VCO.\r VCO output frequency = Fref1_ck x (PLL1N + (PLL1FRACN / 213)), with:\r PLL1N must be between 4 and 512.\r PLL1FRACN can be between 0 and 213- 1.\r The input frequency Fref1_ck must be between 4 and 16 MHz.\r To change the FRACN value on-the-fly even if the PLL is enabled, the application must proceed as follows:\r Set the bit PLL1FRACEN to 0.\r Write the new fractional value into PLL1FRACN.\r Set the bit PLL1FRACEN to 1." bit_offset: 3 bit_size: 13 array: len: 1 stride: 0 fieldset/PLL2CFGR: description: "RCC PLL2 configuration register " fields: - name: PLLSRC description: "PLL2 entry clock source\r Set and cleared by software to select PLL2 clock source. These bits can be written only when the PLL2 is disabled.\r In order to save power, when no PLL2 is used, the value of PLL2SRC must be 0." bit_offset: 0 bit_size: 2 array: len: 1 stride: 0 enum: PLLSRC - name: PLLRGE description: "PLL2 input frequency range\r Set and reset by software to select the proper reference frequency range used for PLL2.\r This bit must be written before enabling the PLL2.\r 00-01-10: PLL2 input (ref2_ck) clock range frequency between 4 and 8 MHz" bit_offset: 2 bit_size: 2 array: len: 1 stride: 0 enum: PLLRGE - name: PLLFRACEN description: "PLL2 fractional latch enable\r Set and reset by software to latch the content of PLL2FRACN into the ΣΠmodulator.\r In order to latch the PLL2FRACN value into the ΣΠmodulator, PLL2FRACEN must be set to 0, then set to 1: the transition 0 to 1 transfers the content of PLL2FRACN into the modulator (see for details)." bit_offset: 4 bit_size: 1 array: len: 1 stride: 0 - name: PLLM description: "Prescaler for PLL2\r Set and cleared by software to configure the prescaler of the PLL2. The VCO2 input frequency is PLL2 input clock frequency/PLL2M.\r This bit can be written only when the PLL2 is disabled (PLL2ON = 0 and PLL2RDY = 0).\r ..." bit_offset: 8 bit_size: 4 array: len: 1 stride: 0 enum: PLLM - name: PLLPEN description: "PLL2 DIVP divider output enable\r Set and reset by software to enable the pll2_p_ck output of the PLL2.\r To save power, PLL2PEN and PLL2P bits must be set to 0 when the pll2_p_ck is not used.\r This bit can be written only when the PLL2 is disabled (PLL2ON = 0 and PLL2RDY = 0)." bit_offset: 16 bit_size: 1 array: len: 1 stride: 0 - name: PLLQEN description: "PLL2 DIVQ divider output enable\r Set and reset by software to enable the pll2_q_ck output of the PLL2.\r To save power, PLL2QEN and PLL2Q bits must be set to 0 when the pll2_q_ck is not used.\r This bit can be written only when the PLL2 is disabled (PLL2ON = 0 and PLL2RDY = 0." bit_offset: 17 bit_size: 1 array: len: 1 stride: 0 - name: PLLREN description: "PLL2 DIVR divider output enable\r Set and reset by software to enable the pll2_r_ck output of the PLL2.\r To save power, PLL2REN and PLL2R bits must be set to 0 when the pll2_r_ck is not used.\r This bit can be written only when the PLL2 is disabled (PLL2ON = 0 and PLL2RDY = 0)." bit_offset: 18 bit_size: 1 array: len: 1 stride: 0 fieldset/PLL2DIVR: description: "RCC PLL2 dividers configuration register " fields: - name: PLLN description: "Multiplication factor for PLL2 VCO\r Set and reset by software to control the multiplication factor of the VCO.\r These bits can be written only when the PLL is disabled (PLL2ON = 0 and PLL2RDY = 0).\r ...\r ...\r Others: reserved\r VCO output frequency = Fref2_ck x PLL2N, when fractional value 0 has been loaded into PLL2FRACN, with:\r PLL2N between 4 and 512\r input frequency Fref2_ck between 1MHz and 16MHz" bit_offset: 0 bit_size: 9 array: len: 1 stride: 0 enum: PLLN - name: PLLP description: "PLL2 DIVP division factor\r Set and reset by software to control the frequency of the pll2_p_ck clock.\r These bits can be written only when the PLL2 is disabled (PLL2ON = 0 and PLL2RDY = 0).\r ..." bit_offset: 9 bit_size: 7 array: len: 1 stride: 0 enum: PLLP - name: PLLQ description: "PLL2 DIVQ division factor\r Set and reset by software to control the frequency of the pll2_q_ck clock.\r These bits can be written only when the PLL2 is disabled (PLL2ON = 0 and PLL2RDY = 0).\r ..." bit_offset: 16 bit_size: 7 array: len: 1 stride: 0 enum: PLLQ - name: PLLR description: "PLL2 DIVR division factor\r Set and reset by software to control the frequency of the pll2_r_ck clock.\r These bits can be written only when the PLL2 is disabled (PLL2ON = 0 and PLL2RDY = 0).\r ..." bit_offset: 24 bit_size: 7 array: len: 1 stride: 0 enum: PLLR fieldset/PLL2FRACR: description: "RCC PLL2 fractional divider register " fields: - name: PLLFRACN description: "Fractional part of the multiplication factor for PLL2 VCO\r Set and reset by software to control the fractional part of the multiplication factor of the VCO.\r These bits can be written at any time, allowing dynamic fine-tuning of the PLL2 VCO.\r VCO output frequency = Fref2_ck x (PLL2N + (PLL2FRACN / 213)), with\r PLL2N must be between 4 and 512.\r PLL2FRACN can be between 0 and 213 - 1.\r The input frequency Fref2_ck must be between 4 and 16 MHz.\r In order to change the FRACN value on-the-fly even if the PLL is enabled, the application must proceed as follows:\r Set the bit PLL2FRACEN to 0.\r Write the new fractional value into PLL2FRACN.\r Set the bit PLL2FRACEN to 1." bit_offset: 3 bit_size: 13 array: len: 1 stride: 0 fieldset/PLL3CFGR: description: "RCC PLL3 configuration register " fields: - name: PLLSRC description: "PLL3 entry clock source\r Set and cleared by software to select PLL3 clock source. These bits can be written only when the PLL3 is disabled.\r In order to save power, when no PLL3 is used, the value of PLL3SRC must be 00." bit_offset: 0 bit_size: 2 array: len: 1 stride: 0 enum: PLLSRC - name: PLLRGE description: "PLL3 input frequency range\r Set and reset by software to select the proper reference frequency range used for PLL3.\r This bit must be written before enabling the PLL3.\r 00-01-10: PLL3 input (ref3_ck) clock range frequency between 4 and 8 MHz" bit_offset: 2 bit_size: 2 array: len: 1 stride: 0 enum: PLLRGE - name: PLLFRACEN description: "PLL3 fractional latch enable\r Set and reset by software to latch the content of PLL3FRACN into the ΣΠmodulator.\r In order to latch the PLL3FRACN value into the ΣΠmodulator, PLL3FRACEN must be set to 0, then set to 1: the transition 0 to 1 transfers the content of PLL3FRACN into the modulator (see for details)." bit_offset: 4 bit_size: 1 array: len: 1 stride: 0 - name: PLLM description: "Prescaler for PLL3\r Set and cleared by software to configure the prescaler of the PLL3. The VCO3 input frequency is PLL3 input clock frequency/PLL3M.\r This bit can be written only when the PLL3 is disabled (PLL3ON = 0 and PLL3RDY = 0).\r ..." bit_offset: 8 bit_size: 4 array: len: 1 stride: 0 enum: PLLM - name: PLLPEN description: "PLL3 DIVP divider output enable\r Set and reset by software to enable the pll3_p_ck output of the PLL3.\r To save power, PLL3PEN and PLL3P bits must be set to 0 when the pll3_p_ck is not used.\r This bit can be written only when the PLL3 is disabled (PLL3ON = 0 and PLL3RDY = 0)." bit_offset: 16 bit_size: 1 array: len: 1 stride: 0 - name: PLLQEN description: "PLL3 DIVQ divider output enable\r Set and reset by software to enable the pll3_q_ck output of the PLL3.\r To save power, PLL3QEN and PLL3Q bits must be set to 0 when the pll3_q_ck is not used.\r This bit can be written only when the PLL3 is disabled (PLL3ON = 0 and PLL3RDY = 0)." bit_offset: 17 bit_size: 1 array: len: 1 stride: 0 - name: PLLREN description: "PLL3 DIVR divider output enable\r Set and reset by software to enable the pll3_r_ck output of the PLL3.\r To save power, PLL3REN and PLL3R bits must be set to 0 when the pll3_r_ck is not used.\r This bit can be written only when the PLL3 is disabled (PLL3ON = 0 and PLL3RDY = 0)." bit_offset: 18 bit_size: 1 array: len: 1 stride: 0 fieldset/PLL3DIVR: description: "RCC PLL3 dividers configuration register " fields: - name: PLLN description: "Multiplication factor for PLL3 VCO\r Set and reset by software to control the multiplication factor of the VCO.\r These bits can be written only when the PLL is disabled (PLL3ON = 0 and PLL3RDY = 0).\r ...\r ...\r Others: reserved\r VCO output frequency = Fref3_ck x PLL3N, when fractional value 0 has been loaded into PLL3FRACN, with:\r PLL3N between 4 and 512\r input frequency Fref3_ck between 4 and 16MHz" bit_offset: 0 bit_size: 9 array: len: 1 stride: 0 enum: PLLN - name: PLLP description: "PLL3 DIVP division factor\r Set and reset by software to control the frequency of the pll3_p_ck clock.\r These bits can be written only when the PLL3 is disabled (PLL3ON = 0 and PLL3RDY = 0).\r ..." bit_offset: 9 bit_size: 7 array: len: 1 stride: 0 enum: PLLP - name: PLLQ description: "PLL3 DIVQ division factor\r Set and reset by software to control the frequency of the pll3_q_ck clock.\r These bits can be written only when the PLL3 is disabled (PLL3ON = 0 and PLL3RDY = 0).\r ..." bit_offset: 16 bit_size: 7 array: len: 1 stride: 0 enum: PLLQ - name: PLLR description: "PLL3 DIVR division factor\r Set and reset by software to control the frequency of the pll3_r_ck clock.\r These bits can be written only when the PLL3 is disabled (PLL3ON = 0 and PLL3RDY = 0).\r ..." bit_offset: 24 bit_size: 7 array: len: 1 stride: 0 enum: PLLR fieldset/PLL3FRACR: description: "RCC PLL3 fractional divider register " fields: - name: PLLFRACN description: "Fractional part of the multiplication factor for PLL3 VCO\r Set and reset by software to control the fractional part of the multiplication factor of the VCO.\r These bits can be written at any time, allowing dynamic fine-tuning of the PLL3 VCO.\r VCO output frequency = Fref3_ck x (PLL3N + (PLL3FRACN / 213)), with:\r PLL3N must be between 4 and 512.\r PLL3FRACN can be between 0 and 213 - 1.\r The input frequency Fref3_ck must be between 4 and 16 MHz.\r In order to change the FRACN value on-the-fly even if the PLL is enabled, the application must proceed as follows:\r Set the bit PLL3FRACEN to 0.\r Write the new fractional value into PLL3FRACN.\r Set the bit PLL3FRACEN to 1." bit_offset: 3 bit_size: 13 array: len: 1 stride: 0 fieldset/PRIVCFGR: description: "RCC privilege configuration register " fields: - name: SPRIV description: "RCC secure functions privilege configuration\r Set and reset by software. This bit can be written only by a secure privileged access." bit_offset: 0 bit_size: 1 enum: SPRIV - name: NSPRIV description: "RCC non-secure functions privilege configuration\r Set and reset by software. This bit can be written only by privileged access, secure or non-secure." bit_offset: 1 bit_size: 1 enum: NSPRIV fieldset/SECCFGR: description: "RCC secure configuration register " fields: - name: HSISEC description: "HSI clock configuration and status bits security\r Set and reset by software." bit_offset: 0 bit_size: 1 enum: HSISEC - name: HSESEC description: "HSE clock configuration bits, status bits and HSE_CSS security\r Set and reset by software." bit_offset: 1 bit_size: 1 enum: HSESEC - name: MSISEC description: "MSI clock configuration and status bits security\r Set and reset by software." bit_offset: 2 bit_size: 1 enum: MSISEC - name: LSISEC description: "LSI clock configuration and status bits security\r Set and reset by software." bit_offset: 3 bit_size: 1 enum: LSISEC - name: LSESEC description: "LSE clock configuration and status bits security\r Set and reset by software." bit_offset: 4 bit_size: 1 enum: LSESEC - name: SYSCLKSEC description: "SYSCLK clock selection, STOPWUCK bit, clock output on MCO configuration security\r Set and reset by software." bit_offset: 5 bit_size: 1 enum: SYSCLKSEC - name: PRESCSEC description: "AHBx/APBx prescaler configuration bits security\r Set and reset by software." bit_offset: 6 bit_size: 1 enum: PRESCSEC - name: PLLSEC description: "PLL1 clock configuration and status bits security\r Set and reset by software." bit_offset: 7 bit_size: 1 array: len: 3 stride: 1 enum: PLLSEC - name: ICLKSEC description: "intermediate clock source selection security\r Set and reset by software." bit_offset: 10 bit_size: 1 enum: ICLKSEC - name: HSI48SEC description: "HSI48 clock configuration and status bits security\r Set and reset by software." bit_offset: 11 bit_size: 1 enum: HSISEC - name: RMVFSEC description: "Remove reset flag security\r Set and reset by software." bit_offset: 12 bit_size: 1 enum: RMVFSEC fieldset/SRDAMR: description: "RCC SmartRun domain peripheral autonomous mode register\t" fields: - name: SPI3AMEN description: "SPI3 autonomous mode enable in Stop 0,1, 2 mode\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." bit_offset: 5 bit_size: 1 - name: LPUART1AMEN description: "LPUART1 autonomous mode enable in Stop 0,1, 2 mode\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." bit_offset: 6 bit_size: 1 - name: I2C3AMEN description: "I2C3 autonomous mode enable in Stop 0,1,2 mode\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." bit_offset: 7 bit_size: 1 - name: LPTIM1AMEN description: "LPTIM1 autonomous mode enable in Stop 0,1,2 mode\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." bit_offset: 11 bit_size: 1 - name: LPTIM3AMEN description: "LPTIM3 autonomous mode enable in Stop 0,1,2 mode\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." bit_offset: 12 bit_size: 1 - name: LPTIM4AMEN description: "LPTIM4 autonomous mode enable in Stop 0,1,2 mode\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." bit_offset: 13 bit_size: 1 - name: OPAMPAMEN description: "OPAMP autonomous mode enable in Stop 0,1,2 mode\r Set and cleared by software." bit_offset: 14 bit_size: 1 - name: COMPAMEN description: "COMP autonomous mode enable in Stop 0,1,2 mode\r Set and cleared by software." bit_offset: 15 bit_size: 1 - name: VREFAMEN description: "VREFBUF autonomous mode enable in Stop 0,1,2 mode\r Set and cleared by software." bit_offset: 20 bit_size: 1 - name: RTCAPBAMEN description: "RTC and TAMP autonomous mode enable in Stop 0,1,2 mode\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." bit_offset: 21 bit_size: 1 - name: ADC4AMEN description: "ADC4 autonomous mode enable in Stop 0,1,2 mode\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." bit_offset: 25 bit_size: 1 - name: LPGPIO1AMEN description: "LPGPIO1 autonomous mode enable in Stop 0,1,2 mode\r Set and cleared by software." bit_offset: 26 bit_size: 1 - name: DAC1AMEN description: "DAC1 autonomous mode enable in Stop 0,1,2 mode\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." bit_offset: 27 bit_size: 1 - name: LPDMA1AMEN description: "LPDMA1 autonomous mode enable in Stop 0,1,2 mode\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." bit_offset: 28 bit_size: 1 - name: ADF1AMEN description: "ADF1 autonomous mode enable in Stop 0,1,2 mode\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." bit_offset: 29 bit_size: 1 - name: SRAM4AMEN description: "SRAM4 autonomous mode enable in Stop 0,1,2 mode\r Set and cleared by software." bit_offset: 31 bit_size: 1 enum/ADCDACSEL: bit_size: 3 variants: - name: B_0x0 description: HCLK clock selected value: 0 - name: B_0x1 description: SYSCLK selected value: 1 - name: B_0x2 description: PLL2 R (pll2_r_ck) selected value: 2 - name: B_0x3 description: HSE clock selected value: 3 - name: B_0x4 description: HSI16 clock selected value: 4 - name: B_0x5 description: MSIK clock selected value: 5 enum/ADFSEL: bit_size: 3 variants: - name: B_0x0 description: HCLK selected value: 0 - name: B_0x1 description: PLL1 P (pll1_p_ck) selected value: 1 - name: B_0x2 description: PLL3 Q (pll3_q_ck) selected value: 2 - name: B_0x3 description: input pin AUDIOCLK selected value: 3 - name: B_0x4 description: MSIK clock selected value: 4 enum/AHBDIS: bit_size: 1 variants: - name: B_0x0 description: "AHB2_2 clock enabled, distributed to peripherals according to their dedicated clock enable control bits" value: 0 - name: B_0x1 description: AHB2_2 clock disabled value: 1 enum/APBDIS: bit_size: 1 variants: - name: B_0x0 description: "APB2 clock enabled, distributed to peripherals according to their dedicated clock enable control bits" value: 0 - name: B_0x1 description: APB2 clock disabled value: 1 enum/BORRSTF: bit_size: 1 variants: - name: B_0x0 description: No BOR occurred value: 0 - name: B_0x1 description: BOR occurred value: 1 enum/CSSF: bit_size: 1 variants: - name: B_0x0 description: No clock security interrupt caused by HSE clock failure value: 0 - name: B_0x1 description: Clock security interrupt caused by HSE clock failure value: 1 enum/DACSEL: bit_size: 1 variants: - name: B_0x0 description: LSE selected value: 0 - name: B_0x1 description: LSI selected value: 1 enum/FDCANSEL: bit_size: 2 variants: - name: B_0x0 description: "HSE clock selected " value: 0 - name: B_0x1 description: PLL1 Q (pll1_q_ck) selected value: 1 - name: B_0x2 description: PLL2 P (pll2_p_ck) selected value: 2 enum/HPRE: bit_size: 4 variants: - name: B_0x8 description: SYSCLK divided by 2 value: 8 - name: B_0x9 description: SYSCLK divided by 4 value: 9 - name: B_0xA description: SYSCLK divided by 8 value: 10 - name: B_0xB description: SYSCLK divided by 16 value: 11 - name: B_0xC description: SYSCLK divided by 64 value: 12 - name: B_0xD description: SYSCLK divided by 128 value: 13 - name: B_0xE description: SYSCLK divided by 256 value: 14 - name: B_0xF description: SYSCLK divided by 512 value: 15 enum/HSEBYP: bit_size: 1 variants: - name: B_0x0 description: HSE crystal oscillator not bypassed value: 0 - name: B_0x1 description: HSE crystal oscillator bypassed with external clock value: 1 enum/HSEEXT: bit_size: 1 variants: - name: B_0x0 description: external HSE clock analog mode value: 0 - name: B_0x1 description: external HSE clock digital mode (through I/O Schmitt trigger) value: 1 enum/HSERDY: bit_size: 1 variants: - name: B_0x0 description: HSE oscillator not ready value: 0 - name: B_0x1 description: "HSE oscillator ready " value: 1 enum/HSERDYF: bit_size: 1 variants: - name: B_0x0 description: No clock ready interrupt caused by the HSE oscillator value: 0 - name: B_0x1 description: Clock ready interrupt caused by the HSE oscillator value: 1 enum/HSERDYIE: bit_size: 1 variants: - name: B_0x0 description: HSE ready interrupt disabled value: 0 - name: B_0x1 description: HSE ready interrupt enabled value: 1 enum/HSESEC: bit_size: 1 variants: - name: B_0x0 description: non secure value: 0 - name: B_0x1 description: secure value: 1 enum/HSIRDY: bit_size: 1 variants: - name: B_0x0 description: HSI16 oscillator not ready value: 0 - name: B_0x1 description: HSI16 oscillator ready value: 1 enum/HSIRDYF: bit_size: 1 variants: - name: B_0x0 description: No clock ready interrupt caused by the HSI16 oscillator value: 0 - name: B_0x1 description: Clock ready interrupt caused by the HSI16 oscillator value: 1 enum/HSIRDYIE: bit_size: 1 variants: - name: B_0x0 description: HSI16 ready interrupt disabled value: 0 - name: B_0x1 description: HSI16 ready interrupt enabled value: 1 enum/HSISEC: bit_size: 1 variants: - name: B_0x0 description: non secure value: 0 - name: B_0x1 description: secure value: 1 enum/ICLKSEC: bit_size: 1 variants: - name: B_0x0 description: non secure value: 0 - name: B_0x1 description: secure value: 1 enum/ICLKSEL: bit_size: 2 variants: - name: B_0x0 description: HSI48 clock selected value: 0 - name: B_0x1 description: PLL2 Q (pll2_q_ck) selected value: 1 - name: B_0x2 description: PLL1 Q (pll1_q_ck) selected value: 2 - name: B_0x3 description: MSIK clock selected value: 3 enum/ICSEL: bit_size: 2 variants: - name: B_0x0 description: PCLK1 selected value: 0 - name: B_0x1 description: SYSCLK selected value: 1 - name: B_0x2 description: HSI16 selected value: 2 - name: B_0x3 description: MSIK selected value: 3 enum/IWDGRSTF: bit_size: 1 variants: - name: B_0x0 description: No independent watchdog reset occurred value: 0 - name: B_0x1 description: Independent watchdog reset occurred value: 1 enum/LPTIMSEL: bit_size: 2 variants: - name: B_0x0 description: PCLK1 selected value: 0 - name: B_0x1 description: LSI selected value: 1 - name: B_0x2 description: HSI16 selected value: 2 - name: B_0x3 description: LSE selected value: 3 enum/LPUARTSEL: bit_size: 3 variants: - name: B_0x0 description: PCLK3 selected value: 0 - name: B_0x1 description: SYSCLK selected value: 1 - name: B_0x2 description: HSI16 selected value: 2 - name: B_0x3 description: LSE selected value: 3 - name: B_0x4 description: MSIK selected value: 4 enum/LPWRRSTF: bit_size: 1 variants: - name: B_0x0 description: No illegal low-power mode reset occurred value: 0 - name: B_0x1 description: Illegal low-power mode reset occurred value: 1 enum/LSCOSEL: bit_size: 1 variants: - name: B_0x0 description: LSI clock selected value: 0 - name: B_0x1 description: LSE clock selected value: 1 enum/LSEBYP: bit_size: 1 variants: - name: B_0x0 description: LSE oscillator not bypassed value: 0 - name: B_0x1 description: LSE oscillator bypassed value: 1 enum/LSECSSD: bit_size: 1 variants: - name: B_0x0 description: No failure detected on LSE value: 0 - name: B_0x1 description: Failure detected on LSE value: 1 enum/LSEDRV: bit_size: 2 variants: - name: B_0x0 description: "'Xtal mode lower driving capability" value: 0 - name: B_0x1 description: "'Xtal mode medium-low driving capability" value: 1 - name: B_0x2 description: "'Xtal mode medium-high driving capability" value: 2 - name: B_0x3 description: "'Xtal mode higher driving capability " value: 3 enum/LSERDY: bit_size: 1 variants: - name: B_0x0 description: LSE oscillator not ready value: 0 - name: B_0x1 description: LSE oscillator ready value: 1 enum/LSERDYF: bit_size: 1 variants: - name: B_0x0 description: No clock ready interrupt caused by the LSE oscillator value: 0 - name: B_0x1 description: Clock ready interrupt caused by the LSE oscillator value: 1 enum/LSERDYIE: bit_size: 1 variants: - name: B_0x0 description: LSE ready interrupt disabled value: 0 - name: B_0x1 description: LSE ready interrupt enabled value: 1 enum/LSESEC: bit_size: 1 variants: - name: B_0x0 description: non secure value: 0 - name: B_0x1 description: secure value: 1 enum/LSESYSRDY: bit_size: 1 variants: - name: B_0x0 description: LSESYS clock not ready value: 0 - name: B_0x1 description: LSESYS clock ready value: 1 enum/LSIPREDIV: bit_size: 1 variants: - name: B_0x0 description: LSI not divided value: 0 - name: B_0x1 description: LSI divided by 128 value: 1 enum/LSIRDY: bit_size: 1 variants: - name: B_0x0 description: LSI oscillator not ready value: 0 - name: B_0x1 description: LSI oscillator ready value: 1 enum/LSIRDYF: bit_size: 1 variants: - name: B_0x0 description: No clock ready interrupt caused by the LSI oscillator value: 0 - name: B_0x1 description: Clock ready interrupt caused by the LSI oscillator value: 1 enum/LSIRDYIE: bit_size: 1 variants: - name: B_0x0 description: LSI ready interrupt disabled value: 0 - name: B_0x1 description: LSI ready interrupt enabled value: 1 enum/LSISEC: bit_size: 1 variants: - name: B_0x0 description: non secure value: 0 - name: B_0x1 description: secure value: 1 enum/MCOPRE: bit_size: 3 variants: - name: B_0x0 description: MCO divided by 1 value: 0 - name: B_0x1 description: MCO divided by 2 value: 1 - name: B_0x2 description: MCO divided by 4 value: 2 - name: B_0x3 description: MCO divided by 8 value: 3 - name: B_0x4 description: MCO divided by 16 value: 4 enum/MCOSEL: bit_size: 4 variants: - name: B_0x0 description: "MCO output disabled, no clock on MCO" value: 0 - name: B_0x1 description: SYSCLK system clock selected value: 1 - name: B_0x2 description: MSIS clock selected value: 2 - name: B_0x3 description: HSI16 clock selected value: 3 - name: B_0x4 description: HSE clock selected value: 4 - name: B_0x5 description: Main PLL clock pll1_r_ck selected value: 5 - name: B_0x6 description: LSI clock selected value: 6 - name: B_0x7 description: LSE clock selected value: 7 - name: B_0x8 description: Internal HSI48 clock selected value: 8 - name: B_0x9 description: MSIK clock selected value: 9 enum/MDFSEL: bit_size: 3 variants: - name: B_0x0 description: HCLK selected value: 0 - name: B_0x1 description: PLL1 P (pll1_p_ck) selected value: 1 - name: B_0x2 description: PLL3 Q (pll3_q_ck) selected value: 2 - name: B_0x3 description: input pin AUDIOCLK selected value: 3 - name: B_0x4 description: MSIK clock selected value: 4 enum/MSIBIAS: bit_size: 1 variants: - name: B_0x0 description: MSI bias continuous mode (clock accuracy fast settling time) value: 0 - name: B_0x1 description: MSI bias sampling mode (ultra-low-power mode) value: 1 enum/MSIKRANGE: bit_size: 4 variants: - name: B_0x0 description: "range 0 around 48 MHz " value: 0 - name: B_0x1 description: "range 1 around 24 MHz " value: 1 - name: B_0x2 description: "range 2 around 16 MHz " value: 2 - name: B_0x3 description: "range 3 around 12 MHz " value: 3 - name: B_0x4 description: "range 4 around 4 MHz (reset value) " value: 4 - name: B_0x5 description: "range 5 around 2 MHz " value: 5 - name: B_0x6 description: "range 6 around 1.33 MHz " value: 6 - name: B_0x7 description: "range 7 around 1 MHz " value: 7 - name: B_0x8 description: "range 8 around 3.072 MHz " value: 8 - name: B_0x9 description: "range 9 around 1.536 MHz " value: 9 - name: B_0xA description: "range 10 around 1.024 MHz " value: 10 - name: B_0xB description: "range 11 around 768 kHz " value: 11 - name: B_0xC description: "range 12 around 400 kHz " value: 12 - name: B_0xD description: "range 13 around 200 kHz " value: 13 - name: B_0xE description: range 14 around 133 kHz value: 14 - name: B_0xF description: "range 15 around 100 kHz " value: 15 enum/MSIKRDY: bit_size: 1 variants: - name: B_0x0 description: MSIK (MSI kernel) oscillator not ready value: 0 - name: B_0x1 description: MSIK (MSI kernel) oscillator ready value: 1 enum/MSIKRDYF: bit_size: 1 variants: - name: B_0x0 description: No clock ready interrupt caused by the MSIK oscillator value: 0 - name: B_0x1 description: Clock ready interrupt caused by the MSIK oscillator value: 1 enum/MSIKRDYIE: bit_size: 1 variants: - name: B_0x0 description: MSIK ready interrupt disabled value: 0 - name: B_0x1 description: MSIK ready interrupt enabled value: 1 enum/MSIKSRANGE: bit_size: 4 variants: - name: B_0x4 description: "range 4 around 4M Hz (reset value) " value: 4 - name: B_0x5 description: "range 5 around 2 MHz " value: 5 - name: B_0x6 description: "range 6 around 1.5 MHz " value: 6 - name: B_0x7 description: "range 7 around 1 MHz " value: 7 - name: B_0x8 description: "range 8 around 3.072 MHz " value: 8 enum/MSIPLLFAST: bit_size: 1 variants: - name: B_0x0 description: MSI PLL normal start-up value: 0 - name: B_0x1 description: MSI PLL fast start-up value: 1 enum/MSIPLLSEL: bit_size: 1 variants: - name: B_0x0 description: "PLL mode applied to MSIK (MSI kernel) clock output " value: 0 - name: B_0x1 description: PLL mode applied to MSIS (MSI system) clock output value: 1 enum/MSIRGSEL: bit_size: 1 variants: - name: B_0x0 description: "MSIS/MSIK ranges provided by MSISSRANGE[3:0] and MSIKSRANGE[3:0] in RCC_CSR" value: 0 - name: B_0x1 description: "MSIS/MSIK ranges provided by MSISRANGE[3:0] and MSIKRANGE[3:0] in RCC_ICSCR1" value: 1 enum/MSISEC: bit_size: 1 variants: - name: B_0x0 description: non secure value: 0 - name: B_0x1 description: secure value: 1 enum/MSISRANGE: bit_size: 4 variants: - name: B_0x0 description: "range 0 around 48 MHz " value: 0 - name: B_0x1 description: "range 1 around 24 MHz " value: 1 - name: B_0x2 description: "range 2 around 16 MHz " value: 2 - name: B_0x3 description: "range 3 around 12 MHz " value: 3 - name: B_0x4 description: "range 4 around 4 MHz (reset value) " value: 4 - name: B_0x5 description: "range 5 around 2 MHz " value: 5 - name: B_0x6 description: "range 6 around 1.33 MHz " value: 6 - name: B_0x7 description: "range 7 around 1 MHz " value: 7 - name: B_0x8 description: "range 8 around 3.072 MHz " value: 8 - name: B_0x9 description: "range 9 around 1.536 MHz " value: 9 - name: B_0xA description: "range 10 around 1.024 MHz " value: 10 - name: B_0xB description: "range 11 around 768 kHz " value: 11 - name: B_0xC description: "range 12 around 400 kHz " value: 12 - name: B_0xD description: "range 13 around 200 kHz " value: 13 - name: B_0xE description: range 14 around 133 kHz value: 14 - name: B_0xF description: "range 15 around 100 kHz " value: 15 enum/MSISRDY: bit_size: 1 variants: - name: B_0x0 description: MSIS (MSI system) oscillator not ready value: 0 - name: B_0x1 description: MSIS (MSI system) oscillator ready value: 1 enum/MSISRDYF: bit_size: 1 variants: - name: B_0x0 description: No clock ready interrupt caused by the MSIS oscillator value: 0 - name: B_0x1 description: Clock ready interrupt caused by the MSIS oscillator value: 1 enum/MSISRDYIE: bit_size: 1 variants: - name: B_0x0 description: MSIS ready interrupt disabled value: 0 - name: B_0x1 description: MSIS ready interrupt enabled value: 1 enum/MSISSRANGE: bit_size: 4 variants: - name: B_0x4 description: "range 4 around 4M Hz (reset value) " value: 4 - name: B_0x5 description: "range 5 around 2 MHz " value: 5 - name: B_0x6 description: "range 6 around 1.5 MHz " value: 6 - name: B_0x7 description: "range 7 around 1 MHz " value: 7 - name: B_0x8 description: "range 8 around 3.072 MHz " value: 8 enum/NSPRIV: bit_size: 1 variants: - name: B_0x0 description: Read and write to RCC non-secure functions can be done by privileged or unprivileged access. value: 0 - name: B_0x1 description: Read and write to RCC non-secure functions can be done by privileged access only. value: 1 enum/OBLRSTF: bit_size: 1 variants: - name: B_0x0 description: No reset from option byte loading occurred value: 0 - name: B_0x1 description: Reset from option byte loading occurred value: 1 enum/OCTOSPISEL: bit_size: 2 variants: - name: B_0x0 description: SYSCLK selected value: 0 - name: B_0x1 description: MSIK selected value: 1 - name: B_0x2 description: "PLL1 Q (pll1_q_ck) selected, can be up to 200 MHz" value: 2 - name: B_0x3 description: "PLL2 Q (pll2_q_ck) selected, can be up to 200 MHz" value: 3 enum/PINRSTF: bit_size: 1 variants: - name: B_0x0 description: No reset from NRST pin occurred value: 0 - name: B_0x1 description: Reset from NRST pin occurred value: 1 enum/PLLM: bit_size: 4 variants: - name: B_0x0 description: division by 1 (bypass) value: 0 - name: B_0x1 description: division by 2 value: 1 - name: B_0x2 description: division by 3 value: 2 - name: B_0xF description: division by 16 value: 15 enum/PLLMBOOST: bit_size: 4 variants: - name: B_0x0 description: division by 1 (bypass) value: 0 - name: B_0x1 description: division by 2 value: 1 - name: B_0x2 description: division by 4 value: 2 - name: B_0x3 description: division by 6 value: 3 - name: B_0x4 description: division by 8 value: 4 - name: B_0x5 description: division by 10 value: 5 - name: B_0x6 description: division by 12 value: 6 - name: B_0x7 description: division by 14 value: 7 - name: B_0x8 description: division by 16 value: 8 enum/PLLN: bit_size: 9 variants: - name: B_0x3 description: "PLL1N = 4 " value: 3 - name: B_0x4 description: "PLL1N = 5 " value: 4 - name: B_0x5 description: "PLL1N = 6 " value: 5 - name: B_0x80 description: PLL1N = 129 (default after reset) value: 128 - name: B_0x1FF description: PLL1N = 512 value: 511 enum/PLLP: bit_size: 7 variants: - name: B_0x0 description: pll3_p_ck = vco3_ck value: 0 - name: B_0x1 description: pll3_p_ck = vco3_ck / 2 (default after reset) value: 1 - name: B_0x2 description: pll3_p_ck = vco3_ck / 3 value: 2 - name: B_0x3 description: pll3_p_ck = vco3_ck / 4 value: 3 - name: B_0x7F description: pll3_p_ck = vco3_ck / 128 value: 127 enum/PLLQ: bit_size: 7 variants: - name: B_0x0 description: "pll3_q_ck = vco3_ck " value: 0 - name: B_0x1 description: pll3_q_ck = vco3_ck / 2 (default after reset) value: 1 - name: B_0x2 description: pll3_q_ck = vco3_ck / 3 value: 2 - name: B_0x3 description: pll3_q_ck = vco3_ck / 4 value: 3 - name: B_0x7F description: pll3_q_ck = vco3_ck / 128 value: 127 enum/PLLR: bit_size: 7 variants: - name: B_0x0 description: "pll2_r_ck = vco2_ck " value: 0 - name: B_0x1 description: pll2_r_ck = vco2_ck / 2 (default after reset) value: 1 - name: B_0x2 description: pll2_r_ck = vco2_ck / 3 value: 2 - name: B_0x3 description: pll2_r_ck = vco2_ck / 4 value: 3 - name: B_0x7F description: pll2_r_ck = vco2_ck / 128 value: 127 enum/PLLRDY: bit_size: 1 variants: - name: B_0x0 description: PLL3 unlocked value: 0 - name: B_0x1 description: PLL3 locked value: 1 enum/PLLRDYF: bit_size: 1 variants: - name: B_0x0 description: No clock ready interrupt caused by PLL1 lock value: 0 - name: B_0x1 description: Clock ready interrupt caused by PLL1 lock value: 1 enum/PLLRDYIE: bit_size: 1 variants: - name: B_0x0 description: PLL1 lock interrupt disabled value: 0 - name: B_0x1 description: PLL1 lock interrupt enabled value: 1 enum/PLLRGE: bit_size: 2 variants: - name: B_0x3 description: PLL2 input (ref2_ck) clock range frequency between 8 and 16 MHz value: 3 enum/PLLSEC: bit_size: 1 variants: - name: B_0x0 description: non secure value: 0 - name: B_0x1 description: secure value: 1 enum/PLLSRC: bit_size: 2 variants: - name: B_0x0 description: No clock sent to PLL3 value: 0 - name: B_0x1 description: MSIS clock selected as PLL3 clock entry value: 1 - name: B_0x2 description: HSI16 clock selected as PLL3 clock entry value: 2 - name: B_0x3 description: HSE clock selected as PLL3 clock entry value: 3 enum/PPRE: bit_size: 3 variants: - name: B_0x4 description: HCLK divided by 2 value: 4 - name: B_0x5 description: HCLK divided by 4 value: 5 - name: B_0x6 description: HCLK divided by 8 value: 6 - name: B_0x7 description: HCLK divided by 16 value: 7 enum/PRESCSEC: bit_size: 1 variants: - name: B_0x0 description: non secure value: 0 - name: B_0x1 description: secure value: 1 enum/RMVF: bit_size: 1 variants: - name: B_0x0 description: No effect value: 0 - name: B_0x1 description: Clear the reset flags value: 1 enum/RMVFSEC: bit_size: 1 variants: - name: B_0x0 description: non secure value: 0 - name: B_0x1 description: secure value: 1 enum/RNGSEL: bit_size: 2 variants: - name: B_0x0 description: "HSI48 selected " value: 0 - name: B_0x1 description: "HSI48 / 2 selected, can be used in Range 4" value: 1 - name: B_0x2 description: HSI16 selected value: 2 enum/RTCSEL: bit_size: 2 variants: - name: B_0x0 description: No clock selected value: 0 - name: B_0x1 description: LSE oscillator clock selected value: 1 - name: B_0x2 description: LSI oscillator clock selected value: 2 - name: B_0x3 description: HSE oscillator clock divided by 32 selected value: 3 enum/SAESSEL: bit_size: 1 variants: - name: B_0x0 description: SHSI selected value: 0 - name: B_0x1 description: "SHSI / 2 selected, can be used in Range 4" value: 1 enum/SAISEL: bit_size: 3 variants: - name: B_0x0 description: PLL2 P (pll2_p_ck) selected value: 0 - name: B_0x1 description: PLL3 P (pll3_p_ck) selected value: 1 - name: B_0x2 description: PLL1 P (pll1_p_ck) selected value: 2 - name: B_0x3 description: input pin AUDIOCLK selected value: 3 - name: B_0x4 description: HSI16 clock selected value: 4 enum/SDMMCSEL: bit_size: 1 variants: - name: B_0x0 description: ICLK clock selected value: 0 - name: B_0x1 description: "PLL1 P (pll1_p_ck) selected, in case higher than 48 MHz is needed (for SDR50 mode) " value: 1 enum/SFTRSTF: bit_size: 1 variants: - name: B_0x0 description: No software reset occurred value: 0 - name: B_0x1 description: Software reset occurred value: 1 enum/SHSIRDY: bit_size: 1 variants: - name: B_0x0 description: SHSI oscillator not ready value: 0 - name: B_0x1 description: "SHSI oscillator ready " value: 1 enum/SHSIRDYF: bit_size: 1 variants: - name: B_0x0 description: No clock ready interrupt caused by the SHSI oscillator value: 0 - name: B_0x1 description: Clock ready interrupt caused by the SHSI oscillator value: 1 enum/SHSIRDYIE: bit_size: 1 variants: - name: B_0x0 description: SHSI ready interrupt disabled value: 0 - name: B_0x1 description: SHSI ready interrupt enabled value: 1 enum/SPISEL: bit_size: 2 variants: - name: B_0x0 description: PCLK2 selected value: 0 - name: B_0x1 description: SYSCLK selected value: 1 - name: B_0x2 description: HSI16 selected value: 2 - name: B_0x3 description: MSIK selected value: 3 enum/SPRIV: bit_size: 1 variants: - name: B_0x0 description: Read and write to RCC secure functions can be done by privileged or unprivileged access. value: 0 - name: B_0x1 description: Read and write to RCC secure functions can be done by privileged access only. value: 1 enum/STOPKERWUCK: bit_size: 1 variants: - name: B_0x0 description: MSIK oscillator automatically enabled when exiting Stop mode value: 0 - name: B_0x1 description: HSI16 oscillator automatically enabled when exiting Stop mode value: 1 enum/STOPWUCK: bit_size: 1 variants: - name: B_0x0 description: MSIS oscillator selected as wakeup from stop clock and CSS backup clock value: 0 - name: B_0x1 description: HSI16 oscillator selected as wakeup from stop clock and CSS backup clock value: 1 enum/SW: bit_size: 2 variants: - name: B_0x0 description: MSIS selected as system clock value: 0 - name: B_0x1 description: HSI16 selected as system clock value: 1 - name: B_0x2 description: HSE selected as system clock value: 2 - name: B_0x3 description: PLL pll1_r_ck selected as system clock value: 3 enum/SWS: bit_size: 2 variants: - name: B_0x0 description: MSIS oscillator used as system clock value: 0 - name: B_0x1 description: HSI16 oscillator used as system clock value: 1 - name: B_0x2 description: HSE used as system clock value: 2 - name: B_0x3 description: PLL pll1_r_ck used as system clock value: 3 enum/SYSCLKSEC: bit_size: 1 variants: - name: B_0x0 description: non secure value: 0 - name: B_0x1 description: secure value: 1 enum/SYSTICKSEL: bit_size: 2 variants: - name: B_0x0 description: HCLK/8 selected value: 0 - name: B_0x1 description: LSI selected value: 1 - name: B_0x2 description: LSE selected value: 2 enum/TIMICSEL: bit_size: 3 variants: - name: B_0x4 description: "HSI/256, MSIS/1024 and MSIS/4 generated and can be selected by TIM16, TIM17 and LPTIM2 as internal input capture" value: 4 - name: B_0x5 description: "HSI/256, MSIS/1024 and MSIK/4 generated and can be selected by TIM16, TIM17 and LPTIM2 as internal input capture" value: 5 - name: B_0x6 description: "HSI/256, MSIK/1024 and MSIS/4 generated and can be selected by TIM16, TIM17 and LPTIM2 as internal input capture" value: 6 - name: B_0x7 description: "HSI/256, MSIK/1024 and MSIK/4 generated and can be selected by TIM16, TIM17 and LPTIM2 as internal input capture" value: 7 enum/UARTSEL: bit_size: 2 variants: - name: B_0x0 description: PCLK1 selected value: 0 - name: B_0x1 description: SYSCLK selected value: 1 - name: B_0x2 description: HSI16 selected value: 2 - name: B_0x3 description: LSE selected value: 3 enum/USARTSEL: bit_size: 2 variants: - name: B_0x0 description: PCLK2 selected value: 0 - name: B_0x1 description: SYSCLK selected value: 1 - name: B_0x2 description: HSI16 selected value: 2 - name: B_0x3 description: LSE selected value: 3 enum/WWDGRSTF: bit_size: 1 variants: - name: B_0x0 description: No window watchdog reset occurred value: 0 - name: B_0x1 description: Window watchdog reset occurred value: 1