block/RCC: description: Reset and clock control items: - name: CR description: Clock control register byte_offset: 0 fieldset: CR - name: ICSCR description: Internal clock sources calibration register byte_offset: 4 fieldset: ICSCR - name: CFGR description: Clock configuration register byte_offset: 12 fieldset: CFGR - name: CIER description: Clock interrupt enable register byte_offset: 16 access: Read fieldset: CIER - name: CIFR description: Clock interrupt flag register byte_offset: 20 access: Read fieldset: CIFR - name: CICR description: Clock interrupt clear register byte_offset: 24 access: Read fieldset: CICR - name: GPIORSTR description: GPIO reset register byte_offset: 28 fieldset: GPIORSTR - name: AHBRSTR description: AHB peripheral reset register byte_offset: 32 fieldset: AHBRSTR - name: APB2RSTR description: APB2 peripheral reset register byte_offset: 36 fieldset: APB2RSTR - name: APB1RSTR description: APB1 peripheral reset register byte_offset: 40 fieldset: APB1RSTR - name: GPIOENR description: GPIO clock enable register byte_offset: 44 fieldset: GPIOENR - name: AHBENR description: AHB peripheral clock enable register byte_offset: 48 fieldset: AHBENR - name: APB2ENR description: APB2 peripheral clock enable register byte_offset: 52 fieldset: APB2ENR - name: APB1ENR description: APB1 peripheral clock enable register byte_offset: 56 fieldset: APB1ENR - name: GPIOSMEN description: GPIO clock enable in sleep mode register byte_offset: 60 fieldset: GPIOSMEN - name: AHBSMENR description: AHB peripheral clock enable in sleep mode register byte_offset: 64 fieldset: AHBSMENR - name: APB2SMENR description: APB2 peripheral clock enable in sleep mode register byte_offset: 68 fieldset: APB2SMENR - name: APB1SMENR description: APB1 peripheral clock enable in sleep mode register byte_offset: 72 fieldset: APB1SMENR - name: CCIPR description: Clock configuration register byte_offset: 76 fieldset: CCIPR - name: CSR description: Control and status register byte_offset: 80 fieldset: CSR fieldset/AHBENR: description: AHB peripheral clock enable register fields: - name: DMA1EN description: DMA clock enable bit_offset: 0 bit_size: 1 - name: MIFEN description: NVM interface clock enable bit_offset: 8 bit_size: 1 - name: CRCEN description: CRC clock enable bit_offset: 12 bit_size: 1 - name: TSCEN description: Touch Sensing clock enable bit_offset: 16 bit_size: 1 - name: RNGEN description: Random Number Generator clock enable bit_offset: 20 bit_size: 1 - name: CRYPEN description: Crypto clock enable bit_offset: 24 bit_size: 1 fieldset/AHBRSTR: description: AHB peripheral reset register fields: - name: DMA1RST description: DMA reset bit_offset: 0 bit_size: 1 - name: MIFRST description: Memory interface reset bit_offset: 8 bit_size: 1 - name: CRCRST description: Test integration module reset bit_offset: 12 bit_size: 1 - name: TSCRST description: Touch Sensing reset bit_offset: 16 bit_size: 1 - name: RNGRST description: Random Number Generator module reset bit_offset: 20 bit_size: 1 - name: CRYPRST description: Crypto module reset bit_offset: 24 bit_size: 1 fieldset/AHBSMENR: description: AHB peripheral clock enable in sleep mode register fields: - name: DMA1SMEN description: DMA clock enable during sleep mode bit_offset: 0 bit_size: 1 - name: MIFSMEN description: NVM interface clock enable during sleep mode bit_offset: 8 bit_size: 1 - name: SRAMSMEN description: SRAM interface clock enable during sleep mode bit_offset: 9 bit_size: 1 - name: CRCSMEN description: CRC clock enable during sleep mode bit_offset: 12 bit_size: 1 - name: TSCSMEN description: Touch Sensing clock enable during sleep mode bit_offset: 16 bit_size: 1 - name: RNGSMEN description: Random Number Generator clock enable during sleep mode bit_offset: 20 bit_size: 1 - name: CRYPSMEN description: Crypto clock enable during sleep mode bit_offset: 24 bit_size: 1 fieldset/APB1ENR: description: APB1 peripheral clock enable register fields: - name: TIM2EN description: Timer2 clock enable bit_offset: 0 bit_size: 1 - name: TIM3EN description: Timer 3 clock enbale bit_offset: 1 bit_size: 1 - name: TIM6EN description: Timer 6 clock enable bit_offset: 4 bit_size: 1 - name: TIM7EN description: Timer 7 clock enable bit_offset: 5 bit_size: 1 - name: WWDGEN description: Window watchdog clock enable bit_offset: 11 bit_size: 1 - name: SPI2EN description: SPI2 clock enable bit_offset: 14 bit_size: 1 - name: USART2EN description: UART2 clock enable bit_offset: 17 bit_size: 1 - name: LPUART1EN description: LPUART1 clock enable bit_offset: 18 bit_size: 1 - name: USART4EN description: USART4 clock enable bit_offset: 19 bit_size: 1 - name: USART5EN description: USART5 clock enable bit_offset: 20 bit_size: 1 - name: I2C1EN description: I2C1 clock enable bit_offset: 21 bit_size: 1 - name: I2C2EN description: I2C2 clock enable bit_offset: 22 bit_size: 1 - name: USBEN description: USB clock enable bit_offset: 23 bit_size: 1 - name: CRSEN description: Clock recovery system clock enable bit_offset: 27 bit_size: 1 - name: PWREN description: Power interface clock enable bit_offset: 28 bit_size: 1 - name: DACEN description: DAC interface clock enable bit_offset: 29 bit_size: 1 - name: I2C3EN description: I2C3 clock enable bit_offset: 30 bit_size: 1 - name: LPTIM1EN description: Low power timer clock enable bit_offset: 31 bit_size: 1 fieldset/APB1RSTR: description: APB1 peripheral reset register fields: - name: TIM2RST description: Timer 2 reset bit_offset: 0 bit_size: 1 - name: TIM3RST description: Timer 3 reset bit_offset: 1 bit_size: 1 - name: TIM6RST description: Timer 6 reset bit_offset: 4 bit_size: 1 - name: TIM7RST description: Timer 7 reset bit_offset: 5 bit_size: 1 - name: WWDGRST description: Window watchdog reset bit_offset: 11 bit_size: 1 - name: SPI2RST description: SPI2 reset bit_offset: 14 bit_size: 1 - name: USART2RST description: USART2 reset bit_offset: 17 bit_size: 1 - name: LPUART1RST description: LPUART1 reset bit_offset: 18 bit_size: 1 - name: USART4RST description: USART4 reset bit_offset: 19 bit_size: 1 - name: USART5RST description: USART5 reset bit_offset: 20 bit_size: 1 - name: I2C1RST description: I2C1 reset bit_offset: 21 bit_size: 1 - name: I2C2RST description: I2C2 reset bit_offset: 22 bit_size: 1 - name: USBRST description: USB reset bit_offset: 23 bit_size: 1 - name: CRSRST description: Clock recovery system reset bit_offset: 27 bit_size: 1 - name: PWRRST description: Power interface reset bit_offset: 28 bit_size: 1 - name: DACRST description: DAC interface reset bit_offset: 29 bit_size: 1 - name: I2C3RST description: I2C3 reset bit_offset: 30 bit_size: 1 - name: LPTIM1RST description: Low power timer reset bit_offset: 31 bit_size: 1 fieldset/APB1SMENR: description: APB1 peripheral clock enable in sleep mode register fields: - name: TIM2SMEN description: Timer2 clock enable during sleep mode bit_offset: 0 bit_size: 1 - name: TIM3SMEN description: Timer 3 clock enable during sleep mode bit_offset: 1 bit_size: 1 - name: TIM6SMEN description: Timer 6 clock enable during sleep mode bit_offset: 4 bit_size: 1 - name: TIM7SMEN description: Timer 7 clock enable during sleep mode bit_offset: 5 bit_size: 1 - name: WWDGSMEN description: Window watchdog clock enable during sleep mode bit_offset: 11 bit_size: 1 - name: SPI2SMEN description: SPI2 clock enable during sleep mode bit_offset: 14 bit_size: 1 - name: USART2SMEN description: UART2 clock enable during sleep mode bit_offset: 17 bit_size: 1 - name: LPUART1SMEN description: LPUART1 clock enable during sleep mode bit_offset: 18 bit_size: 1 - name: USART4SMEN description: USART4 clock enabe during sleep mode bit_offset: 19 bit_size: 1 - name: USART5SMEN description: USART5 clock enable during sleep mode bit_offset: 20 bit_size: 1 - name: I2C1SMEN description: I2C1 clock enable during sleep mode bit_offset: 21 bit_size: 1 - name: I2C2SMEN description: I2C2 clock enable during sleep mode bit_offset: 22 bit_size: 1 - name: USBSMEN description: USB clock enable during sleep mode bit_offset: 23 bit_size: 1 - name: CRSSMEN description: Clock recovery system clock enable during sleep mode bit_offset: 27 bit_size: 1 - name: PWRSMEN description: Power interface clock enable during sleep mode bit_offset: 28 bit_size: 1 - name: DACSMEN description: DAC interface clock enable during sleep mode bit_offset: 29 bit_size: 1 - name: I2C3SMEN description: I2C3 clock enable during sleep mode bit_offset: 30 bit_size: 1 - name: LPTIM1SMEN description: Low power timer clock enable during sleep mode bit_offset: 31 bit_size: 1 fieldset/APB2ENR: description: APB2 peripheral clock enable register fields: - name: SYSCFGEN description: System configuration controller clock enable bit_offset: 0 bit_size: 1 - name: TIM21EN description: TIM21 timer clock enable bit_offset: 2 bit_size: 1 - name: TIM22EN description: TIM22 timer clock enable bit_offset: 5 bit_size: 1 - name: FWEN description: Firewall clock enable bit_offset: 7 bit_size: 1 - name: ADCEN description: ADC clock enable bit_offset: 9 bit_size: 1 - name: SPI1EN description: SPI1 clock enable bit_offset: 12 bit_size: 1 - name: USART1EN description: USART1 clock enable bit_offset: 14 bit_size: 1 - name: DBGEN description: DBG clock enable bit_offset: 22 bit_size: 1 fieldset/APB2RSTR: description: APB2 peripheral reset register fields: - name: SYSCFGRST description: System configuration controller reset bit_offset: 0 bit_size: 1 - name: TIM21RST description: TIM21 timer reset bit_offset: 2 bit_size: 1 - name: TIM22RST description: TIM22 timer reset bit_offset: 5 bit_size: 1 - name: ADCRST description: ADC interface reset bit_offset: 9 bit_size: 1 - name: SPI1RST description: SPI 1 reset bit_offset: 12 bit_size: 1 - name: USART1RST description: USART1 reset bit_offset: 14 bit_size: 1 - name: DBGRST description: DBG reset bit_offset: 22 bit_size: 1 fieldset/APB2SMENR: description: APB2 peripheral clock enable in sleep mode register fields: - name: SYSCFGSMEN description: System configuration controller clock enable during sleep mode bit_offset: 0 bit_size: 1 - name: TIM21SMEN description: TIM21 timer clock enable during sleep mode bit_offset: 2 bit_size: 1 - name: TIM22SMEN description: TIM22 timer clock enable during sleep mode bit_offset: 5 bit_size: 1 - name: ADCSMEN description: ADC clock enable during sleep mode bit_offset: 9 bit_size: 1 - name: SPI1SMEN description: SPI1 clock enable during sleep mode bit_offset: 12 bit_size: 1 - name: USART1SMEN description: USART1 clock enable during sleep mode bit_offset: 14 bit_size: 1 - name: DBGSMEN description: DBG clock enable during sleep mode bit_offset: 22 bit_size: 1 fieldset/CCIPR: description: Clock configuration register fields: - name: USART1SEL description: USART1 clock source selection bit_offset: 0 bit_size: 2 enum: USART1SEL - name: USART2SEL description: USART2 clock source selection bit_offset: 2 bit_size: 2 enum: UARTSEL - name: LPUART1SEL description: LPUART1 clock source selection bit_offset: 10 bit_size: 2 enum: UARTSEL - name: I2C1SEL description: I2C1 clock source selection bit_offset: 12 bit_size: 2 enum: I2CSEL - name: I2C3SEL description: I2C3 clock source selection bit_offset: 16 bit_size: 2 enum: I2CSEL - name: LPTIM1SEL description: Low Power Timer clock source selection bit_offset: 18 bit_size: 2 enum: LPTIMSEL fieldset/CFGR: description: Clock configuration register fields: - name: SW description: System clock switch bit_offset: 0 bit_size: 2 enum: SW - name: SWS description: System clock switch status bit_offset: 2 bit_size: 2 enum: SW - name: HPRE description: AHB prescaler bit_offset: 4 bit_size: 4 enum: HPRE - name: PPRE1 description: APB low-speed prescaler (APB1) bit_offset: 8 bit_size: 3 enum: PPRE - name: PPRE2 description: APB high-speed prescaler (APB2) bit_offset: 11 bit_size: 3 enum: PPRE - name: STOPWUCK description: Wake-up from stop clock selection bit_offset: 15 bit_size: 1 enum: STOPWUCK - name: PLLSRC description: PLL entry clock source bit_offset: 16 bit_size: 1 enum: PLLSRC - name: PLLMUL description: PLL multiplication factor bit_offset: 18 bit_size: 4 enum: PLLMUL - name: PLLDIV description: PLL output division bit_offset: 22 bit_size: 2 enum: PLLDIV - name: MCOSEL description: Microcontroller clock output selection bit_offset: 24 bit_size: 4 enum: MCOSEL - name: MCOPRE description: Microcontroller clock output prescaler bit_offset: 28 bit_size: 3 enum: MCOPRE fieldset/CICR: description: Clock interrupt clear register fields: - name: LSIRDYC description: LSI ready Interrupt clear bit_offset: 0 bit_size: 1 - name: LSERDYC description: LSE ready Interrupt clear bit_offset: 1 bit_size: 1 - name: HSIRDYC description: HSI ready Interrupt clear bit_offset: 2 bit_size: 1 - name: HSERDYC description: HSE ready Interrupt clear bit_offset: 3 bit_size: 1 - name: PLLRDYC description: PLL ready Interrupt clear bit_offset: 4 bit_size: 1 - name: MSIRDYC description: MSI ready Interrupt clear bit_offset: 5 bit_size: 1 - name: CSSLSEC description: LSE Clock Security System Interrupt clear bit_offset: 7 bit_size: 1 - name: CSSHSEC description: Clock Security System Interrupt clear bit_offset: 8 bit_size: 1 fieldset/CIER: description: Clock interrupt enable register fields: - name: LSIRDYIE description: LSI ready interrupt flag bit_offset: 0 bit_size: 1 - name: LSERDYIE description: LSE ready interrupt flag bit_offset: 1 bit_size: 1 - name: HSIRDYIE description: HSI ready interrupt flag bit_offset: 2 bit_size: 1 - name: HSERDYIE description: HSE ready interrupt flag bit_offset: 3 bit_size: 1 - name: PLLRDYIE description: PLL ready interrupt flag bit_offset: 4 bit_size: 1 - name: MSIRDYIE description: MSI ready interrupt flag bit_offset: 5 bit_size: 1 - name: CSSLSE description: LSE CSS interrupt flag bit_offset: 7 bit_size: 1 fieldset/CIFR: description: Clock interrupt flag register fields: - name: LSIRDYF description: LSI ready interrupt flag bit_offset: 0 bit_size: 1 - name: LSERDYF description: LSE ready interrupt flag bit_offset: 1 bit_size: 1 - name: HSIRDYF description: HSI ready interrupt flag bit_offset: 2 bit_size: 1 - name: HSERDYF description: HSE ready interrupt flag bit_offset: 3 bit_size: 1 - name: PLLRDYF description: PLL ready interrupt flag bit_offset: 4 bit_size: 1 - name: MSIRDYF description: MSI ready interrupt flag bit_offset: 5 bit_size: 1 - name: CSSLSEF description: LSE Clock Security System Interrupt flag bit_offset: 7 bit_size: 1 - name: CSSHSEF description: Clock Security System Interrupt flag bit_offset: 8 bit_size: 1 fieldset/CR: description: Clock control register fields: - name: HSION description: 16 MHz high-speed internal clock enable bit_offset: 0 bit_size: 1 - name: HSIKERON description: High-speed internal clock enable bit for some IP kernels bit_offset: 1 bit_size: 1 - name: HSIRDY description: Internal high-speed clock ready flag bit_offset: 2 bit_size: 1 - name: HSIDIVEN description: HSIDIVEN bit_offset: 3 bit_size: 1 - name: HSIDIVF description: HSIDIVF bit_offset: 4 bit_size: 1 - name: HSIOUTEN description: 16 MHz high-speed internal clock output enable bit_offset: 5 bit_size: 1 - name: MSION description: MSI clock enable bit_offset: 8 bit_size: 1 - name: MSIRDY description: MSI clock ready flag bit_offset: 9 bit_size: 1 - name: HSEON description: HSE clock enable bit_offset: 16 bit_size: 1 - name: HSERDY description: HSE clock ready flag bit_offset: 17 bit_size: 1 - name: HSEBYP description: HSE clock bypass bit_offset: 18 bit_size: 1 - name: CSSHSEON description: Clock security system on HSE enable bit_offset: 19 bit_size: 1 - name: RTCPRE description: TC/LCD prescaler bit_offset: 20 bit_size: 2 enum: RTCPRE - name: PLLON description: PLL enable bit_offset: 24 bit_size: 1 - name: PLLRDY description: PLL clock ready flag bit_offset: 25 bit_size: 1 fieldset/CSR: description: Control and status register fields: - name: LSION description: Internal low-speed oscillator enable bit_offset: 0 bit_size: 1 - name: LSIRDY description: Internal low-speed oscillator ready bit_offset: 1 bit_size: 1 - name: LSEON description: External low-speed oscillator enable bit_offset: 8 bit_size: 1 - name: LSERDY description: External low-speed oscillator ready bit_offset: 9 bit_size: 1 - name: LSEBYP description: External low-speed oscillator bypass bit_offset: 10 bit_size: 1 - name: LSEDRV description: LSEDRV bit_offset: 11 bit_size: 2 enum: LSEDRV - name: CSSLSEON description: CSSLSEON bit_offset: 13 bit_size: 1 - name: CSSLSED description: CSS on LSE failure detection flag bit_offset: 14 bit_size: 1 - name: RTCSEL description: RTC and LCD clock source selection bit_offset: 16 bit_size: 2 enum: RTCSEL - name: RTCEN description: RTC clock enable bit_offset: 18 bit_size: 1 - name: RTCRST description: RTC software reset bit_offset: 19 bit_size: 1 - name: RMVF description: Remove reset flag bit_offset: 23 bit_size: 1 - name: FWRSTF description: Firewall reset flag bit_offset: 24 bit_size: 1 - name: OBLRSTF description: OBLRSTF bit_offset: 25 bit_size: 1 - name: PINRSTF description: PIN reset flag bit_offset: 26 bit_size: 1 - name: PORRSTF description: POR/PDR reset flag bit_offset: 27 bit_size: 1 - name: SFTRSTF description: Software reset flag bit_offset: 28 bit_size: 1 - name: IWDGRSTF description: Independent watchdog reset flag bit_offset: 29 bit_size: 1 - name: WWDGRSTF description: Window watchdog reset flag bit_offset: 30 bit_size: 1 - name: LPWRRSTF description: Low-power reset flag bit_offset: 31 bit_size: 1 fieldset/GPIOENR: description: GPIO clock enable register fields: - name: GPIOAEN description: IO port A clock enable bit_offset: 0 bit_size: 1 - name: GPIOBEN description: IO port B clock enable bit_offset: 1 bit_size: 1 - name: GPIOCEN description: IO port A clock enable bit_offset: 2 bit_size: 1 - name: GPIODEN description: I/O port D clock enable bit_offset: 3 bit_size: 1 - name: GPIOEEN description: IO port E clock enable bit_offset: 4 bit_size: 1 - name: GPIOHEN description: I/O port H clock enable bit_offset: 7 bit_size: 1 fieldset/GPIORSTR: description: GPIO reset register fields: - name: GPIOARST description: I/O port A reset bit_offset: 0 bit_size: 1 - name: GPIOBRST description: I/O port B reset bit_offset: 1 bit_size: 1 - name: GPIOCRST description: I/O port A reset bit_offset: 2 bit_size: 1 - name: GPIODRST description: I/O port D reset bit_offset: 3 bit_size: 1 - name: GPIOERST description: I/O port E reset bit_offset: 4 bit_size: 1 - name: GPIOHRST description: I/O port H reset bit_offset: 7 bit_size: 1 fieldset/GPIOSMEN: description: GPIO clock enable in sleep mode register fields: - name: GPIOASMEN description: Port A clock enable during Sleep mode bit_offset: 0 bit_size: 1 - name: GPIOBSMEN description: Port B clock enable during Sleep mode bit_offset: 1 bit_size: 1 - name: GPIOCSMEN description: Port C clock enable during Sleep mode bit_offset: 2 bit_size: 1 - name: GPIODSMEN description: Port D clock enable during Sleep mode bit_offset: 3 bit_size: 1 - name: GPIOESMEN description: Port E clock enable during Sleep mode bit_offset: 4 bit_size: 1 - name: GPIOHSMEN description: Port H clock enable during Sleep mode bit_offset: 7 bit_size: 1 fieldset/ICSCR: description: Internal clock sources calibration register fields: - name: HSICAL description: nternal high speed clock calibration bit_offset: 0 bit_size: 8 - name: HSITRIM description: High speed internal clock trimming bit_offset: 8 bit_size: 5 - name: MSIRANGE description: MSI clock ranges bit_offset: 13 bit_size: 3 enum: MSIRANGE - name: MSICAL description: MSI clock calibration bit_offset: 16 bit_size: 8 - name: MSITRIM description: MSI clock trimming bit_offset: 24 bit_size: 8 enum/HPRE: bit_size: 4 variants: - name: Div1 description: system clock not divided value: 0 - name: Div2 description: system clock divided by 2 value: 8 - name: Div4 description: system clock divided by 4 value: 9 - name: Div8 description: system clock divided by 8 value: 10 - name: Div16 description: system clock divided by 16 value: 11 - name: Div64 description: system clock divided by 64 value: 12 - name: Div128 description: system clock divided by 128 value: 13 - name: Div256 description: system clock divided by 256 value: 14 - name: Div512 description: system clock divided by 512 value: 15 enum/I2CSEL: bit_size: 2 variants: - name: PCLK1 description: APB clock selected as peripheral clock value: 0 - name: SYS description: System clock selected as peripheral clock value: 1 - name: HSI description: HSI clock selected as peripheral clock value: 2 enum/LPTIMSEL: bit_size: 2 variants: - name: PCLK1 description: APB clock selected as Timer clock value: 0 - name: LSI description: LSI clock selected as Timer clock value: 1 - name: HSI description: HSI clock selected as Timer clock value: 2 - name: LSE description: LSE clock selected as Timer clock value: 3 enum/LSEDRV: bit_size: 2 variants: - name: Low description: Low driving capability value: 0 - name: MediumLow description: Medium low driving capability value: 1 - name: MediumHigh description: Medium high driving capability value: 2 - name: High description: High driving capability value: 3 enum/MCOPRE: bit_size: 3 variants: - name: Div1 description: No division value: 0 - name: Div2 description: Division by 2 value: 1 - name: Div4 description: Division by 4 value: 2 - name: Div8 description: Division by 8 value: 3 - name: Div16 description: Division by 16 value: 4 enum/MCOSEL: bit_size: 4 variants: - name: DISABLE description: No clock value: 0 - name: SYS description: SYSCLK clock selected value: 1 - name: HSI description: HSI oscillator clock selected value: 2 - name: MSI description: MSI oscillator clock selected value: 3 - name: HSE description: HSE oscillator clock selected value: 4 - name: PLL description: PLL clock selected value: 5 - name: LSI description: LSI oscillator clock selected value: 6 - name: LSE description: LSE oscillator clock selected value: 7 enum/MSIRANGE: bit_size: 3 variants: - name: Range66K description: range 0 around 65.536 kHz value: 0 - name: Range131K description: range 1 around 131.072 kHz value: 1 - name: Range262K description: range 2 around 262.144 kHz value: 2 - name: Range524K description: range 3 around 524.288 kHz value: 3 - name: Range1M description: range 4 around 1.048 MHz value: 4 - name: Range2M description: range 5 around 2.097 MHz (reset value) value: 5 - name: Range4M description: range 6 around 4.194 MHz value: 6 enum/PLLDIV: bit_size: 2 variants: - name: Div2 description: PLLVCO / 2 value: 1 - name: Div3 description: PLLVCO / 3 value: 2 - name: Div4 description: PLLVCO / 4 value: 3 enum/PLLMUL: bit_size: 4 variants: - name: Mul3 description: PLL clock entry x 3 value: 0 - name: Mul4 description: PLL clock entry x 4 value: 1 - name: Mul6 description: PLL clock entry x 6 value: 2 - name: Mul8 description: PLL clock entry x 8 value: 3 - name: Mul12 description: PLL clock entry x 12 value: 4 - name: Mul16 description: PLL clock entry x 16 value: 5 - name: Mul24 description: PLL clock entry x 24 value: 6 - name: Mul32 description: PLL clock entry x 32 value: 7 - name: Mul48 description: PLL clock entry x 48 value: 8 enum/PLLSRC: bit_size: 1 variants: - name: HSI description: HSI selected as PLL input clock value: 0 - name: HSE description: HSE selected as PLL input clock value: 1 enum/PPRE: bit_size: 3 variants: - name: Div1 description: HCLK not divided value: 0 - name: Div2 description: HCLK divided by 2 value: 4 - name: Div4 description: HCLK divided by 4 value: 5 - name: Div8 description: HCLK divided by 8 value: 6 - name: Div16 description: HCLK divided by 16 value: 7 enum/RTCPRE: bit_size: 2 variants: - name: Div2 description: HSE divided by 2 value: 0 - name: Div4 description: HSE divided by 4 value: 1 - name: Div8 description: HSE divided by 8 value: 2 - name: Div16 description: HSE divided by 16 value: 3 enum/RTCSEL: bit_size: 2 variants: - name: DISABLE description: No clock value: 0 - name: LSE description: LSE oscillator clock used as RTC clock value: 1 - name: LSI description: LSI oscillator clock used as RTC clock value: 2 - name: HSE description: HSE oscillator clock divided by a programmable prescaler (selection through the RTCPRE[1:0] bits in the RCC clock control register (RCC_CR)) used as the RTC clock value: 3 enum/STOPWUCK: bit_size: 1 variants: - name: MSI description: Internal 64 KHz to 4 MHz (MSI) oscillator selected as wake-up from Stop clock value: 0 - name: HSI description: Internal 16 MHz (HSI) oscillator selected as wake-up from Stop clock (or HSI/4 if HSIDIVEN=1) value: 1 enum/SW: bit_size: 2 variants: - name: MSI description: MSI oscillator used as system clock value: 0 - name: HSI description: HSI oscillator used as system clock value: 1 - name: HSE description: HSE oscillator used as system clock value: 2 - name: PLL1_R description: PLL used as system clock value: 3 enum/UARTSEL: bit_size: 2 variants: - name: PCLK1 description: APB clock selected as peripheral clock value: 0 - name: SYS description: System clock selected as peripheral clock value: 1 - name: HSI description: HSI clock selected as peripheral clock value: 2 - name: LSE description: LSE clock selected as peripheral clock value: 3 enum/USART1SEL: bit_size: 2 variants: - name: PCLK2 description: APB clock selected as peripheral clock value: 0 - name: SYS description: System clock selected as peripheral clock value: 1 - name: HSI description: HSI clock selected as peripheral clock value: 2 - name: LSE description: LSE clock selected as peripheral clock value: 3