block/RCC: description: RCC address block description. items: - name: CR description: Clock control register. byte_offset: 0 fieldset: CR - name: ICSCR description: Internal clock sources calibration register. byte_offset: 4 fieldset: ICSCR - name: CFGR description: Clock configuration register. byte_offset: 8 fieldset: CFGR - name: PLLCFGR description: PLL configuration register. byte_offset: 12 fieldset: PLLCFGR - name: CIER description: Clock interrupt enable register. byte_offset: 24 fieldset: CIER - name: CIFR description: Clock interrupt flag register. byte_offset: 28 fieldset: CIFR - name: CICR description: Clock interrupt clear register. byte_offset: 32 fieldset: CICR - name: AHBRSTR description: AHB peripheral reset register. byte_offset: 40 fieldset: AHBRSTR - name: GPIORSTR description: I/O port reset register. byte_offset: 44 fieldset: GPIORSTR - name: APBRSTR1 description: APB peripheral reset register 1. byte_offset: 56 fieldset: APBRSTR1 - name: APBRSTR2 description: APB peripheral reset register 2. byte_offset: 64 fieldset: APBRSTR2 - name: AHBENR description: AHB peripheral clock enable register. byte_offset: 72 fieldset: AHBENR - name: GPIOENR description: I/O port clock enable register. byte_offset: 76 fieldset: GPIOENR - name: DBGCFGR description: Debug configuration register. byte_offset: 80 fieldset: DBGCFGR - name: APBENR1 description: APB peripheral clock enable register 1. byte_offset: 88 fieldset: APBENR1 - name: APBENR2 description: APB peripheral clock enable register 2. byte_offset: 96 fieldset: APBENR2 - name: AHBSMENR description: AHB peripheral clock enable in Sleep/Stop mode register. byte_offset: 104 fieldset: AHBSMENR - name: GPIOSMENR description: I/O port in Sleep mode clock enable register. byte_offset: 108 fieldset: GPIOSMENR - name: APBSMENR1 description: APB peripheral clock enable in Sleep/Stop mode register 1. byte_offset: 120 fieldset: APBSMENR1 - name: APBSMENR2 description: APB peripheral clock enable in Sleep/Stop mode register 2. byte_offset: 128 fieldset: APBSMENR2 - name: CCIPR description: Peripherals independent clock configuration register. byte_offset: 136 fieldset: CCIPR - name: BDCR description: RTC domain control register. byte_offset: 144 fieldset: BDCR - name: CSR description: Control/status register. byte_offset: 148 fieldset: CSR - name: CRRCR description: RCC clock recovery RC register. byte_offset: 152 fieldset: CRRCR fieldset/AHBENR: description: AHB peripheral clock enable register. fields: - name: DMA1EN description: DMA1 and DMAMUX clock enable Set and cleared by software. DMAMUX is enabled as long as at least one DMA peripheral is enabled. bit_offset: 0 bit_size: 1 - name: DMA2EN description: DMA2 and DMAMUX clock enable Set and cleared by software. DMAMUX is enabled as long as at least one DMA peripheral is enabled. bit_offset: 1 bit_size: 1 - name: FLASHEN description: Flash memory interface clock enable Set and cleared by software. This bit can only be cleared when the flash memory is in power down mode. bit_offset: 8 bit_size: 1 - name: CRCEN description: CRC clock enable Set and cleared by software. bit_offset: 12 bit_size: 1 - name: AESEN description: AES hardware accelerator Set and cleared by software. bit_offset: 16 bit_size: 1 - name: RNGEN description: Random number generator clock enable Set and cleared by software. bit_offset: 18 bit_size: 1 - name: TSCEN description: Touch sensing controller clock enable Set and cleared by software. bit_offset: 24 bit_size: 1 fieldset/AHBRSTR: description: AHB peripheral reset register. fields: - name: DMA1RST description: DMA1 and DMAMUX reset Set and cleared by software. bit_offset: 0 bit_size: 1 - name: DMA2RST description: DMA2 and DMAMUX reset Set and cleared by software. bit_offset: 1 bit_size: 1 - name: FLASHRST description: Flash memory interface reset Set and cleared by software. This bit can only be set when the flash memory is in power down mode. bit_offset: 8 bit_size: 1 - name: CRCRST description: CRC reset Set and cleared by software. bit_offset: 12 bit_size: 1 - name: AESRST description: AES hardware accelerator reset Set and cleared by software. bit_offset: 16 bit_size: 1 - name: RNGRST description: Random number generator reset Set and cleared by software. bit_offset: 18 bit_size: 1 - name: TSCRST description: Touch sensing controller reset Set and cleared by software. bit_offset: 24 bit_size: 1 fieldset/AHBSMENR: description: AHB peripheral clock enable in Sleep/Stop mode register. fields: - name: DMA1SMEN description: DMA1 and DMAMUX clock enable during Sleep mode Set and cleared by software. Clock to DMAMUX during Sleep mode is enabled as long as the clock in Sleep mode is enabled to at least one DMA peripheral. bit_offset: 0 bit_size: 1 - name: DMA2SMEN description: DMA2 and DMAMUX clock enable during Sleep mode Set and cleared by software. Clock to DMAMUX during Sleep mode is enabled as long as the clock in Sleep mode is enabled to at least one DMA peripheral. bit_offset: 1 bit_size: 1 - name: FLASHSMEN description: Flash memory interface clock enable during Sleep mode Set and cleared by software. This bit can be activated only when the flash memory is in power down mode. bit_offset: 8 bit_size: 1 - name: SRAMSMEN description: SRAM clock enable during Sleep mode Set and cleared by software. bit_offset: 9 bit_size: 1 - name: CRCSMEN description: CRC clock enable during Sleep mode Set and cleared by software. bit_offset: 12 bit_size: 1 - name: AESSMEN description: AES hardware accelerator clock enable during Sleep mode Set and cleared by software. bit_offset: 16 bit_size: 1 - name: RNGSMEN description: RNG clock enable during Sleep and Stop mode Set and cleared by software. bit_offset: 18 bit_size: 1 - name: TSCSMEN description: TSC clock enable during Sleep and Stop mode Set and cleared by software. bit_offset: 24 bit_size: 1 fieldset/APBENR1: description: APB peripheral clock enable register 1. fields: - name: TIM2EN description: TIM2 timer clock enable Set and cleared by software. bit_offset: 0 bit_size: 1 - name: TIM3EN description: TIM3 timer clock enable Set and cleared by software. bit_offset: 1 bit_size: 1 - name: TIM6EN description: TIM6 timer clock enable Set and cleared by software. bit_offset: 4 bit_size: 1 - name: TIM7EN description: TIM7 timer clock enable Set and cleared by software. bit_offset: 5 bit_size: 1 - name: LPUART2EN description: LPUART2 clock enable Set and cleared by software. bit_offset: 7 bit_size: 1 - name: LCDEN description: LCD clock enable(1) Set and cleared by software. bit_offset: 9 bit_size: 1 - name: RTCAPBEN description: RTC APB clock enable Set and cleared by software. bit_offset: 10 bit_size: 1 - name: WWDGEN description: WWDG clock enable Set by software to enable the window watchdog clock. Cleared by hardware system reset This bit can also be set by hardware if the WWDG_SW option bit is 0. bit_offset: 11 bit_size: 1 - name: LPUART3EN description: LPUART3 clock enable Set and cleared by software. bit_offset: 12 bit_size: 1 - name: USBEN description: USB clock enable(1) Set and cleared by software. bit_offset: 13 bit_size: 1 - name: SPI2EN description: SPI2 clock enable Set and cleared by software. bit_offset: 14 bit_size: 1 - name: SPI3EN description: SPI3 clock enable(1) Set and cleared by software. bit_offset: 15 bit_size: 1 - name: CRSEN description: CRS clock enable(1) Set and cleared by software. bit_offset: 16 bit_size: 1 - name: USART2EN description: USART2 clock enable Set and cleared by software. bit_offset: 17 bit_size: 1 - name: USART3EN description: USART3 clock enable Set and cleared by software. bit_offset: 18 bit_size: 1 - name: USART4EN description: USART4 clock enable Set and cleared by software. bit_offset: 19 bit_size: 1 - name: LPUART1EN description: LPUART1 clock enable Set and cleared by software. bit_offset: 20 bit_size: 1 - name: I2C1EN description: I2C1 clock enable Set and cleared by software. bit_offset: 21 bit_size: 1 - name: I2C2EN description: I2C2 clock enable Set and cleared by software. bit_offset: 22 bit_size: 1 - name: I2C3EN description: I2C3 clock enable Set and cleared by software. bit_offset: 23 bit_size: 1 - name: OPAMPEN description: OPAMP clock enable Set and cleared by software. bit_offset: 24 bit_size: 1 - name: I2C4EN description: I2C4EN clock enable(1) Set and cleared by software. bit_offset: 25 bit_size: 1 - name: LPTIM3EN description: LPTIM3 clock enable Set and cleared by software. bit_offset: 26 bit_size: 1 - name: PWREN description: Power interface clock enable Set and cleared by software. bit_offset: 28 bit_size: 1 - name: DAC1EN description: DAC1 interface clock enable Set and cleared by software. bit_offset: 29 bit_size: 1 - name: LPTIM2EN description: LPTIM2 clock enable Set and cleared by software. bit_offset: 30 bit_size: 1 - name: LPTIM1EN description: LPTIM1 clock enable Set and cleared by software. bit_offset: 31 bit_size: 1 fieldset/APBENR2: description: APB peripheral clock enable register 2. fields: - name: SYSCFGEN description: SYSCFG, COMP and VREFBUF clock enable Set and cleared by software. bit_offset: 0 bit_size: 1 - name: TIM1EN description: TIM1 timer clock enable Set and cleared by software. bit_offset: 11 bit_size: 1 - name: SPI1EN description: SPI1 clock enable Set and cleared by software. bit_offset: 12 bit_size: 1 - name: USART1EN description: USART1 clock enable Set and cleared by software. bit_offset: 14 bit_size: 1 - name: TIM15EN description: TIM15 timer clock enable Set and cleared by software. bit_offset: 16 bit_size: 1 - name: TIM16EN description: TIM16 timer clock enable Set and cleared by software. bit_offset: 17 bit_size: 1 - name: ADCEN description: ADC clock enable Set and cleared by software. bit_offset: 20 bit_size: 1 fieldset/APBRSTR1: description: APB peripheral reset register 1. fields: - name: TIM2RST description: TIM2 timer reset Set and cleared by software. bit_offset: 0 bit_size: 1 - name: TIM3RST description: TIM3 timer reset Set and cleared by software. bit_offset: 1 bit_size: 1 - name: TIM6RST description: TIM6 timer reset Set and cleared by software. bit_offset: 4 bit_size: 1 - name: TIM7RST description: TIM7 timer reset Set and cleared by software. bit_offset: 5 bit_size: 1 - name: LPUART2RST description: LPUART2 reset Set and cleared by software. bit_offset: 7 bit_size: 1 - name: LCDRST description: LCD reset(1) Set and cleared by software. bit_offset: 9 bit_size: 1 - name: LPUART3RST description: LPUART3 reset(1) Set and cleared by software. bit_offset: 12 bit_size: 1 - name: USBRST description: USB reset(1) Set and cleared by software. bit_offset: 13 bit_size: 1 - name: SPI2RST description: SPI2 reset Set and cleared by software. bit_offset: 14 bit_size: 1 - name: SPI3RST description: SPI3 reset(1) Set and cleared by software. bit_offset: 15 bit_size: 1 - name: CRSRST description: CRS reset(1) Set and cleared by software. bit_offset: 16 bit_size: 1 - name: USART2RST description: USART2 reset Set and cleared by software. bit_offset: 17 bit_size: 1 - name: USART3RST description: USART3 reset Set and cleared by software. bit_offset: 18 bit_size: 1 - name: USART4RST description: USART4 reset Set and cleared by software. bit_offset: 19 bit_size: 1 - name: LPUART1RST description: LPUART1 reset Set and cleared by software. bit_offset: 20 bit_size: 1 - name: I2C1RST description: I2C1 reset Set and cleared by software. bit_offset: 21 bit_size: 1 - name: I2C2RST description: I2C2 reset Set and cleared by software. bit_offset: 22 bit_size: 1 - name: I2C3RST description: I2C3 reset Set and cleared by software. bit_offset: 23 bit_size: 1 - name: OPAMPRST description: OPAMP reset Set and cleared by software. bit_offset: 24 bit_size: 1 - name: I2C4RST description: I2C4 reset(1) Set and cleared by software. bit_offset: 25 bit_size: 1 - name: LPTIM3RST description: LPTIM3 reset Set and cleared by software. bit_offset: 26 bit_size: 1 - name: PWRRST description: Power interface reset Set and cleared by software. bit_offset: 28 bit_size: 1 - name: DAC1RST description: DAC1 interface reset Set and cleared by software. bit_offset: 29 bit_size: 1 - name: LPTIM2RST description: Low Power Timer 2 reset Set and cleared by software. bit_offset: 30 bit_size: 1 - name: LPTIM1RST description: Low Power Timer 1 reset Set and cleared by software. bit_offset: 31 bit_size: 1 fieldset/APBRSTR2: description: APB peripheral reset register 2. fields: - name: SYSCFGRST description: SYSCFG, COMP and VREFBUF reset Set and cleared by software. bit_offset: 0 bit_size: 1 - name: TIM1RST description: TIM1 timer reset Set and cleared by software. bit_offset: 11 bit_size: 1 - name: SPI1RST description: SPI1 reset Set and cleared by software. bit_offset: 12 bit_size: 1 - name: USART1RST description: USART1 reset Set and cleared by software. bit_offset: 14 bit_size: 1 - name: TIM15RST description: TIM15 timer reset Set and cleared by software. bit_offset: 16 bit_size: 1 - name: TIM16RST description: TIM16 timer reset Set and cleared by software. bit_offset: 17 bit_size: 1 - name: ADCRST description: ADC reset Set and cleared by software. bit_offset: 20 bit_size: 1 fieldset/APBSMENR1: description: APB peripheral clock enable in Sleep/Stop mode register 1. fields: - name: TIM2SMEN description: TIM2 timer clock enable during Sleep mode Set and cleared by software. bit_offset: 0 bit_size: 1 - name: TIM3SMEN description: TIM3 timer clock enable during Sleep mode Set and cleared by software. bit_offset: 1 bit_size: 1 - name: TIM6SMEN description: TIM6 timer clock enable during Sleep mode Set and cleared by software. bit_offset: 4 bit_size: 1 - name: TIM7SMEN description: TIM7 timer clock enable during Sleep mode Set and cleared by software. bit_offset: 5 bit_size: 1 - name: LPUART2SMEN description: LPUART2 clock enable during Sleep and Stop modes Set and cleared by software. bit_offset: 7 bit_size: 1 - name: LCDSMEN description: LCD clock enable during Sleep mode(1) Set and cleared by software. bit_offset: 9 bit_size: 1 - name: RTCAPBSMEN description: RTC APB clock enable during Sleep mode Set and cleared by software. bit_offset: 10 bit_size: 1 - name: WWDGSMEN description: WWDG clock enable during Sleep and Stop modes Set and cleared by software. bit_offset: 11 bit_size: 1 - name: LPUART3SMEN description: LPUART3 clock enable during Sleep and Stop modes Set and cleared by software. bit_offset: 12 bit_size: 1 - name: USBSMEN description: USB clock enable during Sleep mode(1) Set and cleared by software. bit_offset: 13 bit_size: 1 - name: SPI2SMEN description: SPI2 clock enable during Sleep mode Set and cleared by software. bit_offset: 14 bit_size: 1 - name: SPI3SMEN description: SPI3 clock enable during Sleep mode(1) Set and cleared by software. bit_offset: 15 bit_size: 1 - name: CRSSMEN description: CRS clock enable during Sleep and Stop modes(1) Set and cleared by software. bit_offset: 16 bit_size: 1 - name: USART2SMEN description: USART2 clock enable during Sleep and Stop modes Set and cleared by software. bit_offset: 17 bit_size: 1 - name: USART3SMEN description: USART3 clock enable during Sleep mode Set and cleared by software. bit_offset: 18 bit_size: 1 - name: USART4SMEN description: USART4 clock enable during Sleep mode Set and cleared by software. bit_offset: 19 bit_size: 1 - name: LPUART1SMEN description: LPUART1 clock enable during Sleep and Stop modes Set and cleared by software. bit_offset: 20 bit_size: 1 - name: I2C1SMEN description: I2C1 clock enable during Sleep and Stop modes Set and cleared by software. bit_offset: 21 bit_size: 1 - name: I2C2SMEN description: I2C2 clock enable during Sleep mode Set and cleared by software. bit_offset: 22 bit_size: 1 - name: I2C3SMEN description: I2C3 clock enable during Sleep mode Set and cleared by software. bit_offset: 23 bit_size: 1 - name: OPAMPSMEN description: OPAMP clock enable during Sleep and Stop modes Set and cleared by software. bit_offset: 24 bit_size: 1 - name: I2C4SMEN description: I2C4 clock enable during Sleep mode(1) Set and cleared by software. bit_offset: 25 bit_size: 1 - name: LPTIM3SMEN description: Low power timer 3 clock enable during Sleep mode Set and cleared by software. bit_offset: 26 bit_size: 1 - name: PWRSMEN description: Power interface clock enable during Sleep mode Set and cleared by software. bit_offset: 28 bit_size: 1 - name: DAC1SMEN description: DAC1 interface clock enable during Sleep and Stop modes Set and cleared by software. bit_offset: 29 bit_size: 1 - name: LPTIM2SMEN description: Low Power Timer 2 clock enable during Sleep and Stop modes Set and cleared by software. bit_offset: 30 bit_size: 1 - name: LPTIM1SMEN description: Low Power Timer 1 clock enable during Sleep and Stop modes Set and cleared by software. bit_offset: 31 bit_size: 1 fieldset/APBSMENR2: description: APB peripheral clock enable in Sleep/Stop mode register 2. fields: - name: SYSCFGSMEN description: SYSCFG, COMP and VREFBUF clock enable during Sleep and Stop modes Set and cleared by software. bit_offset: 0 bit_size: 1 - name: TIM1SMEN description: TIM1 timer clock enable during Sleep mode Set and cleared by software. bit_offset: 11 bit_size: 1 - name: SPI1SMEN description: SPI1 clock enable during Sleep mode Set and cleared by software. bit_offset: 12 bit_size: 1 - name: USART1SMEN description: USART1 clock enable during Sleep and Stop modes Set and cleared by software. bit_offset: 14 bit_size: 1 - name: TIM15SMEN description: TIM15 timer clock enable during Sleep mode Set and cleared by software. bit_offset: 16 bit_size: 1 - name: TIM16SMEN description: TIM16 timer clock enable during Sleep mode Set and cleared by software. bit_offset: 17 bit_size: 1 - name: ADCSMEN description: ADC clock enable during Sleep mode Set and cleared by software. bit_offset: 20 bit_size: 1 fieldset/BDCR: description: RTC domain control register. fields: - name: LSEON description: LSE oscillator enable Set and cleared by software to enable LSE oscillator:. bit_offset: 0 bit_size: 1 - name: LSERDY description: 'LSE oscillator ready Set and cleared by hardware to indicate when the external 321kHz oscillator is ready (stable): After the LSEON bit is cleared, LSERDY goes low after 6 external low-speed oscillator clock cycles.' bit_offset: 1 bit_size: 1 - name: LSEBYP description: LSE oscillator bypass Set and cleared by software to bypass the LSE oscillator (in debug mode). This bit can be written only when the external 321kHz oscillator is disabled (LSEON=0 and LSERDY=0). bit_offset: 2 bit_size: 1 - name: LSEDRV description: 'LSE oscillator drive capability Set by software to select the LSE oscillator drive capability as follows: Applicable when the LSE oscillator is in Xtal mode, as opposed to bypass mode.' bit_offset: 3 bit_size: 2 enum: LSEDRV - name: LSECSSON description: 'CSS on LSE enable Set by software to enable the clock security system on LSE (321kHz) oscillator as follows: LSECSSON must be enabled after the LSE oscillator is enabled (LSEON bit enabled) and ready (LSERDY flag set by hardware), and after the RTCSEL bit is selected. Once enabled, this bit cannot be disabled, except after a LSE failure detection (LSECSSD =1). In that case the software must disable the LSECSSON bit.' bit_offset: 5 bit_size: 1 - name: LSECSSD description: CSS on LSE failure Detection Set by hardware to indicate when a failure is detected by the clock security system on the external 321kHz oscillator (LSE):. bit_offset: 6 bit_size: 1 - name: LSESYSEN description: LSE clock enable for system usage This bit must be set by software to enable the LSE clock for a system usage. bit_offset: 7 bit_size: 1 - name: RTCSEL description: 'RTC clock source selection Set by software to select the clock source for the RTC as follows: Once the RTC clock source is selected, it cannot be changed anymore unless the RTC domain is reset, or unless a failure is detected on LSE (LSECSSD is set). The BDRST bit can be used to reset this bitfield to 00.' bit_offset: 8 bit_size: 2 enum: RTCSEL - name: LSESYSRDY description: LSE clock ready for system usage This flag is set by hardware to indicate that the LSE clock is ready for being used by the system (see LSESYSEN bit). This flag is set when LSE clock is ready (LSEON1=11 and LSERDY1=11) and two LSE clock cycles after that LSESYSEN is set. Cleared by hardware to indicate that the LSE clock is not ready to be used by the system. bit_offset: 11 bit_size: 1 - name: RTCEN description: RTC clock enable Set and cleared by software. The bit enables clock to RTC and TAMP. bit_offset: 15 bit_size: 1 - name: BDRST description: RTC domain software reset Set and cleared by software to reset the RTC domain:. bit_offset: 16 bit_size: 1 - name: LSCOEN description: Low-speed clock output (LSCO) enable Set and cleared by software. bit_offset: 24 bit_size: 1 - name: LSCOSEL description: Low-speed clock output selection Set and cleared by software to select the low-speed output clock:. bit_offset: 25 bit_size: 1 enum: LSCOSEL fieldset/CCIPR: description: Peripherals independent clock configuration register. fields: - name: USART1SEL description: USART1 clock source selection This bitfield is controlled by software to select USART1 clock source as follows:. bit_offset: 0 bit_size: 2 enum: USART1SEL - name: USART2SEL description: USART2 clock source selection This bitfield is controlled by software to select USART2 clock source as follows:. bit_offset: 2 bit_size: 2 enum: USART2SEL - name: LPUART3SEL description: LPUART3 clock source selection(1) This bitfield is controlled by software to select LPUART3 clock source as follows:. bit_offset: 6 bit_size: 2 enum: LPUART3SEL - name: LPUART2SEL description: LPUART2 clock source selection This bitfield is controlled by software to select LPUART2 clock source as follows:. bit_offset: 8 bit_size: 2 enum: LPUART2SEL - name: LPUART1SEL description: LPUART1 clock source selection This bitfield is controlled by software to select LPUART1 clock source as follows:. bit_offset: 10 bit_size: 2 enum: LPUART1SEL - name: I2C1SEL description: I2C1 clock source selection This bitfield is controlled by software to select I2C1 clock source as follows:. bit_offset: 12 bit_size: 2 enum: I2C1SEL - name: I2C3SEL description: I2C3 clock source selection This bitfield is controlled by software to select I2C3 clock source as follows:. bit_offset: 16 bit_size: 2 enum: I2C3SEL - name: LPTIM1SEL description: LPTIM1 clock source selection This bitfield is controlled by software to select LPTIM1 clock source as follows:. bit_offset: 18 bit_size: 2 enum: LPTIM1SEL - name: LPTIM2SEL description: LPTIM2 clock source selection This bitfield is controlled by software to select LPTIM2 clock source as follows:. bit_offset: 20 bit_size: 2 enum: LPTIM2SEL - name: LPTIM3SEL description: LPTIM3 clock source selection This bitfield is controlled by software to select LPTIM3 clock source as follows:. bit_offset: 22 bit_size: 2 enum: LPTIM3SEL - name: TIM1SEL description: TIM1 clock source selection This bit is set and cleared by software. It selects TIM1 clock source as follows:. bit_offset: 24 bit_size: 1 enum: TIM1SEL - name: TIM15SEL description: TIM15 clock source selection This bit is set and cleared by software. It selects TIM15 clock source as follows:. bit_offset: 25 bit_size: 1 enum: TIM15SEL - name: CLK48SEL description: 481MHz clock source selection This bitfield is controlled by software to select the 481MHz clock source used by the USB FS and the RNG:. bit_offset: 26 bit_size: 2 enum: CLK48SEL - name: ADCSEL description: ADCs clock source selection This bitfield is controlled by software to select the clock source for ADC:. bit_offset: 28 bit_size: 2 enum: ADCSEL fieldset/CFGR: description: Clock configuration register. fields: - name: SW description: 'System clock switch This bitfield is controlled by software and hardware. The bitfield selects the clock for SYSCLK as follows: Others: Reserved The setting is forced by hardware to 000 (HSISYS selected) when the MCU exits Stop, Standby, or Shutdown mode, or when the setting is 001 (HSE selected) and HSE oscillator failure is detected.' bit_offset: 0 bit_size: 3 enum: SW - name: SWS description: 'System clock switch status This bitfield is controlled by hardware to indicate the clock source used as system clock: Others: Reserved.' bit_offset: 3 bit_size: 3 enum: SW - name: HPRE description: 'AHB prescaler This bitfield is controlled by software. To produce HCLK clock, it sets the division factor of SYSCLK clock as follows: 0xxx: 1 Caution: Depending on the device voltage range, the software has to set correctly these bits to ensure that the system frequency does not exceed the maximum allowed frequency (for more details, refer to Section14.1.4: Dynamic voltage scaling management). After a write operation to these bits and before decreasing the voltage range, this register must be read to be sure that the new value has been taken into account.' bit_offset: 8 bit_size: 4 enum: HPRE - name: PPRE description: 'APB prescaler This bitfield is controlled by software. To produce PCLK clock, it sets the division factor of HCLK clock as follows: 0xx: 1.' bit_offset: 12 bit_size: 3 enum: PPRE - name: STOPWUCK description: 'Wake-up from Stop and CSS backup clock selection Set and cleared by software to select the system clock used when exiting Stop mode. The selected clock is also used as emergency clock for the Clock Security System on HSE. Warning: STOPWUCK must not be modified when the Clock Security System is enabled by HSECSSON in RCC_CR register and the system clock is HSE (SWS=10) or a switch on HSE is requested (SW=10).' bit_offset: 15 bit_size: 1 - name: MCO2SEL description: 'Microcontroller clock output 2 clock selector This bitfield is controlled by software. It sets the clock selector for MCO2 output as follows: Others: Reserved Note: This clock output may have some truncated cycles at startup or during MCO2 clock source switching.' bit_offset: 16 bit_size: 4 enum: MCOSEL - name: MCO2PRE description: 'Microcontroller clock output 2 prescaler This bitfield is controlled by software. It sets the division factor of the clock sent to the MCO2 output as follows: ... Others: reserved It is highly recommended to set this field before the MCO2 output is enabled.' bit_offset: 20 bit_size: 4 enum: MCOPRE - name: MCOSEL description: 'Microcontroller clock output clock selector This bitfield is controlled by software. It sets the clock selector for MCO output as follows: Others: Reserved Note: This clock output may have some truncated cycles at startup or during MCO clock source switching.' bit_offset: 24 bit_size: 4 enum: MCOSEL - name: MCOPRE description: 'Microcontroller clock output prescaler This bitfield is controlled by software. It sets the division factor of the clock sent to the MCO output as follows: ... Others: reserved It is highly recommended to set this field before the MCO output is enabled.' bit_offset: 28 bit_size: 4 enum: MCOPRE fieldset/CICR: description: Clock interrupt clear register. fields: - name: LSIRDYC description: LSI ready interrupt clear This bit is set by software to clear the LSIRDYF flag. bit_offset: 0 bit_size: 1 - name: LSERDYC description: LSE ready interrupt clear This bit is set by software to clear the LSERDYF flag. bit_offset: 1 bit_size: 1 - name: MSIRDYC description: MSI ready interrupt clear This bit is set by software to clear the MSIRDYF flag. bit_offset: 2 bit_size: 1 - name: HSIRDYC description: HSI ready interrupt clear This bit is set software to clear the HSIRDYF flag. bit_offset: 3 bit_size: 1 - name: HSERDYC description: HSE ready interrupt clear This bit is set by software to clear the HSERDYF flag. bit_offset: 4 bit_size: 1 - name: PLLRDYC description: PLL ready interrupt clear This bit is set by software to clear the PLLRDYF flag. bit_offset: 5 bit_size: 1 - name: CSSC description: Clock security system interrupt clear This bit is set by software to clear the HSECSSF flag. bit_offset: 8 bit_size: 1 - name: LSECSSC description: LSE Clock security system interrupt clear This bit is set by software to clear the LSECSSF flag. bit_offset: 9 bit_size: 1 - name: HSI48RDYC description: HSI48 oscillator ready interrupt clear This bit is set by software to clear the HSI48RDYF flag. bit_offset: 10 bit_size: 1 fieldset/CIER: description: Clock interrupt enable register. fields: - name: LSIRDYIE description: LSI ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the LSI oscillator stabilization:. bit_offset: 0 bit_size: 1 - name: LSERDYIE description: LSE ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the LSE oscillator stabilization:. bit_offset: 1 bit_size: 1 - name: MSIRDYIE description: MSI ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the MSI oscillator stabilization. bit_offset: 2 bit_size: 1 - name: HSIRDYIE description: HSI ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the HSI oscillator stabilization:. bit_offset: 3 bit_size: 1 - name: HSERDYIE description: HSE ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the HSE oscillator stabilization:. bit_offset: 4 bit_size: 1 - name: PLLRDYIE description: PLL ready interrupt enable Set and cleared by software to enable/disable interrupt caused by PLL lock:. bit_offset: 5 bit_size: 1 - name: LSECSSIE description: LSE clock security system interrupt enable Set and cleared by software to enable/disable interrupt caused by the clock security system on LSE. bit_offset: 9 bit_size: 1 - name: HSI48RDYIE description: HSI48 ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the internal HSI48 oscillator. bit_offset: 10 bit_size: 1 fieldset/CIFR: description: Clock interrupt flag register. fields: - name: LSIRDYF description: LSI ready interrupt flag Set by hardware when the LSI clock becomes stable and LSIRDYDIE is set. Cleared by software setting the LSIRDYC bit. bit_offset: 0 bit_size: 1 - name: LSERDYF description: LSE ready interrupt flag Set by hardware when the LSE clock becomes stable and LSERDYDIE is set. Cleared by software setting the LSERDYC bit. bit_offset: 1 bit_size: 1 - name: MSIRDYF description: MSI ready interrupt flag Set by hardware when the MSI clock becomes stable and MSIRDYDIE is set. Cleared by software setting the MSIRDYC bit. bit_offset: 2 bit_size: 1 - name: HSIRDYF description: HSI ready interrupt flag Set by hardware when the HSI clock becomes stable and HSIRDYIE is set in a response to setting the HSION (refer to Clock control register (RCC_CR)). When HSION is not set but the HSI oscillator is enabled by the peripheral through a clock request, this bit is not set and no interrupt is generated. Cleared by software setting the HSIRDYC bit. bit_offset: 3 bit_size: 1 - name: HSERDYF description: HSE ready interrupt flag Set by hardware when the HSE clock becomes stable and HSERDYIE is set. Cleared by software setting the HSERDYC bit. bit_offset: 4 bit_size: 1 - name: PLLRDYF description: PLL ready interrupt flag Set by hardware when the PLL locks and PLLRDYIE is set. Cleared by software setting the PLLRDYC bit. bit_offset: 5 bit_size: 1 - name: CSSF description: HSE clock security system interrupt flag Set by hardware when a failure is detected in the HSE oscillator. Cleared by software setting the CSSC bit. bit_offset: 8 bit_size: 1 - name: LSECSSF description: LSE clock security system interrupt flag Set by hardware when a failure is detected in the LSE oscillator. Cleared by software by setting the LSECSSC bit. bit_offset: 9 bit_size: 1 - name: HSI48RDYF description: HSI48 ready interrupt flag Set by hardware when the HSI48 clock becomes stable and HSI48RDYIE is set in a response to setting the HSI48ON (refer to RCC clock recovery RC register (RCC_CRRCR)). Cleared by software setting the HSI48RDYC bit. bit_offset: 10 bit_size: 1 fieldset/CR: description: Clock control register. fields: - name: MSION description: MSI clock enable This bit is set and cleared by software. Cleared by hardware to stop the MSI oscillator when entering Stop, Standby or Shutdown mode. Set by hardware to force the MSI oscillator ON when exiting Standby or Shutdown mode. Set by hardware to force the MSI oscillator ON when STOPWUCK=0 when exiting from Stop modes, or in case of a failure of the HSE oscillator Set by hardware when used directly or indirectly as system clock. bit_offset: 0 bit_size: 1 - name: MSIRDY description: 'MSI clock ready flag This bit is set by hardware to indicate that the MSI oscillator is stable. Note: Once the MSION bit is cleared, MSIRDY goes low after 6 MSI clock cycles.' bit_offset: 1 bit_size: 1 - name: MSIPLLEN description: MSI clock PLL enable Set and cleared by software to enable/ disable the PLL part of the MSI clock source. MSIPLLEN must be enabled after LSE is enabled (LSEON enabled) and ready (LSERDY set by hardware).There is a hardware protection to avoid enabling MSIPLLEN if LSE is not ready. This bit is cleared by hardware when LSE is disabled (LSEON = 0) or when the Clock Security System on LSE detects a LSE failure (refer to RCC_CSR register). bit_offset: 2 bit_size: 1 - name: MSIRGSEL description: MSI clock range selection Set by software to select the MSI clock range with MSIRANGE[3:0]. Write 0 has no effect. After a standby or a reset MSIRGSEL is at 0 and the MSI range value is provided by MSISRANGE in CSR register. bit_offset: 3 bit_size: 1 enum: MSIRGSEL - name: MSIRANGE description: 'MSI clock ranges These bits are configured by software to choose the frequency range of MSI when MSIRGSEL is set.12 frequency ranges are available: others: not allowed (hardware write protection) Note: Warning: MSIRANGE can be modified when MSI is OFF (MSION=0) or when MSI is ready (MSIRDY=1). MSIRANGE must NOT be modified when MSI is ON and NOT ready (MSION=1 and MSIRDY=0).' bit_offset: 4 bit_size: 4 enum: MSIRANGE - name: HSION description: HSI clock enable Set and cleared by software. Cleared by hardware to stop the HSI oscillator when entering Stop, Standby, or Shutdown mode. Forced by hardware to keep the HSI oscillator ON when it is used directly or indirectly as system clock (also when leaving Stop, Standby, or Shutdown modes, or in case of failure of the HSE oscillator used for system clock). bit_offset: 8 bit_size: 1 - name: HSIKERON description: HSI always enable for peripheral kernels. Set and cleared by software to force HSI ON even in Stop modes. The HSI can only feed USART1, USART2, CEC and I2C1 peripherals configured with HSI as kernel clock. Keeping the HSI ON in Stop mode allows avoiding to slow down the communication speed because of the HSI startup time. This bit has no effect on HSION value. bit_offset: 9 bit_size: 1 - name: HSIRDY description: 'HSI clock ready flag Set by hardware to indicate that HSI oscillator is stable. This bit is set only when HSI is enabled by software by setting HSION. Note: Once the HSION bit is cleared, HSIRDY goes low after 6 HSI clock cycles.' bit_offset: 10 bit_size: 1 - name: HSIASFS description: HSI automatic start from Stop Set and cleared by software. When the system wake-up clock is MSI, this bit is used to wake up the HSI is parallel of the system wake-up. bit_offset: 11 bit_size: 1 - name: HSEON description: HSE clock enable Set and cleared by software. Cleared by hardware to stop the HSE oscillator when entering Stop, Standby, or Shutdown mode. This bit cannot be reset if the HSE oscillator is used directly or indirectly as the system clock. bit_offset: 16 bit_size: 1 - name: HSERDY description: 'HSE clock ready flag Set by hardware to indicate that the HSE oscillator is stable. Note: Once the HSEON bit is cleared, HSERDY goes low after 6 HSE clock cycles.' bit_offset: 17 bit_size: 1 - name: HSEBYP description: HSE crystal oscillator bypass Set and cleared by software to bypass the oscillator with an external clock. The external clock must be enabled with the HSEON bit set, to be used by the device. The HSEBYP bit can be written only if the HSE oscillator is disabled. bit_offset: 18 bit_size: 1 - name: CSSON description: Clock security system enable Set by software to enable the clock security system. When CSSON is set, the clock detector is enabled by hardware when the HSE oscillator is ready, and disabled by hardware if a HSE clock failure is detected. This bit is set only and is cleared by reset. bit_offset: 19 bit_size: 1 - name: PLLON description: PLL enable Set and cleared by software to enable the PLL. Cleared by hardware when entering Stop, Standby or Shutdown mode. This bit cannot be reset if the PLL clock is used as the system clock. bit_offset: 24 bit_size: 1 - name: PLLRDY description: PLL clock ready flag Set by hardware to indicate that the PLL is locked. bit_offset: 25 bit_size: 1 fieldset/CRRCR: description: RCC clock recovery RC register. fields: - name: HSI48ON description: HSI48 RC oscillator enable(1). bit_offset: 0 bit_size: 1 - name: HSI48RDY description: HSI48 clock ready flag(1) The flag is set when the HSI48 clock is ready for use. bit_offset: 1 bit_size: 1 - name: HSI48CAL description: HSI48 clock calibration These bits are initialized at startup with the factory-programmed HSI48 calibration trim value. bit_offset: 7 bit_size: 9 fieldset/CSR: description: Control/status register. fields: - name: LSION description: LSI oscillator enable Set and cleared by software to enable/disable the LSI oscillator:. bit_offset: 0 bit_size: 1 - name: LSIRDY description: 'LSI oscillator ready Set and cleared by hardware to indicate when the LSI oscillator is ready (stable): After the LSION bit is cleared, LSIRDY goes low after 3 LSI oscillator clock cycles. This bit can be set even if LSION = 0 if the LSI is requested by the Clock Security System on LSE, by the Independent Watchdog or by the RTC.' bit_offset: 1 bit_size: 1 - name: LSIPREDIV description: Internal low-speed oscillator pre-divided by 128 Set and reset by hardware to indicate when the low-speed internal RC oscillator has to be divided by 128. The software has to switch off the LSI before changing this bit. bit_offset: 2 bit_size: 1 enum: LSIPREDIV - name: MSISRANGE description: 'MSI range after Standby mode Set by software to chose the MSI frequency at startup. This range is used after exiting Standby mode until MSIRGSEL is set. After a pad or a power-on reset, the range is always 41MHz. MSISRANGE[3:0] can be written only when MSIRGSEL1=11. Others: Reserved Note: Changing the MSISRANGE[3:0] does not change the current MSI frequency.' bit_offset: 8 bit_size: 4 enum: MSISRANGE - name: RMVF description: Remove reset flags Set by software to clear the reset flags. bit_offset: 23 bit_size: 1 - name: OBLRSTF description: Option byte loader reset flag Set by hardware when a reset from the Option byte loading occurs. Cleared by setting the RMVF bit. bit_offset: 25 bit_size: 1 - name: PINRSTF description: Pin reset flag Set by hardware when a reset from the NRST pin occurs. Cleared by setting the RMVF bit. bit_offset: 26 bit_size: 1 - name: PWRRSTF description: BOR or POR/PDR flag Set by hardware when a BOR or POR/PDR occurs. Cleared by setting the RMVF bit. bit_offset: 27 bit_size: 1 - name: SFTRSTF description: Software reset flag Set by hardware when a software reset occurs. Cleared by setting the RMVF bit. bit_offset: 28 bit_size: 1 - name: IWDGRSTF description: Independent window watchdog reset flag Set by hardware when an independent watchdog reset domain occurs. Cleared by setting the RMVF bit. bit_offset: 29 bit_size: 1 - name: WWDGRSTF description: Window watchdog reset flag Set by hardware when a window watchdog reset occurs. Cleared by setting the RMVF bit. bit_offset: 30 bit_size: 1 - name: LPWRRSTF description: Low-power reset flag Set by hardware when a reset occurs due to illegal Stop, Standby, or Shutdown mode entry. Cleared by setting the RMVF bit. This operates only if nRST_STOP, nRST_STDBY or nRST_SHDW option bits are cleared. bit_offset: 31 bit_size: 1 fieldset/DBGCFGR: description: Debug configuration register. fields: - name: DBGEN description: Debug support clock enable Set and cleared by software. bit_offset: 0 bit_size: 1 - name: DBGRST description: Debug support reset Set and cleared by software. bit_offset: 1 bit_size: 1 fieldset/ICSCR: description: Internal clock sources calibration register. fields: - name: MSICAL description: MSI clock calibration These bits are initialized at startup with the factory-programmed MSI calibration trim value. When MSITRIM is written, MSICAL is updated with the sum of MSITRIM and the factory trim value. bit_offset: 0 bit_size: 8 - name: MSITRIM description: MSI clock trimming These bits provide an additional user-programmable trimming value that is added to the MSICAL[7:0] bits. It can be programmed to adjust to variations in voltage and temperature that influence the frequency of the MSI. bit_offset: 8 bit_size: 8 - name: HSICAL description: HSI clock calibration These bits are initialized at startup with the factory-programmed HSI calibration trim value. When HSITRIM is written, HSICAL is updated with the sum of HSITRIM and the factory trim value. bit_offset: 16 bit_size: 8 - name: HSITRIM description: HSI clock trimming These bits provide an additional user-programmable trimming value that is added to the HSICAL[7:0] bits. It can be programmed to adjust to variations in voltage and temperature that influence the frequency of the HSI. The default value is 64 when added to the HSICAL value, trim the HSI to 161MHz 1 11%. bit_offset: 24 bit_size: 7 fieldset/GPIOENR: description: I/O port clock enable register. fields: - name: GPIOAEN description: I/O port A clock enable This bit is set and cleared by software. bit_offset: 0 bit_size: 1 - name: GPIOBEN description: I/O port B clock enable This bit is set and cleared by software. bit_offset: 1 bit_size: 1 - name: GPIOCEN description: I/O port C clock enable This bit is set and cleared by software. bit_offset: 2 bit_size: 1 - name: GPIODEN description: I/O port D clock enable This bit is set and cleared by software. bit_offset: 3 bit_size: 1 - name: GPIOEEN description: I/O port E clock enable(1) This bit is set and cleared by software. bit_offset: 4 bit_size: 1 - name: GPIOFEN description: I/O port F clock enable This bit is set and cleared by software. bit_offset: 5 bit_size: 1 fieldset/GPIORSTR: description: I/O port reset register. fields: - name: GPIOARST description: I/O port A reset This bit is set and cleared by software. bit_offset: 0 bit_size: 1 - name: GPIOBRST description: I/O port B reset This bit is set and cleared by software. bit_offset: 1 bit_size: 1 - name: GPIOCRST description: I/O port C reset This bit is set and cleared by software. bit_offset: 2 bit_size: 1 - name: GPIODRST description: I/O port D reset This bit is set and cleared by software. bit_offset: 3 bit_size: 1 - name: GPIOERST description: I/O port E reset This bit is set and cleared by software. bit_offset: 4 bit_size: 1 - name: GPIOFRST description: I/O port F reset This bit is set and cleared by software. bit_offset: 5 bit_size: 1 fieldset/GPIOSMENR: description: I/O port in Sleep mode clock enable register. fields: - name: GPIOASMEN description: I/O port A clock enable during Sleep mode Set and cleared by software. bit_offset: 0 bit_size: 1 - name: GPIOBSMEN description: I/O port B clock enable during Sleep mode Set and cleared by software. bit_offset: 1 bit_size: 1 - name: GPIOCSMEN description: I/O port C clock enable during Sleep mode Set and cleared by software. bit_offset: 2 bit_size: 1 - name: GPIODSMEN description: I/O port D clock enable during Sleep mode(1) Set and cleared by software. bit_offset: 3 bit_size: 1 - name: GPIOESMEN description: I/O port E clock enable during Sleep mode Set and cleared by software. bit_offset: 4 bit_size: 1 - name: GPIOFSMEN description: I/O port F clock enable during Sleep mode Set and cleared by software. bit_offset: 5 bit_size: 1 fieldset/PLLCFGR: description: PLL configuration register. fields: - name: PLLSRC description: 'PLL input clock source This bit is controlled by software to select PLL clock source, as follows: The bitfield can be written only when the PLL is disabled. When the PLL is not used, selecting 00 allows saving power.' bit_offset: 0 bit_size: 2 enum: PLLSRC - name: PLLM description: 'Division factor M of the PLL input clock divider This bit is controlled by software to divide the PLL input clock before the actual phase-locked loop, as follows: The bitfield can be written only when the PLL is disabled. Caution: The software must set these bits so that the PLL input frequency after the /M divider is between 2.66 and 161MHz.' bit_offset: 4 bit_size: 3 enum: PLLM - name: PLLN description: 'PLL frequency multiplication factor N This bit is controlled by software to set the division factor of the fVCO feedback divider (that determines the PLL multiplication ratio) as follows: ... ... The bitfield can be written only when the PLL is disabled. Caution: The software must set these bits so that the VCO output frequency is between 96 and 3441MHz.' bit_offset: 8 bit_size: 7 enum: PLLN - name: PLLPEN description: 'PLLPCLK clock output enable This bit is controlled by software to enable/disable the PLLPCLK clock output of the PLL: Disabling the PLLPCLK clock output, when not used, allows saving power.' bit_offset: 16 bit_size: 1 - name: PLLP description: 'PLL VCO division factor P for PLLPCLK clock output This bitfield is controlled by software. It sets the PLL VCO division factor P as follows: ... The bitfield can be written only when the PLL is disabled. Caution: The software must set this bitfield so as not to exceed 541MHz on this clock.' bit_offset: 17 bit_size: 5 enum: PLLP - name: PLLQEN description: 'PLLQCLK clock output enable This bit is controlled by software to enable/disable the PLLQCLK clock output of the PLL: Disabling the PLLQCLK clock output, when not used, allows saving power.' bit_offset: 24 bit_size: 1 - name: PLLQ description: 'PLL VCO division factor Q for PLLQCLK clock output This bitfield is controlled by software. It sets the PLL VCO division factor Q as follows: The bitfield can be written only when the PLL is disabled. Caution: The software must set this bitfield so as not to exceed 541MHz on this clock.' bit_offset: 25 bit_size: 3 enum: PLLQ - name: PLLREN description: 'PLLRCLK clock output enable This bit is controlled by software to enable/disable the PLLRCLK clock output of the PLL: This bit cannot be written when PLLRCLK output of the PLL is selected for system clock. Disabling the PLLRCLK clock output, when not used, allows saving power.' bit_offset: 28 bit_size: 1 - name: PLLR description: 'PLL VCO division factor R for PLLRCLK clock output This bitfield is controlled by software. It sets the PLL VCO division factor R as follows: The bitfield can be written only when the PLL is disabled. The PLLRCLK clock can be selected as system clock. Caution: The software must set this bitfield so as not to exceed 122MHz on this clock.' bit_offset: 29 bit_size: 3 enum: PLLR enum/ADCSEL: bit_size: 2 variants: - name: SYS value: 0 - name: PLL1_P value: 1 - name: HSI value: 2 enum/CLK48SEL: bit_size: 2 variants: - name: DISABLE value: 0 - name: MSI value: 1 - name: PLL1_Q value: 2 - name: HSI48 value: 3 enum/HPRE: bit_size: 4 variants: - name: Div1 value: 0 - name: Div2 value: 8 - name: Div4 value: 9 - name: Div8 value: 10 - name: Div16 value: 11 - name: Div64 value: 12 - name: Div128 value: 13 - name: Div256 value: 14 - name: Div512 value: 15 enum/I2C1SEL: bit_size: 2 variants: - name: PCLK1 value: 0 - name: SYS value: 1 - name: HSI value: 2 enum/I2C3SEL: bit_size: 2 variants: - name: PCLK1 value: 0 - name: SYS value: 1 - name: HSI value: 2 enum/LPTIM1SEL: bit_size: 2 variants: - name: PCLK1 value: 0 - name: LSI value: 1 - name: HSI value: 2 - name: LSE value: 3 enum/LPTIM2SEL: bit_size: 2 variants: - name: PCLK1 value: 0 - name: LSI value: 1 - name: HSI value: 2 - name: LSE value: 3 enum/LPTIM3SEL: bit_size: 2 variants: - name: PCLK1 value: 0 - name: LSI value: 1 - name: HSI value: 2 - name: LSE value: 3 enum/LPUART1SEL: bit_size: 2 variants: - name: PCLK1 value: 0 - name: SYS value: 1 - name: HSI value: 2 - name: LSE value: 3 enum/LPUART2SEL: bit_size: 2 variants: - name: PCLK1 value: 0 - name: SYS value: 1 - name: HSI value: 2 - name: LSE value: 3 enum/LPUART3SEL: bit_size: 2 variants: - name: PCLK1 value: 0 - name: SYS value: 1 - name: HSI value: 2 - name: LSE value: 3 enum/LSCOSEL: bit_size: 1 variants: - name: LSI value: 0 - name: LSE value: 1 enum/LSEDRV: bit_size: 2 variants: - name: Low description: Low driving capability value: 0 - name: MediumLow description: Medium low driving capability value: 1 - name: MediumHigh description: Medium high driving capability value: 2 - name: High description: High driving capability value: 3 enum/LSIPREDIV: bit_size: 1 variants: - name: Div1 value: 0 - name: Div128 value: 1 enum/MCOPRE: bit_size: 4 variants: - name: Div1 value: 0 - name: Div2 value: 1 - name: Div4 value: 2 - name: Div8 value: 3 - name: Div16 value: 4 - name: Div32 value: 5 - name: Div64 value: 6 - name: Div128 value: 7 - name: Div256 value: 8 - name: Div512 value: 9 - name: Div1024 value: 10 enum/MCOSEL: bit_size: 4 variants: - name: DISABLE value: 0 - name: SYS value: 1 - name: MSI value: 2 - name: HSI value: 3 - name: HSE value: 4 - name: PLL1_R value: 5 - name: LSI value: 6 - name: LSE value: 7 - name: HSI48 value: 8 - name: RTC value: 9 - name: RTC_WKUP value: 10 enum/MSIRANGE: bit_size: 4 variants: - name: Range100K description: range 0 around 100 kHz value: 0 - name: Range200K description: range 1 around 200 kHz value: 1 - name: Range400K description: range 2 around 400 kHz value: 2 - name: Range800K description: range 3 around 800 kHz value: 3 - name: Range1M description: range 4 around 1 MHz value: 4 - name: Range2M description: range 5 around 2 MHz value: 5 - name: Range4M description: range 6 around 4 MHz value: 6 - name: Range8M description: range 7 around 8 MHz value: 7 - name: Range16M description: range 8 around 16 MHz value: 8 - name: Range24M description: range 9 around 24 MHz value: 9 - name: Range32M description: range 10 around 32 MHz value: 10 - name: Range48M description: range 11 around 48 MHz value: 11 enum/MSIRGSEL: bit_size: 1 variants: - name: CSR description: MSI Range is provided by MSISRANGE[3:0] in RCC_CSR register value: 0 - name: CR description: MSI Range is provided by MSIRANGE[3:0] in the RCC_CR register value: 1 enum/MSISRANGE: bit_size: 4 variants: - name: RANGE_81MHz value: 4 enum/PLLM: bit_size: 3 variants: - name: Div1 value: 0 - name: Div2 value: 1 - name: Div3 value: 2 - name: Div4 value: 3 - name: Div5 value: 4 - name: Div6 value: 5 - name: Div7 value: 6 - name: Div8 value: 7 enum/PLLN: bit_size: 7 variants: - name: Mul4 value: 4 - name: Mul5 value: 5 - name: Mul6 value: 6 - name: Mul7 value: 7 - name: Mul8 value: 8 - name: Mul9 value: 9 - name: Mul10 value: 10 - name: Mul11 value: 11 - name: Mul12 value: 12 - name: Mul13 value: 13 - name: Mul14 value: 14 - name: Mul15 value: 15 - name: Mul16 value: 16 - name: Mul17 value: 17 - name: Mul18 value: 18 - name: Mul19 value: 19 - name: Mul20 value: 20 - name: Mul21 value: 21 - name: Mul22 value: 22 - name: Mul23 value: 23 - name: Mul24 value: 24 - name: Mul25 value: 25 - name: Mul26 value: 26 - name: Mul27 value: 27 - name: Mul28 value: 28 - name: Mul29 value: 29 - name: Mul30 value: 30 - name: Mul31 value: 31 - name: Mul32 value: 32 - name: Mul33 value: 33 - name: Mul34 value: 34 - name: Mul35 value: 35 - name: Mul36 value: 36 - name: Mul37 value: 37 - name: Mul38 value: 38 - name: Mul39 value: 39 - name: Mul40 value: 40 - name: Mul41 value: 41 - name: Mul42 value: 42 - name: Mul43 value: 43 - name: Mul44 value: 44 - name: Mul45 value: 45 - name: Mul46 value: 46 - name: Mul47 value: 47 - name: Mul48 value: 48 - name: Mul49 value: 49 - name: Mul50 value: 50 - name: Mul51 value: 51 - name: Mul52 value: 52 - name: Mul53 value: 53 - name: Mul54 value: 54 - name: Mul55 value: 55 - name: Mul56 value: 56 - name: Mul57 value: 57 - name: Mul58 value: 58 - name: Mul59 value: 59 - name: Mul60 value: 60 - name: Mul61 value: 61 - name: Mul62 value: 62 - name: Mul63 value: 63 - name: Mul64 value: 64 - name: Mul65 value: 65 - name: Mul66 value: 66 - name: Mul67 value: 67 - name: Mul68 value: 68 - name: Mul69 value: 69 - name: Mul70 value: 70 - name: Mul71 value: 71 - name: Mul72 value: 72 - name: Mul73 value: 73 - name: Mul74 value: 74 - name: Mul75 value: 75 - name: Mul76 value: 76 - name: Mul77 value: 77 - name: Mul78 value: 78 - name: Mul79 value: 79 - name: Mul80 value: 80 - name: Mul81 value: 81 - name: Mul82 value: 82 - name: Mul83 value: 83 - name: Mul84 value: 84 - name: Mul85 value: 85 - name: Mul86 value: 86 - name: Mul87 value: 87 - name: Mul88 value: 88 - name: Mul89 value: 89 - name: Mul90 value: 90 - name: Mul91 value: 91 - name: Mul92 value: 92 - name: Mul93 value: 93 - name: Mul94 value: 94 - name: Mul95 value: 95 - name: Mul96 value: 96 - name: Mul97 value: 97 - name: Mul98 value: 98 - name: Mul99 value: 99 - name: Mul100 value: 100 - name: Mul101 value: 101 - name: Mul102 value: 102 - name: Mul103 value: 103 - name: Mul104 value: 104 - name: Mul105 value: 105 - name: Mul106 value: 106 - name: Mul107 value: 107 - name: Mul108 value: 108 - name: Mul109 value: 109 - name: Mul110 value: 110 - name: Mul111 value: 111 - name: Mul112 value: 112 - name: Mul113 value: 113 - name: Mul114 value: 114 - name: Mul115 value: 115 - name: Mul116 value: 116 - name: Mul117 value: 117 - name: Mul118 value: 118 - name: Mul119 value: 119 - name: Mul120 value: 120 - name: Mul121 value: 121 - name: Mul122 value: 122 - name: Mul123 value: 123 - name: Mul124 value: 124 - name: Mul125 value: 125 - name: Mul126 value: 126 - name: Mul127 value: 127 enum/PLLP: bit_size: 5 variants: - name: Div2 value: 1 - name: Div3 value: 2 - name: Div4 value: 3 - name: Div5 value: 4 - name: Div6 value: 5 - name: Div7 value: 6 - name: Div8 value: 7 - name: Div9 value: 8 - name: Div10 value: 9 - name: Div11 value: 10 - name: Div12 value: 11 - name: Div13 value: 12 - name: Div14 value: 13 - name: Div15 value: 14 - name: Div16 value: 15 - name: Div17 value: 16 - name: Div18 value: 17 - name: Div19 value: 18 - name: Div20 value: 19 - name: Div21 value: 20 - name: Div22 value: 21 - name: Div23 value: 22 - name: Div24 value: 23 - name: Div25 value: 24 - name: Div26 value: 25 - name: Div27 value: 26 - name: Div28 value: 27 - name: Div29 value: 28 - name: Div30 value: 29 - name: Div31 value: 30 - name: Div32 value: 31 enum/PLLQ: bit_size: 3 variants: - name: Div2 value: 1 - name: Div3 value: 2 - name: Div4 value: 3 - name: Div5 value: 4 - name: Div6 value: 5 - name: Div7 value: 6 - name: Div8 value: 7 enum/PLLR: bit_size: 3 variants: - name: Div2 value: 1 - name: Div3 value: 2 - name: Div4 value: 3 - name: Div5 value: 4 - name: Div6 value: 5 - name: Div7 value: 6 - name: Div8 value: 7 enum/PLLSRC: bit_size: 2 variants: - name: DISABLE value: 0 - name: MSI value: 1 - name: HSI value: 2 - name: HSE value: 3 enum/PPRE: bit_size: 3 variants: - name: Div1 description: HCLK not divided value: 0 - name: Div2 description: HCLK divided by 2 value: 4 - name: Div4 description: HCLK divided by 4 value: 5 - name: Div8 description: HCLK divided by 8 value: 6 - name: Div16 description: HCLK divided by 16 value: 7 enum/RTCSEL: bit_size: 2 variants: - name: DISABLE value: 0 - name: LSE value: 1 - name: LSI value: 2 - name: HSE value: 3 enum/SW: bit_size: 3 variants: - name: MSI value: 0 - name: HSI value: 1 - name: HSE value: 2 - name: PLL1_R value: 3 - name: LSI value: 4 - name: LSE value: 5 enum/TIM15SEL: bit_size: 1 variants: - name: PCLK1_TIM value: 0 - name: PLL1_Q value: 1 enum/TIM1SEL: bit_size: 1 variants: - name: PCLK1_TIM value: 0 - name: PLL1_Q value: 1 enum/USART1SEL: bit_size: 2 variants: - name: PCLK1 value: 0 - name: SYS value: 1 - name: HSI value: 2 - name: LSE value: 3 enum/USART2SEL: bit_size: 2 variants: - name: PCLK1 value: 0 - name: SYS value: 1 - name: HSI value: 2 - name: LSE value: 3