block/RCC: description: Reset and clock control items: - name: CR description: Clock control register byte_offset: 0 fieldset: CR - name: ICSCR description: Internal clock sources calibration register byte_offset: 4 fieldset: ICSCR - name: CFGR description: Clock configuration register byte_offset: 8 fieldset: CFGR - name: PLLCFGR description: PLL configuration register byte_offset: 12 fieldset: PLLCFGR - name: PLLSAI1CFGR description: PLLSAI1 configuration register byte_offset: 16 fieldset: PLLCFGR - name: PLLSAI2CFGR description: PLLSAI2 configuration register byte_offset: 20 fieldset: PLLCFGR - name: CIER description: Clock interrupt enable register byte_offset: 24 fieldset: CIER - name: CIFR description: Clock interrupt flag register byte_offset: 28 access: Read fieldset: CIFR - name: CICR description: Clock interrupt clear register byte_offset: 32 access: Write fieldset: CICR - name: AHB1RSTR description: AHB1 peripheral reset register byte_offset: 40 fieldset: AHB1RSTR - name: AHB2RSTR description: AHB2 peripheral reset register byte_offset: 44 fieldset: AHB2RSTR - name: AHB3RSTR description: AHB3 peripheral reset register byte_offset: 48 fieldset: AHB3RSTR - name: APB1RSTR1 description: APB1 peripheral reset register 1 byte_offset: 56 fieldset: APB1RSTR1 - name: APB1RSTR2 description: APB1 peripheral reset register 2 byte_offset: 60 fieldset: APB1RSTR2 - name: APB2RSTR description: APB2 peripheral reset register byte_offset: 64 fieldset: APB2RSTR - name: AHB1ENR description: AHB1 peripheral clock enable register byte_offset: 72 fieldset: AHB1ENR - name: AHB2ENR description: AHB2 peripheral clock enable register byte_offset: 76 fieldset: AHB2ENR - name: AHB3ENR description: AHB3 peripheral clock enable register byte_offset: 80 fieldset: AHB3ENR - name: APB1ENR1 description: APB1ENR1 byte_offset: 88 fieldset: APB1ENR1 - name: APB1ENR2 description: APB1 peripheral clock enable register 2 byte_offset: 92 fieldset: APB1ENR2 - name: APB2ENR description: APB2ENR byte_offset: 96 fieldset: APB2ENR - name: AHB1SMENR description: AHB1 peripheral clocks enable in Sleep and Stop modes register byte_offset: 104 fieldset: AHB1SMENR - name: AHB2SMENR description: AHB2 peripheral clocks enable in Sleep and Stop modes register byte_offset: 108 fieldset: AHB2SMENR - name: AHB3SMENR description: AHB3 peripheral clocks enable in Sleep and Stop modes register byte_offset: 112 fieldset: AHB3SMENR - name: APB1SMENR1 description: APB1SMENR1 byte_offset: 120 fieldset: APB1SMENR1 - name: APB1SMENR2 description: APB1 peripheral clocks enable in Sleep and Stop modes register 2 byte_offset: 124 fieldset: APB1SMENR2 - name: APB2SMENR description: APB2SMENR byte_offset: 128 fieldset: APB2SMENR - name: CCIPR description: CCIPR byte_offset: 136 fieldset: CCIPR - name: BDCR description: BDCR byte_offset: 144 fieldset: BDCR - name: CSR description: CSR byte_offset: 148 fieldset: CSR - name: CRRCR description: Clock recovery RC register byte_offset: 152 fieldset: CRRCR - name: CCIPR2 description: Peripherals independent clock configuration register byte_offset: 156 fieldset: CCIPR2 - name: SECCFGR description: RCC secure configuration register byte_offset: 184 fieldset: SECCFGR - name: SECSR description: RCC secure status register byte_offset: 188 fieldset: SECSR - name: AHB1SECSR description: RCC AHB1 security status register byte_offset: 232 access: Read fieldset: AHB1SECSR - name: AHB2SECSR description: RCC AHB2 security status register byte_offset: 236 access: Read fieldset: AHB2SECSR - name: AHB3SECSR description: RCC AHB3 security status register byte_offset: 240 access: Read fieldset: AHB3SECSR - name: APB1SECSR1 description: RCC APB1 security status register 1 byte_offset: 248 access: Read fieldset: APB1SECSR1 - name: APB1SECSR2 description: RCC APB1 security status register 2 byte_offset: 252 access: Read fieldset: APB1SECSR2 - name: APB2SECSR description: RCC APB2 security status register byte_offset: 256 access: Read fieldset: APB2SECSR fieldset/AHB1ENR: description: AHB1 peripheral clock enable register fields: - name: DMA1EN description: DMA1 clock enable bit_offset: 0 bit_size: 1 - name: DMA2EN description: DMA2 clock enable bit_offset: 1 bit_size: 1 - name: DMAMUX1EN description: DMAMUX clock enable bit_offset: 2 bit_size: 1 - name: FLASHEN description: Flash memory interface clock enable bit_offset: 8 bit_size: 1 - name: CRCEN description: CRC clock enable bit_offset: 12 bit_size: 1 - name: TSCEN description: Touch Sensing Controller clock enable bit_offset: 16 bit_size: 1 - name: GTZCEN description: GTZCEN bit_offset: 22 bit_size: 1 fieldset/AHB1RSTR: description: AHB1 peripheral reset register fields: - name: DMA1RST description: DMA1 reset bit_offset: 0 bit_size: 1 - name: DMA2RST description: DMA2 reset bit_offset: 1 bit_size: 1 - name: DMAMUX1RST description: DMAMUX1RST bit_offset: 2 bit_size: 1 - name: FLASHRST description: Flash memory interface reset bit_offset: 8 bit_size: 1 - name: CRCRST description: CRC reset bit_offset: 12 bit_size: 1 - name: TSCRST description: Touch Sensing Controller reset bit_offset: 16 bit_size: 1 - name: GTZCRST description: GTZC reset bit_offset: 22 bit_size: 1 fieldset/AHB1SECSR: description: RCC AHB1 security status register fields: - name: DMA1SECF description: DMA1SECF bit_offset: 0 bit_size: 1 - name: DMA2SECF description: DMA2SECF bit_offset: 1 bit_size: 1 - name: DMAMUX1SECF description: DMAMUX1SECF bit_offset: 2 bit_size: 1 - name: FLASHSECF description: FLASHSECF bit_offset: 8 bit_size: 1 - name: SRAM1SECF description: SRAM1SECF bit_offset: 9 bit_size: 1 - name: CRCSECF description: CRCSECF bit_offset: 12 bit_size: 1 - name: TSCSECF description: TSCSECF bit_offset: 16 bit_size: 1 - name: GTZCSECF description: GTZCSECF bit_offset: 22 bit_size: 1 - name: ICACHESECF description: ICACHESECF bit_offset: 23 bit_size: 1 fieldset/AHB1SMENR: description: AHB1 peripheral clocks enable in Sleep and Stop modes register fields: - name: DMA1SMEN description: DMA1 clocks enable during Sleep and Stop modes bit_offset: 0 bit_size: 1 - name: DMA2SMEN description: DMA2 clocks enable during Sleep and Stop modes bit_offset: 1 bit_size: 1 - name: DMAMUX1SMEN description: DMAMUX clock enable during Sleep and Stop modes bit_offset: 2 bit_size: 1 - name: FLASHSMEN description: Flash memory interface clocks enable during Sleep and Stop modes bit_offset: 8 bit_size: 1 - name: SRAM1SMEN description: SRAM1 interface clocks enable during Sleep and Stop modes bit_offset: 9 bit_size: 1 - name: CRCSMEN description: CRCSMEN bit_offset: 12 bit_size: 1 - name: TSCSMEN description: Touch Sensing Controller clocks enable during Sleep and Stop modes bit_offset: 16 bit_size: 1 - name: GTZCSMEN description: GTZCSMEN bit_offset: 22 bit_size: 1 - name: ICACHESMEN description: ICACHESMEN bit_offset: 23 bit_size: 1 fieldset/AHB2ENR: description: AHB2 peripheral clock enable register fields: - name: GPIOAEN description: IO port A clock enable bit_offset: 0 bit_size: 1 - name: GPIOBEN description: IO port B clock enable bit_offset: 1 bit_size: 1 - name: GPIOCEN description: IO port C clock enable bit_offset: 2 bit_size: 1 - name: GPIODEN description: IO port D clock enable bit_offset: 3 bit_size: 1 - name: GPIOEEN description: IO port E clock enable bit_offset: 4 bit_size: 1 - name: GPIOFEN description: IO port F clock enable bit_offset: 5 bit_size: 1 - name: GPIOGEN description: IO port G clock enable bit_offset: 6 bit_size: 1 - name: GPIOHEN description: IO port H clock enable bit_offset: 7 bit_size: 1 - name: ADCEN description: ADC clock enable bit_offset: 13 bit_size: 1 - name: AESEN description: AES accelerator clock enable bit_offset: 16 bit_size: 1 - name: HASHEN description: HASH clock enable bit_offset: 17 bit_size: 1 - name: RNGEN description: Random Number Generator clock enable bit_offset: 18 bit_size: 1 - name: PKAEN description: PKAEN bit_offset: 19 bit_size: 1 - name: OTFDEC1EN description: OTFDEC1EN bit_offset: 21 bit_size: 1 - name: SDMMC1EN description: SDMMC1 clock enable bit_offset: 22 bit_size: 1 fieldset/AHB2RSTR: description: AHB2 peripheral reset register fields: - name: GPIOARST description: IO port A reset bit_offset: 0 bit_size: 1 - name: GPIOBRST description: IO port B reset bit_offset: 1 bit_size: 1 - name: GPIOCRST description: IO port C reset bit_offset: 2 bit_size: 1 - name: GPIODRST description: IO port D reset bit_offset: 3 bit_size: 1 - name: GPIOERST description: IO port E reset bit_offset: 4 bit_size: 1 - name: GPIOFRST description: IO port F reset bit_offset: 5 bit_size: 1 - name: GPIOGRST description: IO port G reset bit_offset: 6 bit_size: 1 - name: GPIOHRST description: IO port H reset bit_offset: 7 bit_size: 1 - name: ADCRST description: ADC reset bit_offset: 13 bit_size: 1 - name: AESRST description: AES hardware accelerator reset bit_offset: 16 bit_size: 1 - name: HASHRST description: Hash reset bit_offset: 17 bit_size: 1 - name: RNGRST description: Random number generator reset bit_offset: 18 bit_size: 1 - name: PKARST description: PKARST bit_offset: 19 bit_size: 1 - name: OTFDEC1RST description: OTFDEC1RST bit_offset: 21 bit_size: 1 - name: SDMMC1RST description: SDMMC1 reset bit_offset: 22 bit_size: 1 fieldset/AHB2SECSR: description: RCC AHB2 security status register fields: - name: GPIOASECF description: GPIOASECF bit_offset: 0 bit_size: 1 - name: GPIOBSECF description: GPIOBSECF bit_offset: 1 bit_size: 1 - name: GPIOCSECF description: GPIOCSECF bit_offset: 2 bit_size: 1 - name: GPIODSECF description: GPIODSECF bit_offset: 3 bit_size: 1 - name: GPIOESECF description: GPIOESECF bit_offset: 4 bit_size: 1 - name: GPIOFSECF description: GPIOFSECF bit_offset: 5 bit_size: 1 - name: GPIOGSECF description: GPIOGSECF bit_offset: 6 bit_size: 1 - name: GPIOHSECF description: GPIOHSECF bit_offset: 7 bit_size: 1 - name: SRAM2SECF description: SRAM2SECF bit_offset: 9 bit_size: 1 - name: OTFDEC1SECF description: OTFDEC1SECF bit_offset: 21 bit_size: 1 - name: SDMMC1SECF description: SDMMC1SECF bit_offset: 22 bit_size: 1 fieldset/AHB2SMENR: description: AHB2 peripheral clocks enable in Sleep and Stop modes register fields: - name: GPIOASMEN description: IO port A clocks enable during Sleep and Stop modes bit_offset: 0 bit_size: 1 - name: GPIOBSMEN description: IO port B clocks enable during Sleep and Stop modes bit_offset: 1 bit_size: 1 - name: GPIOCSMEN description: IO port C clocks enable during Sleep and Stop modes bit_offset: 2 bit_size: 1 - name: GPIODSMEN description: IO port D clocks enable during Sleep and Stop modes bit_offset: 3 bit_size: 1 - name: GPIOESMEN description: IO port E clocks enable during Sleep and Stop modes bit_offset: 4 bit_size: 1 - name: GPIOFSMEN description: IO port F clocks enable during Sleep and Stop modes bit_offset: 5 bit_size: 1 - name: GPIOGSMEN description: IO port G clocks enable during Sleep and Stop modes bit_offset: 6 bit_size: 1 - name: GPIOHSMEN description: IO port H clocks enable during Sleep and Stop modes bit_offset: 7 bit_size: 1 - name: SRAM2SMEN description: SRAM2 interface clocks enable during Sleep and Stop modes bit_offset: 9 bit_size: 1 - name: ADCFSSMEN description: ADC clocks enable during Sleep and Stop modes bit_offset: 13 bit_size: 1 - name: AESSMEN description: AES accelerator clocks enable during Sleep and Stop modes bit_offset: 16 bit_size: 1 - name: HASHSMEN description: HASH clock enable during Sleep and Stop modes bit_offset: 17 bit_size: 1 - name: RNGSMEN description: Random Number Generator clocks enable during Sleep and Stop modes bit_offset: 18 bit_size: 1 - name: PKASMEN description: PKASMEN bit_offset: 19 bit_size: 1 - name: OTFDEC1SMEN description: OTFDEC1SMEN bit_offset: 21 bit_size: 1 - name: SDMMC1SMEN description: SDMMC1 clocks enable during Sleep and Stop modes bit_offset: 22 bit_size: 1 fieldset/AHB3ENR: description: AHB3 peripheral clock enable register fields: - name: FMCEN description: Flexible memory controller clock enable bit_offset: 0 bit_size: 1 - name: OCTOSPI1EN description: OCTOSPI1EN bit_offset: 8 bit_size: 1 fieldset/AHB3RSTR: description: AHB3 peripheral reset register fields: - name: FMCRST description: Flexible memory controller reset bit_offset: 0 bit_size: 1 - name: OCTOSPI1RST description: OCTOSPI1RST bit_offset: 8 bit_size: 1 fieldset/AHB3SECSR: description: RCC AHB3 security status register fields: - name: FSMCSECF description: FSMCSECF bit_offset: 0 bit_size: 1 - name: OCTOSPI1SECF description: OCTOSPI1SECF bit_offset: 8 bit_size: 1 fieldset/AHB3SMENR: description: AHB3 peripheral clocks enable in Sleep and Stop modes register fields: - name: FMCSMEN description: Flexible memory controller clocks enable during Sleep and Stop modes bit_offset: 0 bit_size: 1 - name: OCTOSPI1SMEN description: OCTOSPI1SMEN bit_offset: 8 bit_size: 1 fieldset/APB1ENR1: description: APB1ENR1 fields: - name: TIM2EN description: TIM2 timer clock enable bit_offset: 0 bit_size: 1 - name: TIM3EN description: TIM3 timer clock enable bit_offset: 1 bit_size: 1 - name: TIM4EN description: TIM4 timer clock enable bit_offset: 2 bit_size: 1 - name: TIM5EN description: TIM5 timer clock enable bit_offset: 3 bit_size: 1 - name: TIM6EN description: TIM6 timer clock enable bit_offset: 4 bit_size: 1 - name: TIM7EN description: TIM7 timer clock enable bit_offset: 5 bit_size: 1 - name: RTCAPBEN description: RTC APB clock enable bit_offset: 10 bit_size: 1 - name: WWDGEN description: Window watchdog clock enable bit_offset: 11 bit_size: 1 - name: SPI2EN description: SPI2 clock enable bit_offset: 14 bit_size: 1 - name: SPI3EN description: SPI3 clock enable bit_offset: 15 bit_size: 1 - name: USART2EN description: USART2 clock enable bit_offset: 17 bit_size: 1 - name: USART3EN description: USART3 clock enable bit_offset: 18 bit_size: 1 - name: UART4EN description: UART4 clock enable bit_offset: 19 bit_size: 1 - name: UART5EN description: UART5 clock enable bit_offset: 20 bit_size: 1 - name: I2C1EN description: I2C1 clock enable bit_offset: 21 bit_size: 1 - name: I2C2EN description: I2C2 clock enable bit_offset: 22 bit_size: 1 - name: I2C3EN description: I2C3 clock enable bit_offset: 23 bit_size: 1 - name: CRSEN description: Clock Recovery System clock enable bit_offset: 24 bit_size: 1 - name: PWREN description: Power interface clock enable bit_offset: 28 bit_size: 1 - name: DAC1EN description: DAC1 interface clock enable bit_offset: 29 bit_size: 1 - name: OPAMPEN description: OPAMP interface clock enable bit_offset: 30 bit_size: 1 - name: LPTIM1EN description: Low power timer 1 clock enable bit_offset: 31 bit_size: 1 fieldset/APB1ENR2: description: APB1 peripheral clock enable register 2 fields: - name: LPUART1EN description: Low power UART 1 clock enable bit_offset: 0 bit_size: 1 - name: I2C4EN description: I2C4 clock enable bit_offset: 1 bit_size: 1 - name: LPTIM2EN description: LPTIM2EN bit_offset: 5 bit_size: 1 - name: LPTIM3EN description: LPTIM3EN bit_offset: 6 bit_size: 1 - name: FDCAN1EN description: FDCAN1EN bit_offset: 9 bit_size: 1 - name: USBEN description: USBEN bit_offset: 21 bit_size: 1 - name: UCPD1EN description: UCPD1EN bit_offset: 23 bit_size: 1 fieldset/APB1RSTR1: description: APB1 peripheral reset register 1 fields: - name: TIM2RST description: TIM2 timer reset bit_offset: 0 bit_size: 1 - name: TIM3RST description: TIM3 timer reset bit_offset: 1 bit_size: 1 - name: TIM4RST description: TIM3 timer reset bit_offset: 2 bit_size: 1 - name: TIM5RST description: TIM5 timer reset bit_offset: 3 bit_size: 1 - name: TIM6RST description: TIM6 timer reset bit_offset: 4 bit_size: 1 - name: TIM7RST description: TIM7 timer reset bit_offset: 5 bit_size: 1 - name: SPI2RST description: SPI2 reset bit_offset: 14 bit_size: 1 - name: SPI3RST description: SPI3 reset bit_offset: 15 bit_size: 1 - name: USART2RST description: USART2 reset bit_offset: 17 bit_size: 1 - name: USART3RST description: USART3 reset bit_offset: 18 bit_size: 1 - name: UART4RST description: UART4 reset bit_offset: 19 bit_size: 1 - name: UART5RST description: UART5 reset bit_offset: 20 bit_size: 1 - name: I2C1RST description: I2C1 reset bit_offset: 21 bit_size: 1 - name: I2C2RST description: I2C2 reset bit_offset: 22 bit_size: 1 - name: I2C3RST description: I2C3 reset bit_offset: 23 bit_size: 1 - name: CRSRST description: CRS reset bit_offset: 24 bit_size: 1 - name: PWRRST description: Power interface reset bit_offset: 28 bit_size: 1 - name: DAC1RST description: DAC1 interface reset bit_offset: 29 bit_size: 1 - name: OPAMPRST description: OPAMP interface reset bit_offset: 30 bit_size: 1 - name: LPTIM1RST description: Low Power Timer 1 reset bit_offset: 31 bit_size: 1 fieldset/APB1RSTR2: description: APB1 peripheral reset register 2 fields: - name: LPUART1RST description: Low-power UART 1 reset bit_offset: 0 bit_size: 1 - name: I2C4RST description: I2C4 reset bit_offset: 1 bit_size: 1 - name: LPTIM2RST description: Low-power timer 2 reset bit_offset: 5 bit_size: 1 - name: LPTIM3RST description: LPTIM3RST bit_offset: 6 bit_size: 1 - name: FDCAN1RST description: FDCAN1RST bit_offset: 9 bit_size: 1 - name: USBRST description: USBRST bit_offset: 21 bit_size: 1 - name: UCPD1RST description: UCPD1RST bit_offset: 23 bit_size: 1 fieldset/APB1SECSR1: description: RCC APB1 security status register 1 fields: - name: TIM2SECF description: TIM2SECF bit_offset: 0 bit_size: 1 - name: TIM3SECF description: TIM3SECF bit_offset: 1 bit_size: 1 - name: TIM4SECF description: TIM4SECF bit_offset: 2 bit_size: 1 - name: TIM5SECF description: TIM5SECF bit_offset: 3 bit_size: 1 - name: TIM6SECF description: TIM6SECF bit_offset: 4 bit_size: 1 - name: TIM7SECF description: TIM7SECF bit_offset: 5 bit_size: 1 - name: RTCAPBSECF description: RTCAPBSECF bit_offset: 10 bit_size: 1 - name: WWDGSECF description: WWDGSECF bit_offset: 11 bit_size: 1 - name: SPI2SECF description: SPI2SECF bit_offset: 14 bit_size: 1 - name: SPI3SECF description: SPI3SECF bit_offset: 15 bit_size: 1 - name: UART2SECF description: UART2SECF bit_offset: 17 bit_size: 1 - name: UART3SECF description: UART3SECF bit_offset: 18 bit_size: 1 - name: UART4SECF description: UART4SECF bit_offset: 19 bit_size: 1 - name: UART5SECF description: UART5SECF bit_offset: 20 bit_size: 1 - name: I2C1SECF description: I2C1SECF bit_offset: 21 bit_size: 1 - name: I2C2SECF description: I2C2SECF bit_offset: 22 bit_size: 1 - name: I2C3SECF description: I2C3SECF bit_offset: 23 bit_size: 1 - name: CRSSECF description: CRSSECF bit_offset: 24 bit_size: 1 - name: PWRSECF description: PWRSECF bit_offset: 28 bit_size: 1 - name: DACSECF description: DACSECF bit_offset: 29 bit_size: 1 - name: OPAMPSECF description: OPAMPSECF bit_offset: 30 bit_size: 1 - name: LPTIM1SECF description: LPTIM1SECF bit_offset: 31 bit_size: 1 fieldset/APB1SECSR2: description: RCC APB1 security status register 2 fields: - name: LPUART1SECF description: LPUART1SECF bit_offset: 0 bit_size: 1 - name: I2C4SECF description: I2C4SECF bit_offset: 1 bit_size: 1 - name: LPTIM2SECF description: LPTIM2SECF bit_offset: 5 bit_size: 1 - name: LPTIM3SECF description: LPTIM3SECF bit_offset: 6 bit_size: 1 - name: FDCAN1SECF description: FDCAN1SECF bit_offset: 9 bit_size: 1 - name: USBSECF description: USBSECF bit_offset: 21 bit_size: 1 - name: UCPD1SECF description: UCPD1SECF bit_offset: 23 bit_size: 1 fieldset/APB1SMENR1: description: APB1SMENR1 fields: - name: TIM2SMEN description: TIM2 timer clocks enable during Sleep and Stop modes bit_offset: 0 bit_size: 1 - name: TIM3SMEN description: TIM3 timer clocks enable during Sleep and Stop modes bit_offset: 1 bit_size: 1 - name: TIM4SMEN description: TIM4 timer clocks enable during Sleep and Stop modes bit_offset: 2 bit_size: 1 - name: TIM5SMEN description: TIM5 timer clocks enable during Sleep and Stop modes bit_offset: 3 bit_size: 1 - name: TIM6SMEN description: TIM6 timer clocks enable during Sleep and Stop modes bit_offset: 4 bit_size: 1 - name: TIM7SMEN description: TIM7 timer clocks enable during Sleep and Stop modes bit_offset: 5 bit_size: 1 - name: RTCAPBSMEN description: RTC APB clock enable during Sleep and Stop modes bit_offset: 10 bit_size: 1 - name: WWDGSMEN description: Window watchdog clocks enable during Sleep and Stop modes bit_offset: 11 bit_size: 1 - name: SPI2SMEN description: SPI2 clocks enable during Sleep and Stop modes bit_offset: 14 bit_size: 1 - name: SP3SMEN description: SPI3 clocks enable during Sleep and Stop modes bit_offset: 15 bit_size: 1 - name: USART2SMEN description: USART2 clocks enable during Sleep and Stop modes bit_offset: 17 bit_size: 1 - name: USART3SMEN description: USART3 clocks enable during Sleep and Stop modes bit_offset: 18 bit_size: 1 - name: UART4SMEN description: UART4 clocks enable during Sleep and Stop modes bit_offset: 19 bit_size: 1 - name: UART5SMEN description: UART5 clocks enable during Sleep and Stop modes bit_offset: 20 bit_size: 1 - name: I2C1SMEN description: I2C1 clocks enable during Sleep and Stop modes bit_offset: 21 bit_size: 1 - name: I2C2SMEN description: I2C2 clocks enable during Sleep and Stop modes bit_offset: 22 bit_size: 1 - name: I2C3SMEN description: I2C3 clocks enable during Sleep and Stop modes bit_offset: 23 bit_size: 1 - name: CRSSMEN description: CRS clock enable during Sleep and Stop modes bit_offset: 24 bit_size: 1 - name: PWRSMEN description: Power interface clocks enable during Sleep and Stop modes bit_offset: 28 bit_size: 1 - name: DAC1SMEN description: DAC1 interface clocks enable during Sleep and Stop modes bit_offset: 29 bit_size: 1 - name: OPAMPSMEN description: OPAMP interface clocks enable during Sleep and Stop modes bit_offset: 30 bit_size: 1 - name: LPTIM1SMEN description: Low power timer 1 clocks enable during Sleep and Stop modes bit_offset: 31 bit_size: 1 fieldset/APB1SMENR2: description: APB1 peripheral clocks enable in Sleep and Stop modes register 2 fields: - name: LPUART1SMEN description: Low power UART 1 clocks enable during Sleep and Stop modes bit_offset: 0 bit_size: 1 - name: I2C4SMEN description: I2C4 clocks enable during Sleep and Stop modes bit_offset: 1 bit_size: 1 - name: LPTIM2SMEN description: LPTIM2SMEN bit_offset: 5 bit_size: 1 - name: LPTIM3SMEN description: LPTIM3SMEN bit_offset: 6 bit_size: 1 - name: FDCAN1SMEN description: FDCAN1SMEN bit_offset: 9 bit_size: 1 - name: USBSMEN description: USBSMEN bit_offset: 21 bit_size: 1 - name: UCPD1SMEN description: UCPD1SMEN bit_offset: 23 bit_size: 1 fieldset/APB2ENR: description: APB2ENR fields: - name: SYSCFGEN description: SYSCFG clock enable bit_offset: 0 bit_size: 1 - name: TIM1EN description: TIM1 timer clock enable bit_offset: 11 bit_size: 1 - name: SPI1EN description: SPI1 clock enable bit_offset: 12 bit_size: 1 - name: TIM8EN description: TIM8 timer clock enable bit_offset: 13 bit_size: 1 - name: USART1EN description: USART1clock enable bit_offset: 14 bit_size: 1 - name: TIM15EN description: TIM15 timer clock enable bit_offset: 16 bit_size: 1 - name: TIM16EN description: TIM16 timer clock enable bit_offset: 17 bit_size: 1 - name: TIM17EN description: TIM17 timer clock enable bit_offset: 18 bit_size: 1 - name: SAI1EN description: SAI1 clock enable bit_offset: 21 bit_size: 1 - name: SAI2EN description: SAI2 clock enable bit_offset: 22 bit_size: 1 - name: DFSDM1EN description: DFSDM timer clock enable bit_offset: 24 bit_size: 1 fieldset/APB2RSTR: description: APB2 peripheral reset register fields: - name: SYSCFGRST description: System configuration (SYSCFG) reset bit_offset: 0 bit_size: 1 - name: TIM1RST description: TIM1 timer reset bit_offset: 11 bit_size: 1 - name: SPI1RST description: SPI1 reset bit_offset: 12 bit_size: 1 - name: TIM8RST description: TIM8 timer reset bit_offset: 13 bit_size: 1 - name: USART1RST description: USART1 reset bit_offset: 14 bit_size: 1 - name: TIM15RST description: TIM15 timer reset bit_offset: 16 bit_size: 1 - name: TIM16RST description: TIM16 timer reset bit_offset: 17 bit_size: 1 - name: TIM17RST description: TIM17 timer reset bit_offset: 18 bit_size: 1 - name: SAI1RST description: Serial audio interface 1 (SAI1) reset bit_offset: 21 bit_size: 1 - name: SAI2RST description: Serial audio interface 2 (SAI2) reset bit_offset: 22 bit_size: 1 - name: DFSDM1RST description: Digital filters for sigma-delata modulators (DFSDM) reset bit_offset: 24 bit_size: 1 fieldset/APB2SECSR: description: RCC APB2 security status register fields: - name: SYSCFGSECF description: SYSCFGSECF bit_offset: 0 bit_size: 1 - name: TIM1SECF description: TIM1SECF bit_offset: 11 bit_size: 1 - name: SPI1SECF description: SPI1SECF bit_offset: 12 bit_size: 1 - name: TIM8SECF description: TIM8SECF bit_offset: 13 bit_size: 1 - name: USART1SECF description: USART1SECF bit_offset: 14 bit_size: 1 - name: TIM15SECF description: TIM15SECF bit_offset: 16 bit_size: 1 - name: TIM16SECF description: TIM16SECF bit_offset: 17 bit_size: 1 - name: TIM17SECF description: TIM17SECF bit_offset: 18 bit_size: 1 - name: SAI1SECF description: SAI1SECF bit_offset: 21 bit_size: 1 - name: SAI2SECF description: SAI2SECF bit_offset: 22 bit_size: 1 - name: DFSDM1SECF description: DFSDM1SECF bit_offset: 24 bit_size: 1 fieldset/APB2SMENR: description: APB2SMENR fields: - name: SYSCFGSMEN description: SYSCFG clocks enable during Sleep and Stop modes bit_offset: 0 bit_size: 1 - name: TIM1SMEN description: TIM1 timer clocks enable during Sleep and Stop modes bit_offset: 11 bit_size: 1 - name: SPI1SMEN description: SPI1 clocks enable during Sleep and Stop modes bit_offset: 12 bit_size: 1 - name: TIM8SMEN description: TIM8 timer clocks enable during Sleep and Stop modes bit_offset: 13 bit_size: 1 - name: USART1SMEN description: USART1clocks enable during Sleep and Stop modes bit_offset: 14 bit_size: 1 - name: TIM15SMEN description: TIM15 timer clocks enable during Sleep and Stop modes bit_offset: 16 bit_size: 1 - name: TIM16SMEN description: TIM16 timer clocks enable during Sleep and Stop modes bit_offset: 17 bit_size: 1 - name: TIM17SMEN description: TIM17 timer clocks enable during Sleep and Stop modes bit_offset: 18 bit_size: 1 - name: SAI1SMEN description: SAI1 clocks enable during Sleep and Stop modes bit_offset: 21 bit_size: 1 - name: SAI2SMEN description: SAI2 clocks enable during Sleep and Stop modes bit_offset: 22 bit_size: 1 - name: DFSDM1SMEN description: DFSDM timer clocks enable during Sleep and Stop modes bit_offset: 24 bit_size: 1 fieldset/BDCR: description: BDCR fields: - name: LSEON description: LSE oscillator enable bit_offset: 0 bit_size: 1 - name: LSERDY description: LSE oscillator ready bit_offset: 1 bit_size: 1 - name: LSEBYP description: LSE oscillator bypass bit_offset: 2 bit_size: 1 - name: LSEDRV description: SE oscillator drive capability bit_offset: 3 bit_size: 2 enum: LSEDRV - name: LSECSSON description: LSECSSON bit_offset: 5 bit_size: 1 - name: LSECSSD description: LSECSSD bit_offset: 6 bit_size: 1 - name: LSESYSEN description: LSESYSEN bit_offset: 7 bit_size: 1 - name: RTCSEL description: RTC clock source selection bit_offset: 8 bit_size: 2 enum: RTCSEL - name: LSESYSRDY description: LSESYSRDY bit_offset: 11 bit_size: 1 - name: RTCEN description: RTC clock enable bit_offset: 15 bit_size: 1 - name: BDRST description: Backup domain software reset bit_offset: 16 bit_size: 1 - name: LSCOEN description: Low speed clock output enable bit_offset: 24 bit_size: 1 - name: LSCOSEL description: Low speed clock output selection bit_offset: 25 bit_size: 1 enum: LSCOSEL fieldset/CCIPR: description: CCIPR fields: - name: USART1SEL description: USART1 clock source selection bit_offset: 0 bit_size: 2 - name: USART2SEL description: USART2 clock source selection bit_offset: 2 bit_size: 2 - name: USART3SEL description: USART3 clock source selection bit_offset: 4 bit_size: 2 - name: UART4SEL description: UART4 clock source selection bit_offset: 6 bit_size: 2 - name: UART5SEL description: UART5 clock source selection bit_offset: 8 bit_size: 2 - name: LPUART1SEL description: LPUART1 clock source selection bit_offset: 10 bit_size: 2 - name: I2C1SEL description: I2C1 clock source selection bit_offset: 12 bit_size: 2 - name: I2C2SEL description: I2C2 clock source selection bit_offset: 14 bit_size: 2 - name: I2C3SEL description: I2C3 clock source selection bit_offset: 16 bit_size: 2 - name: LPTIM1SEL description: Low power timer 1 clock source selection bit_offset: 18 bit_size: 2 - name: LPTIM2SEL description: Low power timer 2 clock source selection bit_offset: 20 bit_size: 2 - name: LPTIM3SEL description: Low-power timer 3 clock source selection bit_offset: 22 bit_size: 2 - name: FDCANSEL description: FDCAN clock source selection bit_offset: 24 bit_size: 2 enum: FDCANSEL - name: CLK48SEL description: 48 MHz clock source selection bit_offset: 26 bit_size: 2 enum: CLK48SEL - name: ADCSEL description: ADCs clock source selection bit_offset: 28 bit_size: 2 enum: ADCSEL fieldset/CCIPR2: description: Peripherals independent clock configuration register fields: - name: I2C4SEL description: I2C4 clock source selection bit_offset: 0 bit_size: 2 - name: DFSDMSEL description: Digital filter for sigma delta modulator kernel clock source selection bit_offset: 2 bit_size: 1 - name: ADFSDMSEL description: Digital filter for sigma delta modulator audio clock source selection bit_offset: 3 bit_size: 2 - name: SAI1SEL description: SAI1 clock source selection bit_offset: 5 bit_size: 3 - name: SAI2SEL description: SAI2 clock source selection bit_offset: 8 bit_size: 3 - name: SDMMCSEL description: SDMMC clock selection bit_offset: 14 bit_size: 1 - name: OCTOSPISEL description: Octospi clock source selection bit_offset: 20 bit_size: 2 fieldset/CFGR: description: Clock configuration register fields: - name: SW description: System clock switch bit_offset: 0 bit_size: 2 enum: SW - name: SWS description: System clock switch status bit_offset: 2 bit_size: 2 enum: SW - name: HPRE description: AHB prescaler bit_offset: 4 bit_size: 4 enum: HPRE - name: PPRE1 description: APB low-speed prescaler (APB1) bit_offset: 8 bit_size: 3 enum: PPRE - name: PPRE2 description: APB high-speed prescaler (APB2) bit_offset: 11 bit_size: 3 enum: PPRE - name: STOPWUCK description: Wakeup from Stop and CSS backup clock selection bit_offset: 15 bit_size: 1 enum: STOPWUCK - name: MCOSEL description: Microcontroller clock output selection bit_offset: 24 bit_size: 4 enum: MCOSEL - name: MCOPRE description: Microcontroller clock output prescaler bit_offset: 28 bit_size: 3 enum: MCOPRE fieldset/CICR: description: Clock interrupt clear register fields: - name: LSIRDYC description: LSI ready interrupt clear bit_offset: 0 bit_size: 1 - name: LSERDYC description: LSE ready interrupt clear bit_offset: 1 bit_size: 1 - name: MSIRDYC description: MSI ready interrupt clear bit_offset: 2 bit_size: 1 - name: HSIRDYC description: HSI ready interrupt clear bit_offset: 3 bit_size: 1 - name: HSERDYC description: HSE ready interrupt clear bit_offset: 4 bit_size: 1 - name: PLLRDYC description: PLL ready interrupt clear bit_offset: 5 bit_size: 1 - name: PLLSAI1RDYC description: PLLSAI1 ready interrupt clear bit_offset: 6 bit_size: 1 - name: PLLSAI2RDYC description: PLLSAI2 ready interrupt clear bit_offset: 7 bit_size: 1 - name: CSSC description: Clock security system interrupt clear bit_offset: 8 bit_size: 1 - name: LSECSSC description: LSE Clock security system interrupt clear bit_offset: 9 bit_size: 1 - name: HSI48RDYC description: HSI48 oscillator ready interrupt clear bit_offset: 10 bit_size: 1 fieldset/CIER: description: Clock interrupt enable register fields: - name: LSIRDYIE description: LSI ready interrupt enable bit_offset: 0 bit_size: 1 - name: LSERDYIE description: LSE ready interrupt enable bit_offset: 1 bit_size: 1 - name: MSIRDYIE description: MSI ready interrupt enable bit_offset: 2 bit_size: 1 - name: HSIRDYIE description: HSI ready interrupt enable bit_offset: 3 bit_size: 1 - name: HSERDYIE description: HSE ready interrupt enable bit_offset: 4 bit_size: 1 - name: PLLRDYIE description: PLL ready interrupt enable bit_offset: 5 bit_size: 1 - name: PLLSAI1RDYIE description: PLLSAI1 ready interrupt enable bit_offset: 6 bit_size: 1 - name: PLLSAI2RDYIE description: PLLSAI2 ready interrupt enable bit_offset: 7 bit_size: 1 - name: LSECSSIE description: LSE clock security system interrupt enable bit_offset: 9 bit_size: 1 - name: HSI48RDYIE description: HSI48 ready interrupt enable bit_offset: 10 bit_size: 1 fieldset/CIFR: description: Clock interrupt flag register fields: - name: LSIRDYF description: LSI ready interrupt flag bit_offset: 0 bit_size: 1 - name: LSERDYF description: LSE ready interrupt flag bit_offset: 1 bit_size: 1 - name: MSIRDYF description: MSI ready interrupt flag bit_offset: 2 bit_size: 1 - name: HSIRDYF description: HSI ready interrupt flag bit_offset: 3 bit_size: 1 - name: HSERDYF description: HSE ready interrupt flag bit_offset: 4 bit_size: 1 - name: PLLRDYF description: PLL ready interrupt flag bit_offset: 5 bit_size: 1 - name: PLLSAI1RDYF description: PLLSAI1 ready interrupt flag bit_offset: 6 bit_size: 1 - name: PLLSAI2RDYF description: PLLSAI2 ready interrupt flag bit_offset: 7 bit_size: 1 - name: CSSF description: Clock security system interrupt flag bit_offset: 8 bit_size: 1 - name: LSECSSF description: LSE Clock security system interrupt flag bit_offset: 9 bit_size: 1 - name: HSI48RDYF description: HSI48 ready interrupt flag bit_offset: 10 bit_size: 1 fieldset/CR: description: Clock control register fields: - name: MSION description: MSI clock enable bit_offset: 0 bit_size: 1 - name: MSIRDY description: MSI clock ready flag bit_offset: 1 bit_size: 1 - name: MSIPLLEN description: MSI clock PLL enable bit_offset: 2 bit_size: 1 - name: MSIRGSEL description: MSI clock range selection bit_offset: 3 bit_size: 1 enum: MSIRGSEL - name: MSIRANGE description: MSI clock ranges bit_offset: 4 bit_size: 4 enum: MSIRANGE - name: HSION description: HSI clock enable bit_offset: 8 bit_size: 1 - name: HSIKERON description: HSI always enable for peripheral kernels bit_offset: 9 bit_size: 1 - name: HSIRDY description: HSI clock ready flag bit_offset: 10 bit_size: 1 - name: HSIASFS description: HSI automatic start from Stop bit_offset: 11 bit_size: 1 - name: HSEON description: HSE clock enable bit_offset: 16 bit_size: 1 - name: HSERDY description: HSE clock ready flag bit_offset: 17 bit_size: 1 - name: HSEBYP description: HSE crystal oscillator bypass bit_offset: 18 bit_size: 1 - name: CSSON description: Clock security system enable bit_offset: 19 bit_size: 1 - name: PLLON description: Main PLL enable bit_offset: 24 bit_size: 1 - name: PLLRDY description: Main PLL clock ready flag bit_offset: 25 bit_size: 1 - name: PLLSAI1ON description: SAI1 PLL enable bit_offset: 26 bit_size: 1 - name: PLLSAI1RDY description: SAI1 PLL clock ready flag bit_offset: 27 bit_size: 1 - name: PLLSAI2ON description: SAI2 PLL enable bit_offset: 28 bit_size: 1 - name: PLLSAI2RDY description: SAI2 PLL clock ready flag bit_offset: 29 bit_size: 1 - name: PRIV description: PRIV bit_offset: 31 bit_size: 1 fieldset/CRRCR: description: Clock recovery RC register fields: - name: HSI48ON description: HSI48 clock enable bit_offset: 0 bit_size: 1 - name: HSI48RDY description: HSI48 clock ready flag bit_offset: 1 bit_size: 1 - name: HSI48CAL description: HSI48 clock calibration bit_offset: 7 bit_size: 9 fieldset/CSR: description: CSR fields: - name: LSION description: LSI oscillator enable bit_offset: 0 bit_size: 1 - name: LSIRDY description: LSI oscillator ready bit_offset: 1 bit_size: 1 - name: LSIPREDIV description: LSIPREDIV bit_offset: 4 bit_size: 1 - name: MSISRANGE description: SI range after Standby mode bit_offset: 8 bit_size: 4 - name: RMVF description: Remove reset flag bit_offset: 23 bit_size: 1 - name: OBLRSTF description: Option byte loader reset flag bit_offset: 25 bit_size: 1 - name: PINRSTF description: Pin reset flag bit_offset: 26 bit_size: 1 - name: BORRSTF description: BOR flag bit_offset: 27 bit_size: 1 - name: SFTRSTF description: Software reset flag bit_offset: 28 bit_size: 1 - name: IWDGRSTF description: Independent window watchdog reset flag bit_offset: 29 bit_size: 1 - name: WWDGRSTF description: Window watchdog reset flag bit_offset: 30 bit_size: 1 - name: LPWRRSTF description: Low-power reset flag bit_offset: 31 bit_size: 1 fieldset/ICSCR: description: Internal clock sources calibration register fields: - name: MSICAL description: MSI clock calibration bit_offset: 0 bit_size: 8 - name: MSITRIM description: MSI clock trimming bit_offset: 8 bit_size: 8 - name: HSICAL description: HSI clock calibration bit_offset: 16 bit_size: 8 - name: HSITRIM description: HSI clock trimming bit_offset: 24 bit_size: 7 fieldset/PLLCFGR: description: PLL configuration register fields: - name: PLLSRC description: PLL clock source bit_offset: 0 bit_size: 2 enum: PLLSRC - name: PLLM description: Division factor for the PLL input clock bit_offset: 4 bit_size: 4 enum: PLLM - name: PLLN description: PLL multiplication factor for VCO bit_offset: 8 bit_size: 7 enum: PLLN - name: PLLPEN description: PLL PLLSAI3CLK output enable bit_offset: 16 bit_size: 1 - name: PLLPBIT description: PLL division factor for PLLSAI3CLK (SAI1 and SAI2 clock) bit_offset: 17 bit_size: 1 enum: PLLPBIT - name: PLLQEN description: PLL PLLUSB1CLK output enable bit_offset: 20 bit_size: 1 - name: PLLQ description: PLL division factor for PLLUSB1CLK(48 MHz clock) bit_offset: 21 bit_size: 2 enum: PLLQ - name: PLLREN description: PLL PLLCLK output enable bit_offset: 24 bit_size: 1 - name: PLLR description: PLL division factor for PLLCLK (system clock) bit_offset: 25 bit_size: 2 enum: PLLR - name: PLLP description: PLL division factor for PLLSAI2CLK bit_offset: 27 bit_size: 5 enum: PLLP fieldset/SECCFGR: description: RCC secure configuration register fields: - name: HSISEC description: HSISEC bit_offset: 0 bit_size: 1 - name: HSESEC description: HSESEC bit_offset: 1 bit_size: 1 - name: MSISEC description: MSISEC bit_offset: 2 bit_size: 1 - name: LSISEC description: LSISEC bit_offset: 3 bit_size: 1 - name: LSESEC description: LSESEC bit_offset: 4 bit_size: 1 - name: SYSCLKSEC description: SYSCLKSEC bit_offset: 5 bit_size: 1 - name: PRESCSEC description: PRESCSEC bit_offset: 6 bit_size: 1 - name: PLLSEC description: PLLSEC bit_offset: 7 bit_size: 1 - name: PLLSAI1SEC description: PLLSAI1SEC bit_offset: 8 bit_size: 1 - name: PLLSAI2SEC description: PLLSAI2SEC bit_offset: 9 bit_size: 1 - name: CLK48SEC description: CLK48SEC bit_offset: 10 bit_size: 1 - name: HSI48SEC description: HSI48SEC bit_offset: 11 bit_size: 1 - name: RMVFSEC description: RMVFSEC bit_offset: 12 bit_size: 1 fieldset/SECSR: description: RCC secure status register fields: - name: HSISECF description: HSISECF bit_offset: 0 bit_size: 1 - name: HSESECF description: HSESECF bit_offset: 1 bit_size: 1 - name: MSISECF description: MSISECF bit_offset: 2 bit_size: 1 - name: LSISECF description: LSISECF bit_offset: 3 bit_size: 1 - name: LSESECF description: LSESECF bit_offset: 4 bit_size: 1 - name: SYSCLKSECF description: SYSCLKSECF bit_offset: 5 bit_size: 1 - name: PRESCSECF description: PRESCSECF bit_offset: 6 bit_size: 1 - name: PLLSECF description: PLLSECF bit_offset: 7 bit_size: 1 - name: PLLSAI1SECF description: PLLSAI1SECF bit_offset: 8 bit_size: 1 - name: PLLSAI2SECF description: PLLSAI2SECF bit_offset: 9 bit_size: 1 - name: CLK48SECF description: CLK48SECF bit_offset: 10 bit_size: 1 - name: HSI48SECF description: HSI48SECF bit_offset: 11 bit_size: 1 - name: RMVFSECF description: RMVFSECF bit_offset: 12 bit_size: 1 enum/ADCSEL: bit_size: 2 variants: - name: DISABLE description: No clock selected value: 0 - name: PLLSAI1_R description: PLLADC1CLK clock selected value: 1 - name: SYS description: SYSCLK clock selected value: 3 enum/CLK48SEL: bit_size: 2 variants: - name: HSI48 description: HSI48 clock selected value: 0 - name: PLLSAI1_Q description: PLLSAI1_Q aka PLL48M1CLK clock selected value: 1 - name: PLL1_Q description: PLL_Q aka PLL48M2CLK clock selected value: 2 - name: MSI description: MSI clock selected value: 3 enum/FDCANSEL: bit_size: 2 variants: - name: HSE description: HSE clock selected value: 0 - name: PLL1_Q description: PLL "Q" clock selected value: 1 - name: PLLSAI1_P description: PLLSAI "P" clock selected value: 2 enum/HPRE: bit_size: 4 variants: - name: Div1 description: SYSCLK not divided value: 0 - name: Div2 description: SYSCLK divided by 2 value: 8 - name: Div4 description: SYSCLK divided by 4 value: 9 - name: Div8 description: SYSCLK divided by 8 value: 10 - name: Div16 description: SYSCLK divided by 16 value: 11 - name: Div64 description: SYSCLK divided by 64 value: 12 - name: Div128 description: SYSCLK divided by 128 value: 13 - name: Div256 description: SYSCLK divided by 256 value: 14 - name: Div512 description: SYSCLK divided by 512 value: 15 enum/LSCOSEL: bit_size: 1 variants: - name: LSI description: LSI clock selected" value: 0 - name: LSE description: LSE clock selected value: 1 enum/LSEDRV: bit_size: 2 variants: - name: Low description: Low driving capability value: 0 - name: MediumLow description: Medium low driving capability value: 1 - name: MediumHigh description: Medium high driving capability value: 2 - name: High description: High driving capability value: 3 enum/MCOPRE: bit_size: 3 variants: - name: Div1 description: MCO divided by 1 value: 0 - name: Div2 description: MCO divided by 2 value: 1 - name: Div4 description: MCO divided by 4 value: 2 - name: Div8 description: MCO divided by 8 value: 3 - name: Div16 description: MCO divided by 16 value: 4 enum/MCOSEL: bit_size: 4 variants: - name: DISABLE description: MCO output disabled, no clock on MCO value: 0 - name: SYS description: SYSCLK system clock selected value: 1 - name: MSI description: MSI clock selected value: 2 - name: HSI description: HSI clock selected value: 3 - name: HSE description: HSE clock selected value: 4 - name: PLL description: Main PLL clock selected value: 5 - name: LSI description: LSI clock selected value: 6 - name: LSE description: LSE clock selected value: 7 - name: HSI48 description: Internal HSI48 clock selected value: 8 enum/MSIRANGE: bit_size: 4 variants: - name: Range100K description: range 0 around 100 kHz value: 0 - name: Range200K description: range 1 around 200 kHz value: 1 - name: Range400K description: range 2 around 400 kHz value: 2 - name: Range800K description: range 3 around 800 kHz value: 3 - name: Range1M description: range 4 around 1 MHz value: 4 - name: Range2M description: range 5 around 2 MHz value: 5 - name: Range4M description: range 6 around 4 MHz value: 6 - name: Range8M description: range 7 around 8 MHz value: 7 - name: Range16M description: range 8 around 16 MHz value: 8 - name: Range24M description: range 9 around 24 MHz value: 9 - name: Range32M description: range 10 around 32 MHz value: 10 - name: Range48M description: range 11 around 48 MHz value: 11 enum/MSIRGSEL: bit_size: 1 variants: - name: CSR description: MSI Range is provided by MSISRANGE[3:0] in RCC_CSR register value: 0 - name: CR description: MSI Range is provided by MSIRANGE[3:0] in the RCC_CR register value: 1 enum/PLLM: bit_size: 4 variants: - name: Div1 value: 0 - name: Div2 value: 1 - name: Div3 value: 2 - name: Div4 value: 3 - name: Div5 value: 4 - name: Div6 value: 5 - name: Div7 value: 6 - name: Div8 value: 7 - name: Div9 value: 8 - name: Div10 value: 9 - name: Div11 value: 10 - name: Div12 value: 11 - name: Div13 value: 12 - name: Div14 value: 13 - name: Div15 value: 14 - name: Div16 value: 15 enum/PLLN: bit_size: 7 variants: - name: Mul8 value: 8 - name: Mul9 value: 9 - name: Mul10 value: 10 - name: Mul11 value: 11 - name: Mul12 value: 12 - name: Mul13 value: 13 - name: Mul14 value: 14 - name: Mul15 value: 15 - name: Mul16 value: 16 - name: Mul17 value: 17 - name: Mul18 value: 18 - name: Mul19 value: 19 - name: Mul20 value: 20 - name: Mul21 value: 21 - name: Mul22 value: 22 - name: Mul23 value: 23 - name: Mul24 value: 24 - name: Mul25 value: 25 - name: Mul26 value: 26 - name: Mul27 value: 27 - name: Mul28 value: 28 - name: Mul29 value: 29 - name: Mul30 value: 30 - name: Mul31 value: 31 - name: Mul32 value: 32 - name: Mul33 value: 33 - name: Mul34 value: 34 - name: Mul35 value: 35 - name: Mul36 value: 36 - name: Mul37 value: 37 - name: Mul38 value: 38 - name: Mul39 value: 39 - name: Mul40 value: 40 - name: Mul41 value: 41 - name: Mul42 value: 42 - name: Mul43 value: 43 - name: Mul44 value: 44 - name: Mul45 value: 45 - name: Mul46 value: 46 - name: Mul47 value: 47 - name: Mul48 value: 48 - name: Mul49 value: 49 - name: Mul50 value: 50 - name: Mul51 value: 51 - name: Mul52 value: 52 - name: Mul53 value: 53 - name: Mul54 value: 54 - name: Mul55 value: 55 - name: Mul56 value: 56 - name: Mul57 value: 57 - name: Mul58 value: 58 - name: Mul59 value: 59 - name: Mul60 value: 60 - name: Mul61 value: 61 - name: Mul62 value: 62 - name: Mul63 value: 63 - name: Mul64 value: 64 - name: Mul65 value: 65 - name: Mul66 value: 66 - name: Mul67 value: 67 - name: Mul68 value: 68 - name: Mul69 value: 69 - name: Mul70 value: 70 - name: Mul71 value: 71 - name: Mul72 value: 72 - name: Mul73 value: 73 - name: Mul74 value: 74 - name: Mul75 value: 75 - name: Mul76 value: 76 - name: Mul77 value: 77 - name: Mul78 value: 78 - name: Mul79 value: 79 - name: Mul80 value: 80 - name: Mul81 value: 81 - name: Mul82 value: 82 - name: Mul83 value: 83 - name: Mul84 value: 84 - name: Mul85 value: 85 - name: Mul86 value: 86 - name: Mul87 value: 87 - name: Mul88 value: 88 - name: Mul89 value: 89 - name: Mul90 value: 90 - name: Mul91 value: 91 - name: Mul92 value: 92 - name: Mul93 value: 93 - name: Mul94 value: 94 - name: Mul95 value: 95 - name: Mul96 value: 96 - name: Mul97 value: 97 - name: Mul98 value: 98 - name: Mul99 value: 99 - name: Mul100 value: 100 - name: Mul101 value: 101 - name: Mul102 value: 102 - name: Mul103 value: 103 - name: Mul104 value: 104 - name: Mul105 value: 105 - name: Mul106 value: 106 - name: Mul107 value: 107 - name: Mul108 value: 108 - name: Mul109 value: 109 - name: Mul110 value: 110 - name: Mul111 value: 111 - name: Mul112 value: 112 - name: Mul113 value: 113 - name: Mul114 value: 114 - name: Mul115 value: 115 - name: Mul116 value: 116 - name: Mul117 value: 117 - name: Mul118 value: 118 - name: Mul119 value: 119 - name: Mul120 value: 120 - name: Mul121 value: 121 - name: Mul122 value: 122 - name: Mul123 value: 123 - name: Mul124 value: 124 - name: Mul125 value: 125 - name: Mul126 value: 126 - name: Mul127 value: 127 enum/PLLP: bit_size: 5 variants: - name: Div2 value: 2 - name: Div3 value: 3 - name: Div4 value: 4 - name: Div5 value: 5 - name: Div6 value: 6 - name: Div7 value: 7 - name: Div8 value: 8 - name: Div9 value: 9 - name: Div10 value: 10 - name: Div11 value: 11 - name: Div12 value: 12 - name: Div13 value: 13 - name: Div14 value: 14 - name: Div15 value: 15 - name: Div16 value: 16 - name: Div17 value: 17 - name: Div18 value: 18 - name: Div19 value: 19 - name: Div20 value: 20 - name: Div21 value: 21 - name: Div22 value: 22 - name: Div23 value: 23 - name: Div24 value: 24 - name: Div25 value: 25 - name: Div26 value: 26 - name: Div27 value: 27 - name: Div28 value: 28 - name: Div29 value: 29 - name: Div30 value: 30 - name: Div31 value: 31 enum/PLLPBIT: bit_size: 1 variants: - name: Div7 value: 0 - name: Div17 value: 1 enum/PLLQ: bit_size: 2 variants: - name: Div2 value: 0 - name: Div4 value: 1 - name: Div6 value: 2 - name: Div8 value: 3 enum/PLLR: bit_size: 2 variants: - name: Div2 value: 0 - name: Div4 value: 1 - name: Div6 value: 2 - name: Div8 value: 3 enum/PLLSRC: bit_size: 2 variants: - name: DISABLE description: No clock sent to PLL value: 0 - name: MSI description: MSI selected as PLL input clock value: 1 - name: HSI description: HSI selected as PLL input clock value: 2 - name: HSE description: HSE selected as PLL input clock value: 3 enum/PPRE: bit_size: 3 variants: - name: Div1 description: HCLK not divided value: 0 - name: Div2 description: HCLK divided by 2 value: 4 - name: Div4 description: HCLK divided by 4 value: 5 - name: Div8 description: HCLK divided by 8 value: 6 - name: Div16 description: HCLK divided by 16 value: 7 enum/RTCSEL: bit_size: 2 variants: - name: DISABLE description: No clock value: 0 - name: LSE description: LSE oscillator clock used as RTC clock value: 1 - name: LSI description: LSI oscillator clock used as RTC clock value: 2 - name: HSE description: HSE oscillator clock divided by a prescaler used as RTC clock value: 3 enum/STOPWUCK: bit_size: 1 variants: - name: MSI description: MSI oscillator selected as wake-up from Stop clock and CSS backup clock value: 0 - name: HSI description: HSI oscillator selected as wake-up from stop clock and CSS backup clock value: 1 enum/SW: bit_size: 2 variants: - name: MSI description: MSI selected as system clock value: 0 - name: HSI description: HSI selected as system clock value: 1 - name: HSE description: HSE selected as system clock value: 2 - name: PLL1_R description: PLL selected as system clock value: 3