--- block/ADC: description: Analog to Digital Converter items: - name: ISR description: interrupt and status register byte_offset: 0 fieldset: ISR - name: IER description: interrupt enable register byte_offset: 4 fieldset: IER - name: CR description: control register byte_offset: 8 fieldset: CR - name: CFGR description: configuration register 1 byte_offset: 12 fieldset: CFGR - name: CFGR2 description: configuration register 2 byte_offset: 16 fieldset: CFGR2 - name: SMPR description: sampling time register 1-2 byte_offset: 20 array: len: 2 stride: 4 fieldset: SMPR - name: PCSEL description: pre channel selection register byte_offset: 28 fieldset: PCSEL - name: LTR1 description: analog watchdog 1 threshold register byte_offset: 32 fieldset: LTR1 - name: HTR1 description: analog watchdog 2 threshold register byte_offset: 36 fieldset: HTR1 - name: SQR1 description: group regular sequencer ranks register 1 byte_offset: 48 fieldset: SQR1 - name: SQR2 description: group regular sequencer ranks register 2 byte_offset: 52 fieldset: SQR2 - name: SQR3 description: group regular sequencer ranks register 3 byte_offset: 56 fieldset: SQR3 - name: SQR4 description: group regular sequencer ranks register 4 byte_offset: 60 fieldset: SQR4 - name: DR description: group regular conversion data register byte_offset: 64 access: Read fieldset: DR - name: JSQR description: group injected sequencer register byte_offset: 76 fieldset: JSQR - name: OFR description: offset number 1-4 register byte_offset: 96 array: len: 4 stride: 4 fieldset: OFR - name: JDR description: group injected sequencer rank 1-4 register byte_offset: 128 array: len: 4 stride: 4 access: Read fieldset: JDR - name: AWD2CR description: analog watchdog 2 configuration register byte_offset: 160 fieldset: AWD2CR - name: AWD3CR description: analog watchdog 3 configuration register byte_offset: 164 fieldset: AWD3CR - name: LTR2 description: watchdog lower threshold register 2 byte_offset: 176 fieldset: LTR2 - name: HTR2 description: watchdog higher threshold register 2 byte_offset: 180 fieldset: HTR2 - name: LTR3 description: watchdog lower threshold register 3 byte_offset: 184 fieldset: LTR3 - name: HTR3 description: watchdog higher threshold register 3 byte_offset: 188 fieldset: HTR3 - name: DIFSEL description: channel differential or single-ended mode selection register byte_offset: 192 fieldset: DIFSEL - name: CALFACT description: calibration factors register byte_offset: 196 fieldset: CALFACT - name: CALFACT2 description: Calibration Factor register 2 byte_offset: 200 fieldset: CALFACT2 fieldset/AWD2CR: description: analog watchdog 2 configuration register fields: - name: AWD2CH description: analog watchdog 2 monitored channel selection bit_offset: 0 bit_size: 1 array: len: 20 stride: 1 fieldset/AWD3CR: description: analog watchdog 3 configuration register fields: - name: AWD3CH description: analog watchdog 3 monitored channel selection bit_offset: 1 bit_size: 1 array: len: 20 stride: 1 fieldset/CALFACT: description: calibration factors register fields: - name: CALFACT_S description: calibration factor in single-ended mode bit_offset: 0 bit_size: 11 - name: CALFACT_D description: calibration factor in differential mode bit_offset: 16 bit_size: 11 fieldset/CALFACT2: description: Calibration Factor register 2 fields: - name: LINCALFACT description: Linearity Calibration Factor bit_offset: 0 bit_size: 30 fieldset/CFGR: description: configuration register 1 fields: - name: DMNGT description: DMA transfer enable bit_offset: 0 bit_size: 2 enum: DMNGT - name: RES description: data resolution bit_offset: 2 bit_size: 3 enum: RES - name: EXTSEL description: group regular external trigger source bit_offset: 5 bit_size: 5 enum: EXTSEL - name: EXTEN description: group regular external trigger polarity bit_offset: 10 bit_size: 2 enum: EXTEN - name: OVRMOD description: group regular overrun configuration bit_offset: 12 bit_size: 1 enum: OVRMOD - name: CONT description: group regular continuous conversion mode bit_offset: 13 bit_size: 1 - name: AUTDLY description: low power auto wait bit_offset: 14 bit_size: 1 - name: DISCEN description: group regular sequencer discontinuous mode bit_offset: 16 bit_size: 1 - name: DISCNUM description: group regular sequencer discontinuous number of ranks bit_offset: 17 bit_size: 3 - name: JDISCEN description: group injected sequencer discontinuous mode bit_offset: 20 bit_size: 1 - name: JQM description: group injected contexts queue mode bit_offset: 21 bit_size: 1 enum: JQM - name: AWD1SGL description: analog watchdog 1 monitoring a single channel or all channels bit_offset: 22 bit_size: 1 enum: AWD1SGL - name: AWD1EN description: analog watchdog 1 enable on scope group regular bit_offset: 23 bit_size: 1 - name: JAWD1EN description: analog watchdog 1 enable on scope group injected bit_offset: 24 bit_size: 1 - name: JAUTO description: group injected automatic trigger mode bit_offset: 25 bit_size: 1 - name: AWD1CH description: analog watchdog 1 monitored channel selection bit_offset: 26 bit_size: 5 - name: JQDIS description: group injected contexts queue disable bit_offset: 31 bit_size: 1 fieldset/CFGR2: description: configuration register 2 fields: - name: ROVSE description: oversampler enable on scope group regular bit_offset: 0 bit_size: 1 - name: JOVSE description: oversampler enable on scope group injected bit_offset: 1 bit_size: 1 - name: OVSS description: oversampling shift bit_offset: 5 bit_size: 4 - name: TROVS description: oversampling discontinuous mode (triggered mode) for group regular bit_offset: 9 bit_size: 1 enum: TROVS - name: ROVSM description: Regular Oversampling mode bit_offset: 10 bit_size: 1 enum: ROVSM - name: RSHIFT1 description: Right-shift data after Offset 1 correction bit_offset: 11 bit_size: 1 - name: RSHIFT2 description: Right-shift data after Offset 2 correction bit_offset: 12 bit_size: 1 - name: RSHIFT3 description: Right-shift data after Offset 3 correction bit_offset: 13 bit_size: 1 - name: RSHIFT4 description: Right-shift data after Offset 4 correction bit_offset: 14 bit_size: 1 - name: OSVR description: Oversampling ratio bit_offset: 16 bit_size: 10 - name: LSHIFT description: Left shift factor bit_offset: 28 bit_size: 4 fieldset/CR: description: control register fields: - name: ADEN description: enable bit_offset: 0 bit_size: 1 enum_write: ADENW - name: ADDIS description: disable bit_offset: 1 bit_size: 1 enum_write: ADDISW - name: ADSTART description: group regular conversion start bit_offset: 2 bit_size: 1 - name: JADSTART description: group injected conversion start bit_offset: 3 bit_size: 1 - name: ADSTP description: group regular conversion stop bit_offset: 4 bit_size: 1 enum: ADSTP - name: JADSTP description: group injected conversion stop bit_offset: 5 bit_size: 1 enum: ADSTP - name: BOOST description: Boost mode control bit_offset: 8 bit_size: 2 enum: BOOST - name: ADCALLIN description: Linearity calibration bit_offset: 16 bit_size: 1 - name: LINCALRDYW1 description: Linearity calibration ready Word 1 bit_offset: 22 bit_size: 1 - name: LINCALRDYW2 description: Linearity calibration ready Word 2 bit_offset: 23 bit_size: 1 - name: LINCALRDYW3 description: Linearity calibration ready Word 3 bit_offset: 24 bit_size: 1 - name: LINCALRDYW4 description: Linearity calibration ready Word 4 bit_offset: 25 bit_size: 1 - name: LINCALRDYW5 description: Linearity calibration ready Word 5 bit_offset: 26 bit_size: 1 - name: LINCALRDYW6 description: Linearity calibration ready Word 6 bit_offset: 27 bit_size: 1 - name: ADVREGEN description: voltage regulator enable bit_offset: 28 bit_size: 1 - name: DEEPPWD description: deep power down enable bit_offset: 29 bit_size: 1 - name: ADCALDIF description: differential mode for calibration bit_offset: 30 bit_size: 1 enum: ADCALDIF - name: ADCAL description: calibration bit_offset: 31 bit_size: 1 fieldset/DIFSEL: description: channel differential or single-ended mode selection register fields: - name: DIFSEL description: channel differential or single-ended mode for channel bit_offset: 0 bit_size: 1 array: len: 20 stride: 1 enum: DIFSEL fieldset/DR: description: group regular conversion data register fields: - name: RDATA description: group regular conversion data bit_offset: 0 bit_size: 16 fieldset/HTR1: description: analog watchdog 2 threshold register fields: - name: HTR1 description: analog watchdog 2 threshold low bit_offset: 0 bit_size: 26 fieldset/HTR2: description: watchdog higher threshold register 2 fields: - name: HTR2 description: Analog watchdog 2 higher threshold bit_offset: 0 bit_size: 26 fieldset/HTR3: description: watchdog higher threshold register 3 fields: - name: HTR3 description: Analog watchdog 3 higher threshold bit_offset: 0 bit_size: 26 fieldset/IER: description: interrupt enable register fields: - name: ADRDYIE description: ready interrupt bit_offset: 0 bit_size: 1 - name: EOSMPIE description: group regular end of sampling interrupt bit_offset: 1 bit_size: 1 - name: EOCIE description: group regular end of unitary conversion interrupt bit_offset: 2 bit_size: 1 - name: EOSIE description: group regular end of sequence conversions interrupt bit_offset: 3 bit_size: 1 - name: OVRIE description: group regular overrun interrupt bit_offset: 4 bit_size: 1 - name: JEOCIE description: group injected end of unitary conversion interrupt bit_offset: 5 bit_size: 1 - name: JEOSIE description: group injected end of sequence conversions interrupt bit_offset: 6 bit_size: 1 - name: AWD1IE description: analog watchdog 1 interrupt bit_offset: 7 bit_size: 1 - name: AWD2IE description: analog watchdog 2 interrupt bit_offset: 8 bit_size: 1 - name: AWD3IE description: analog watchdog 3 interrupt bit_offset: 9 bit_size: 1 - name: JQOVFIE description: group injected contexts queue overflow interrupt bit_offset: 10 bit_size: 1 fieldset/ISR: description: interrupt and status register fields: - name: ADRDY description: ready flag bit_offset: 0 bit_size: 1 - name: EOSMP description: group regular end of sampling flag bit_offset: 1 bit_size: 1 - name: EOC description: group regular end of unitary conversion flag bit_offset: 2 bit_size: 1 - name: EOS description: group regular end of sequence conversions flag bit_offset: 3 bit_size: 1 - name: OVR description: group regular overrun flag bit_offset: 4 bit_size: 1 - name: JEOC description: group injected end of unitary conversion flag bit_offset: 5 bit_size: 1 - name: JEOS description: group injected end of sequence conversions flag bit_offset: 6 bit_size: 1 - name: AWD1 description: analog watchdog 1 flag bit_offset: 7 bit_size: 1 - name: AWD2 description: analog watchdog 2 flag bit_offset: 8 bit_size: 1 - name: AWD3 description: analog watchdog 3 flag bit_offset: 9 bit_size: 1 - name: JQOVF description: group injected contexts queue overflow flag bit_offset: 10 bit_size: 1 - name: LDORDY description: ADC LDO output voltage ready (not always available) bit_offset: 12 bit_size: 1 fieldset/JDR: description: group injected sequencer rank 1 register fields: - name: JDATA description: group injected sequencer rank 1 conversion data bit_offset: 0 bit_size: 32 fieldset/JSQR: description: group injected sequencer register fields: - name: JL description: group injected sequencer scan length bit_offset: 0 bit_size: 2 - name: JEXTSEL description: group injected external trigger source bit_offset: 2 bit_size: 5 enum: JEXTSEL - name: JEXTEN description: group injected external trigger polarity bit_offset: 7 bit_size: 2 enum: JEXTEN - name: JSQ1 description: group injected sequencer rank 1-4 bit_offset: 9 bit_size: 5 array: len: 4 stride: 6 fieldset/LTR1: description: analog watchdog 1 threshold register fields: - name: LTR1 description: analog watchdog 1 threshold low bit_offset: 0 bit_size: 26 fieldset/LTR2: description: watchdog lower threshold register 2 fields: - name: LTR2 description: Analog watchdog 2 lower threshold bit_offset: 0 bit_size: 26 fieldset/LTR3: description: watchdog lower threshold register 3 fields: - name: LTR3 description: Analog watchdog 3 lower threshold bit_offset: 0 bit_size: 26 fieldset/OFR: description: offset number x register fields: - name: OFFSET1 description: offset number x offset level bit_offset: 0 bit_size: 26 - name: OFFSET1_CH description: offset number x channel selection bit_offset: 26 bit_size: 5 - name: SSATE description: Signed saturation enable bit_offset: 31 bit_size: 1 fieldset/PCSEL: description: channel preselection register fields: - name: PCSEL description: "Channel x (VINP[i]) pre selection" bit_offset: 0 bit_size: 1 array: len: 20 stride: 1 enum: PCSEL fieldset/SMPR: description: sampling time register n fields: - name: SMP description: channel n * 10 + x sampling time bit_offset: 0 bit_size: 3 array: len: 10 stride: 3 enum: SMP fieldset/SQR1: description: group regular sequencer ranks register 1 fields: - name: L description: L3 bit_offset: 0 bit_size: 4 - name: SQ description: group regular sequencer rank 1-4 bit_offset: 6 bit_size: 5 array: len: 4 stride: 6 fieldset/SQR2: description: group regular sequencer ranks register 2 fields: - name: SQ description: group regular sequencer rank 5-9 bit_offset: 0 bit_size: 5 array: len: 5 stride: 6 fieldset/SQR3: description: group regular sequencer ranks register 3 fields: - name: SQ description: group regular sequencer rank 10-14 bit_offset: 0 bit_size: 5 array: len: 5 stride: 6 fieldset/SQR4: description: group regular sequencer ranks register 4 fields: - name: SQ description: group regular sequencer rank 15-16 bit_offset: 0 bit_size: 5 array: len: 2 stride: 6 enum/ADCALDIF: bit_size: 1 variants: - name: SingleEnded description: Calibration for single-ended mode value: 0 - name: Differential description: Calibration for differential mode value: 1 enum/ADDISW: bit_size: 1 variants: - name: Disable description: Disable conversion and go to power down mode value: 0 enum/ADENW: bit_size: 1 variants: - name: Enable description: Enable ADC value: 1 enum/ADSTP: bit_size: 1 variants: - name: Stop description: Stop conversion of channel value: 1 enum/AWD1SGL: bit_size: 1 variants: - name: All description: Analog watchdog 1 enabled on all channels value: 0 - name: Single description: Analog watchdog 1 enabled on single channel selected in AWD1CH value: 1 enum/BOOST: bit_size: 2 variants: - name: LT6_25 description: Boost mode used when clock ≤ 6.25 MHz value: 0 - name: LT12_5 description: Boost mode used when 6.25 MHz < clock ≤ 12.5 MHz value: 1 - name: LT25 description: Boost mode used when 12.5 MHz < clock ≤ 25.0 MHz value: 2 - name: LT50 description: Boost mode used when 25.0 MHz < clock ≤ 50.0 MHz value: 3 enum/DIFSEL: bit_size: 1 variants: - name: SingleEnded description: Input channel is configured in single-ended mode value: 0 - name: Differential description: Input channel is configured in differential mode value: 1 enum/DMNGT: bit_size: 2 variants: - name: DR description: Store output data in DR only value: 0 - name: DMA_OneShot description: DMA One Shot Mode selected value: 1 - name: DFSDM description: DFSDM mode selected value: 2 - name: DMA_Circular description: DMA Circular Mode selected value: 3 enum/EXTEN: bit_size: 2 variants: - name: Disabled description: Trigger detection disabled value: 0 - name: RisingEdge description: Trigger detection on the rising edge value: 1 - name: FallingEdge description: Trigger detection on the falling edge value: 2 - name: BothEdges description: Trigger detection on both the rising and falling edges value: 3 enum/EXTSEL: bit_size: 5 variants: - name: TIM1_CC1 description: Timer 1 CC1 event value: 0 - name: TIM1_CC2 description: Timer 1 CC2 event value: 1 - name: TIM1_CC3 description: Timer 1 CC3 event value: 2 - name: TIM2_CC2 description: Timer 2 CC2 event value: 3 - name: TIM3_TRGO description: Timer 3 TRGO event value: 4 - name: TIM4_CC4 description: Timer 4 CC4 event value: 5 - name: EXTI11 description: EXTI line 11 value: 6 - name: TIM8_TRGO description: Timer 8 TRGO event value: 7 - name: TIM8_TRGO2 description: Timer 8 TRGO2 event value: 8 - name: TIM1_TRGO description: Timer 1 TRGO event value: 9 - name: TIM1_TRGO2 description: Timer 1 TRGO2 event value: 10 - name: TIM2_TRGO description: Timer 2 TRGO event value: 11 - name: TIM4_TRGO description: Timer 4 TRGO event value: 12 - name: TIM6_TRGO description: Timer 6 TRGO event value: 13 - name: TIM15_TRGO description: Timer 15 TRGO event value: 14 - name: TIM3_CC4 description: Timer 3 CC4 event value: 15 - name: HRTIM1_ADCTRG1 description: HRTIM1_ADCTRG1 event value: 16 - name: HRTIM1_ADCTRG3 description: HRTIM1_ADCTRG3 event value: 17 - name: LPTIM1_OUT description: LPTIM1_OUT event value: 18 - name: LPTIM2_OUT description: LPTIM2_OUT event value: 19 - name: LPTIM3_OUT description: LPTIM3_OUT event value: 20 enum/JEXTEN: bit_size: 2 variants: - name: Disabled description: Trigger detection disabled value: 0 - name: RisingEdge description: Trigger detection on the rising edge value: 1 - name: FallingEdge description: Trigger detection on the falling edge value: 2 - name: BothEdges description: Trigger detection on both the rising and falling edges value: 3 enum/JEXTSEL: bit_size: 5 variants: - name: TIM1_TRGO description: Timer 1 TRGO event value: 0 - name: TIM1_CC4 description: Timer 1 CC4 event value: 1 - name: TIM2_TRGO description: Timer 2 TRGO event value: 2 - name: TIM2_CC1 description: Timer 2 CC1 event value: 3 - name: TIM3_CC4 description: Timer 3 CC4 event value: 4 - name: TIM4_TRGO description: Timer 4 TRGO event value: 5 - name: EXTI15 description: EXTI line 15 value: 6 - name: TIM8_CC4 description: Timer 8 CC4 event value: 7 - name: TIM1_TRGO2 description: Timer 1 TRGO2 event value: 8 - name: TIM8_TRGO description: Timer 8 TRGO event value: 9 - name: TIM8_TRGO2 description: Timer 8 TRGO2 event value: 10 - name: TIM3_CC3 description: Timer 3 CC3 event value: 11 - name: TIM3_TRGO description: Timer 3 TRGO event value: 12 - name: TIM3_CC1 description: Timer 3 CC1 event value: 13 - name: TIM6_TRGO description: Timer 6 TRGO event value: 14 - name: TIM15_TRGO description: Timer 15 TRGO event value: 15 - name: HRTIM1_ADCTRG2 description: HRTIM1_ADCTRG2 event value: 16 - name: HRTIM1_ADCTRG4 description: HRTIM1_ADCTRG4 event value: 17 - name: LPTIM1_OUT description: LPTIM1_OUT event value: 18 - name: LPTIM2_OUT description: LPTIM2_OUT event value: 19 - name: LPTIM3_OUT description: LPTIM3_OUT event value: 20 enum/JQM: bit_size: 1 variants: - name: Mode0 description: "JSQR Mode 0: Queue maintains the last written configuration into JSQR" value: 0 - name: Mode1 description: "JSQR Mode 1: An empty queue disables software and hardware triggers of the injected sequence" value: 1 enum/OVRMOD: bit_size: 1 variants: - name: Preserve description: Preserve DR register when an overrun is detected value: 0 - name: Overwrite description: Overwrite DR register when an overrun is detected value: 1 enum/PCSEL: bit_size: 20 variants: - name: NotPreselected description: Input channel x is not pre-selected value: 0 - name: Preselected description: Pre-select input channel x value: 1 enum/RES: bit_size: 3 variants: - name: SixteenBit description: 16-bit resolution value: 0 - name: FourteenBit description: 14-bit resolution in legacy mode (not optimized power consumption) value: 1 - name: TwelveBit description: 12-bit resolution in legacy mode (not optimized power consumption) value: 2 - name: TenBit description: 10-bit resolution value: 3 - name: FourteenBitV description: 14-bit resolution value: 5 - name: TwelveBitV description: 12-bit resolution value: 6 - name: EightBit description: 8-bit resolution value: 7 enum/ROVSM: bit_size: 1 variants: - name: Continued description: Oversampling is temporary stopped and continued after injection sequence value: 0 - name: Resumed description: Oversampling is aborted and resumed from start after injection sequence value: 1 enum/SMP: bit_size: 3 variants: - name: Cycles1_5 description: 1.5 clock cycles value: 0 - name: Cycles2_5 description: 2.5 clock cycles value: 1 - name: Cycles8_5 description: 8.5 clock cycles value: 2 - name: Cycles16_5 description: 16.5 clock cycles value: 3 - name: Cycles32_5 description: 32.5 clock cycles value: 4 - name: Cycles64_5 description: 64.5 clock cycles value: 5 - name: Cycles387_5 description: 387.5 clock cycles value: 6 - name: Cycles810_5 description: 810.5 clock cycles value: 7 enum/TROVS: bit_size: 1 variants: - name: Automatic description: All oversampled conversions for a channel are run following a trigger value: 0 - name: Triggered description: Each oversampled conversion for a channel needs a new trigger value: 1