block/TIM_1CH: description: 1-channel timers items: - name: CR1 description: control register 1 byte_offset: 0 fieldset: CR1_1CH - name: DIER description: DMA/Interrupt enable register byte_offset: 12 fieldset: DIER_1CH - name: SR description: status register byte_offset: 16 fieldset: SR_1CH - name: EGR description: event generation register byte_offset: 20 access: Write fieldset: EGR_1CH - name: CCMR_Input description: capture/compare mode register 1 (input mode) array: len: 1 stride: 4 byte_offset: 24 fieldset: CCMR_Input_1CH - name: CCMR_Output description: capture/compare mode register 1 (output mode) array: len: 1 stride: 4 byte_offset: 24 fieldset: CCMR_Output_1CH - name: CCER description: capture/compare enable register byte_offset: 32 fieldset: CCER_1CH - name: CNT description: counter byte_offset: 36 fieldset: CNT_1CH - name: PSC description: prescaler byte_offset: 40 fieldset: PSC_1CH - name: ARR description: auto-reload register (Dither mode disabled) byte_offset: 44 fieldset: ARR_1CH - name: ARR_DITHER description: auto-reload register (Dither mode enabled) byte_offset: 44 fieldset: ARR_DITHER_1CH - name: CCR description: capture/compare register x (x=1) (Dither mode disabled) array: len: 1 stride: 4 byte_offset: 52 fieldset: CCR_1CH - name: CCR_DITHER description: capture/compare register x (x=1) (Dither mode enabled) array: len: 1 stride: 4 byte_offset: 52 fieldset: CCR_DITHER_1CH - name: TISEL description: input selection register byte_offset: 92 fieldset: TISEL_1CH fieldset/ARR_1CH: description: auto-reload register (Dither mode disabled) fields: - name: ARR description: Auto-reload value bit_offset: 0 bit_size: 16 fieldset/ARR_DITHER_1CH: description: auto-reload register (Dither mode enabled) fields: - name: DITHER description: Dither value bit_offset: 0 bit_size: 4 - name: ARR description: Auto-reload value bit_offset: 4 bit_size: 16 fieldset/CCER_1CH: description: capture/compare enable register fields: - name: CCE description: Capture/Compare x (x=1) output enable bit_offset: 0 bit_size: 1 array: len: 1 stride: 4 - name: CCP description: Capture/Compare x (x=1) output Polarity bit_offset: 1 bit_size: 1 array: len: 1 stride: 4 - name: CCNP description: Capture/Compare x (x=1) output Polarity bit_offset: 3 bit_size: 1 array: len: 1 stride: 4 fieldset/CCMR_Input_1CH: description: capture/compare mode register x (x=1) (input mode) fields: - name: CCS description: Capture/Compare y selection bit_offset: 0 bit_size: 2 array: len: 1 stride: 8 enum: CCMR_Input_CCS - name: ICPSC description: Input capture y prescaler bit_offset: 2 bit_size: 2 array: len: 1 stride: 8 - name: ICF description: Input capture y filter bit_offset: 4 bit_size: 4 array: len: 1 stride: 8 enum: FilterValue fieldset/CCMR_Output_1CH: description: capture/compare mode register x (x=1) (output mode) fields: - name: CCS description: Capture/Compare y selection bit_offset: 0 bit_size: 2 array: len: 1 stride: 8 enum: CCMR_Output_CCS - name: OCFE description: Output compare y fast enable bit_offset: 2 bit_size: 1 array: len: 1 stride: 8 - name: OCPE description: Output compare y preload enable bit_offset: 3 bit_size: 1 array: len: 1 stride: 8 - name: OCM description: Output compare y mode bit_offset: 4 bit_size: 3 array: len: 1 stride: 8 enum: OCM fieldset/CCR_1CH: description: capture/compare register x (x=1) (Dither mode disabled) fields: - name: CCR description: capture/compare x (x=1) value bit_offset: 0 bit_size: 16 fieldset/CCR_DITHER_1CH: description: capture/compare register x (x=1) (Dither mode enabled) fields: - name: DITHER description: Dither value bit_offset: 0 bit_size: 4 - name: CCR description: capture/compare x (x=1) value bit_offset: 4 bit_size: 16 fieldset/CNT_1CH: description: counter fields: - name: CNT description: counter value bit_offset: 0 bit_size: 16 - name: UIFCPY description: UIF copy bit_offset: 31 bit_size: 1 fieldset/CR1_1CH: description: control register 1 fields: - name: CEN description: Counter enable bit_offset: 0 bit_size: 1 - name: UDIS description: Update disable bit_offset: 1 bit_size: 1 - name: URS description: Update request source bit_offset: 2 bit_size: 1 enum: URS - name: OPM description: One-pulse mode enbaled bit_offset: 3 bit_size: 1 - name: ARPE description: Auto-reload preload enable bit_offset: 7 bit_size: 1 - name: CKD description: Clock division bit_offset: 8 bit_size: 2 enum: CKD - name: UIFREMAP description: UIF status bit remapping enable bit_offset: 11 bit_size: 1 - name: DITHEN description: Dithering enable bit_offset: 12 bit_size: 1 fieldset/DIER_1CH: description: DMA/Interrupt enable register fields: - name: UIE description: Update interrupt enable bit_offset: 0 bit_size: 1 - name: CCIE description: Capture/Compare x (x=1) interrupt enable bit_offset: 1 bit_size: 1 array: len: 1 stride: 1 fieldset/EGR_1CH: description: event generation register fields: - name: UG description: Update generation bit_offset: 0 bit_size: 1 - name: CCG description: Capture/compare x (x=1) generation bit_offset: 1 bit_size: 1 array: len: 1 stride: 1 fieldset/PSC_1CH: description: prescaler fields: - name: PSC description: Prescaler value bit_offset: 0 bit_size: 16 fieldset/SR_1CH: description: status register fields: - name: UIF description: Update interrupt flag bit_offset: 0 bit_size: 1 - name: CCIF description: Capture/compare x (x=1) interrupt flag bit_offset: 1 bit_size: 1 array: len: 1 stride: 1 - name: CCOF description: Capture/Compare x (x=1) overcapture flag bit_offset: 9 bit_size: 1 array: len: 1 stride: 1 fieldset/TISEL_1CH: description: input selection register fields: - name: TISEL description: Selects TIM_TIx (x=1) input bit_offset: 0 bit_size: 4 array: len: 1 stride: 8 block/TIM_1CH_CMP: extends: TIM_1CH description: 1-channel with one complementary output timers items: - name: CR2 description: control register 2 byte_offset: 4 fieldset: CR2_1CH_CMP - name: DIER description: DMA/Interrupt enable register byte_offset: 12 fieldset: DIER_1CH_CMP - name: SR description: status register byte_offset: 16 fieldset: SR_1CH_CMP - name: EGR description: event generation register byte_offset: 20 access: Write fieldset: EGR_1CH_CMP - name: CCER description: capture/compare enable register byte_offset: 32 fieldset: CCER_1CH_CMP - name: RCR description: repetition counter register byte_offset: 48 fieldset: RCR_1CH_CMP - name: CCR_DITHER description: capture/compare register x (x=1) (Dither mode enabled) array: len: 1 stride: 4 byte_offset: 52 fieldset: CCR_DITHER_1CH_CMP - name: BDTR description: break and dead-time register byte_offset: 68 fieldset: BDTR_1CH_CMP - name: DTR2 description: break and dead-time register byte_offset: 84 fieldset: DTR2_1CH_CMP - name: AF1 description: alternate function register 1 byte_offset: 96 fieldset: AF1_1CH_CMP - name: AF2 description: alternate function register 2 byte_offset: 100 fieldset: AF2_1CH_CMP - name: DCR description: DMA control register byte_offset: 988 fieldset: DCR_1CH_CMP - name: DMAR description: DMA address for full transfer byte_offset: 992 fieldset: DMAR_1CH_CMP fieldset/AF1_1CH_CMP: description: alternate function register 1 fields: - name: BKINE description: TIMx_BKIN input enable bit_offset: 0 bit_size: 1 - name: BKCMPE description: TIM_BRK_CMPx (x=1-8) enable bit_offset: 1 bit_size: 1 array: len: 8 stride: 1 - name: BKINP description: TIMx_BKIN input polarity bit_offset: 9 bit_size: 1 enum: BKINP - name: BKCMPP description: TIM_BRK_CMPx (x=1-4) input polarity bit_offset: 10 bit_size: 1 array: len: 4 stride: 1 enum: BKINP fieldset/AF2_1CH_CMP: description: alternate function register 2 fields: - name: OCRSEL description: ocref_clr source selection bit_offset: 16 bit_size: 3 fieldset/BDTR_1CH_CMP: description: break and dead-time register fields: - name: DTG description: Dead-time generator setup bit_offset: 0 bit_size: 8 - name: LOCK description: Lock configuration bit_offset: 8 bit_size: 2 enum: LOCK - name: OSSI description: Off-state selection for Idle mode bit_offset: 10 bit_size: 1 enum: OSSI - name: OSSR description: Off-state selection for Run mode bit_offset: 11 bit_size: 1 enum: OSSR - name: BKE description: Break x (x=1) enable bit_offset: 12 bit_size: 1 array: len: 1 stride: 12 - name: BKP description: Break x (x=1) polarity bit_offset: 13 bit_size: 1 array: len: 1 stride: 12 enum: BKP - name: AOE description: Automatic output enable bit_offset: 14 bit_size: 1 - name: MOE description: Main output enable bit_offset: 15 bit_size: 1 - name: BKF description: Break x (x=1) filter bit_offset: 16 bit_size: 4 array: len: 1 stride: 4 enum: FilterValue - name: BKDSRM description: Break x (x=1) Disarm bit_offset: 26 bit_size: 1 array: len: 1 stride: 1 enum: BKDSRM - name: BKBID description: Break x (x=1) bidirectional bit_offset: 28 bit_size: 1 array: len: 1 stride: 1 enum: BKBID fieldset/CCER_1CH_CMP: extends: CCER_1CH description: capture/compare enable register fields: - name: CCE description: Capture/Compare x (x=1) output enable bit_offset: 0 bit_size: 1 array: len: 1 stride: 4 - name: CCP description: Capture/Compare x (x=1) output Polarity bit_offset: 1 bit_size: 1 array: len: 1 stride: 4 - name: CCNP description: Capture/Compare x (x=1) output Polarity bit_offset: 3 bit_size: 1 array: len: 1 stride: 4 fieldset/CCR_DITHER_1CH_CMP: description: capture/compare register x (x=1) (Dither mode enabled) fields: - name: DITHER description: Dither value bit_offset: 0 bit_size: 4 - name: CCR description: capture/compare x (x=1) value bit_offset: 4 bit_size: 16 fieldset/CR2_1CH_CMP: description: control register 2 fields: - name: CCPC description: Capture/compare preloaded control bit_offset: 0 bit_size: 1 - name: CCUS description: Capture/compare control update selection bit_offset: 2 bit_size: 1 - name: CCDS description: Capture/compare DMA selection bit_offset: 3 bit_size: 1 enum: CCDS - name: OIS description: Output Idle state x (x=1) bit_offset: 8 bit_size: 1 array: len: 1 stride: 2 - name: OISN description: Output Idle state x (x=1) bit_offset: 9 bit_size: 1 array: len: 1 stride: 2 fieldset/DCR_1CH_CMP: description: DMA control register fields: - name: DBA description: DMA base address bit_offset: 0 bit_size: 5 - name: DBL description: DMA burst length bit_offset: 8 bit_size: 5 - name: DBSS description: DMA burst source selection bit_offset: 16 bit_size: 4 enum: DBSS fieldset/DIER_1CH_CMP: extends: DIER_1CH description: DMA/Interrupt enable register fields: - name: COMIE description: COM interrupt enable bit_offset: 5 bit_size: 1 - name: BIE description: Break interrupt enable bit_offset: 7 bit_size: 1 - name: UDE description: Update DMA request enable bit_offset: 8 bit_size: 1 - name: CCDE description: Capture/Compare x (x=1) DMA request enable bit_offset: 9 bit_size: 1 array: len: 1 stride: 1 fieldset/DMAR_1CH_CMP: description: DMA address for full transfer fields: - name: DMAB description: DMA register for burst accesses bit_offset: 0 bit_size: 32 fieldset/DTR2_1CH_CMP: description: deadtime register 2 fields: - name: DTGF description: Dead-time falling edge generator setup bit_offset: 0 bit_size: 8 - name: DTAE description: Deadtime asymmetric enable bit_offset: 16 bit_size: 1 enum: DTAE - name: DTPE description: Deadtime preload enable bit_offset: 17 bit_size: 1 fieldset/EGR_1CH_CMP: extends: EGR_1CH description: event generation register fields: - name: COMG description: Capture/Compare control update generation bit_offset: 5 bit_size: 1 - name: BG description: Break x (x=1) generation bit_offset: 7 bit_size: 1 array: len: 1 stride: 1 fieldset/RCR_1CH_CMP: description: repetition counter register fields: - name: REP description: Repetition counter value bit_offset: 0 bit_size: 8 fieldset/SR_1CH_CMP: extends: SR_1CH description: status register fields: - name: COMIF description: COM interrupt flag bit_offset: 5 bit_size: 1 - name: BIF description: Break x (x=1) interrupt flag bit_offset: 7 bit_size: 1 array: len: 1 stride: 1 enum/BKBID: bit_size: 1 variants: - name: Input description: Break input tim_brk in input mode value: 0 - name: Bidirectional description: Break input tim_brk in bidirectional mode value: 1 enum/BKDSRM: bit_size: 1 variants: - name: Armed description: Break input tim_brk is armed value: 0 - name: Disarmed description: Break input tim_brk is disarmed value: 1 enum/BKINP: bit_size: 1 variants: - name: NotInverted description: input polarity is not inverted (active low if BKxP = 0, active high if BKxP = 1) value: 0 - name: Inverted description: input polarity is inverted (active high if BKxP = 0, active low if BKxP = 1) value: 1 enum/BKP: bit_size: 1 variants: - name: ActiveLow description: Break input tim_brk is active low value: 0 - name: ActiveHigh description: Break input tim_brk is active high value: 1 enum/CCDS: bit_size: 1 variants: - name: OnCompare description: CCx DMA request sent when CCx event occurs value: 0 - name: OnUpdate description: CCx DMA request sent when update event occurs value: 1 enum/CCMR_Input_CCS: bit_size: 2 variants: - name: TI4 description: 'CCx channel is configured as input, normal mapping: ICx mapped to TIx' value: 1 - name: TI3 description: CCx channel is configured as input, alternate mapping (switches 1 with 2, 3 with 4) value: 2 - name: TRC description: CCx channel is configured as input, ICx is mapped on TRC value: 3 enum/CCMR_Output_CCS: bit_size: 2 variants: - name: Output description: CCx channel is configured as output value: 0 enum/CKD: bit_size: 2 variants: - name: Div1 description: t_DTS = t_CK_INT value: 0 - name: Div2 description: t_DTS = 2 × t_CK_INT value: 1 - name: Div4 description: t_DTS = 4 × t_CK_INT value: 2 enum/DBSS: bit_size: 4 variants: - name: Update description: Update value: 1 - name: CC1 description: CC1 value: 2 - name: CC2 description: CC2 value: 3 - name: CC3 description: CC3 value: 4 - name: CC4 description: CC4 value: 5 - name: COM description: COM value: 6 - name: Trigger description: Trigger value: 7 enum/DTAE: bit_size: 1 variants: - name: Identical description: Deadtime on rising and falling edges are identical, and defined with DTG[7:0] register value: 0 - name: Distinct description: Deadtime on rising edge is defined with DTG[7:0] register and deadtime on falling edge is defined with DTGF[7:0] bits. value: 1 enum/FilterValue: bit_size: 4 variants: - name: NoFilter description: No filter, sampling is done at fDTS value: 0 - name: FCK_INT_N2 description: fSAMPLING=fCK_INT, N=2 value: 1 - name: FCK_INT_N4 description: fSAMPLING=fCK_INT, N=4 value: 2 - name: FCK_INT_N8 description: fSAMPLING=fCK_INT, N=8 value: 3 - name: FDTS_Div2_N6 description: fSAMPLING=fDTS/2, N=6 value: 4 - name: FDTS_Div2_N8 description: fSAMPLING=fDTS/2, N=8 value: 5 - name: FDTS_Div4_N6 description: fSAMPLING=fDTS/4, N=6 value: 6 - name: FDTS_Div4_N8 description: fSAMPLING=fDTS/4, N=8 value: 7 - name: FDTS_Div8_N6 description: fSAMPLING=fDTS/8, N=6 value: 8 - name: FDTS_Div8_N8 description: fSAMPLING=fDTS/8, N=8 value: 9 - name: FDTS_Div16_N5 description: fSAMPLING=fDTS/16, N=5 value: 10 - name: FDTS_Div16_N6 description: fSAMPLING=fDTS/16, N=6 value: 11 - name: FDTS_Div16_N8 description: fSAMPLING=fDTS/16, N=8 value: 12 - name: FDTS_Div32_N5 description: fSAMPLING=fDTS/32, N=5 value: 13 - name: FDTS_Div32_N6 description: fSAMPLING=fDTS/32, N=6 value: 14 - name: FDTS_Div32_N8 description: fSAMPLING=fDTS/32, N=8 value: 15 enum/LOCK: bit_size: 2 variants: - name: Disabled description: No bit is write protected value: 0 - name: Level1 description: DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register and BKBID/BKE/BKP/AOE bits in TIMx_BDTR register can no longer be written value: 1 - name: Level2 description: LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written. value: 2 - name: Level3 description: LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written. value: 3 enum/OCM: bit_size: 3 variants: - name: Frozen description: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs value: 0 - name: ActiveOnMatch description: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register value: 1 - name: InactiveOnMatch description: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register value: 2 - name: Toggle description: OCyREF toggles when TIMx_CNT=TIMx_CCRy value: 3 - name: ForceInactive description: OCyREF is forced low value: 4 - name: ForceActive description: OCyREF is forced high value: 5 - name: PwmMode1 description: In upcounting, channel is active as long as TIMx_CNTTIMx_CCRy else active value: 6 - name: PwmMode2 description: Inversely to PwmMode1 value: 7 enum/OSSI: bit_size: 1 variants: - name: Disabled description: When inactive, OC/OCN outputs are disabled value: 0 - name: IdleLevel description: When inactive, OC/OCN outputs are forced to idle level value: 1 enum/OSSR: bit_size: 1 variants: - name: Disabled description: When inactive, OC/OCN outputs are disabled value: 0 - name: IdleLevel description: When inactive, OC/OCN outputs are enabled with their inactive level value: 1 enum/URS: bit_size: 1 variants: - name: AnyEvent description: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request value: 0 - name: CounterOnly description: Only counter overflow/underflow generates an update interrupt or DMA request value: 1