block/IC:
  items:
  - name: ISR
    description: LPTIM interrupt and status register.
    byte_offset: 0
    fieldset: ISR_IC
  - name: ICR
    description: LPTIM interrupt clear register.
    byte_offset: 4
    fieldset: ICR_IC
  - name: DIER
    description: LPTIM interrupt enable register.
    byte_offset: 8
    fieldset: DIER_IC
block/LPTIM_ADV:
  extends: LPTIM_BASIC
  description: Low power timer with Output Compare
  items:
  - name: InputCapture
    byte_offset: 0
    block: IC
  - name: OutputCompare
    byte_offset: 0
    block: OC_ADV
  - name: CCR
    description: LPTIM compare register 1.
    array:
      len: 2
      stride: 32
    byte_offset: 20
    fieldset: CCR
  - name: CCMR_IC
    description: LPTIM capture/compare mode register 1.
    byte_offset: 44
    fieldset: CCMR_IC
  - name: CCMR_OC
    description: LPTIM capture/compare mode register 1.
    byte_offset: 44
    fieldset: CCMR_OC
block/LPTIM_BASIC:
  description: Low power timer with Output Compare
  items:
  - name: ISR
    description: LPTIM interrupt and status register.
    byte_offset: 0
    fieldset: ISR_BASIC
  - name: ICR
    description: LPTIM interrupt clear register.
    byte_offset: 4
    fieldset: ICR_BASIC
  - name: DIER
    description: LPTIM interrupt enable register.
    byte_offset: 8
    fieldset: DIER_BASIC
  - name: CFGR
    description: LPTIM configuration register.
    byte_offset: 12
    fieldset: CFGR
  - name: CR
    description: LPTIM control register.
    byte_offset: 16
    fieldset: CR
  - name: CCR
    description: LPTIM compare register 1.
    array:
      len: 1
      stride: 32
    byte_offset: 20
    fieldset: CCR
  - name: ARR
    description: LPTIM autoreload register.
    byte_offset: 24
    fieldset: ARR
  - name: CNT
    description: LPTIM counter register.
    byte_offset: 28
    fieldset: CNT
  - name: CFGR2
    description: LPTIM configuration register 2.
    byte_offset: 36
    fieldset: CFGR2
  - name: RCR
    description: LPTIM repetition register.
    byte_offset: 40
    fieldset: RCR
block/OC_ADV:
  items:
  - name: ISR
    description: LPTIM interrupt and status register.
    byte_offset: 0
    fieldset: ISR_OC_ADV
  - name: ICR
    description: LPTIM interrupt clear register.
    byte_offset: 4
    fieldset: ICR_OC_ADV
  - name: DIER
    description: LPTIM interrupt enable register.
    byte_offset: 8
    fieldset: DIER_OC_ADV
fieldset/ARR:
  description: LPTIM autoreload register.
  fields:
  - name: ARR
    description: Auto reload value ARR is the autoreload value for the LPTIM. This value must be strictly greater than the CCRx[15:0] value.
    bit_offset: 0
    bit_size: 16
fieldset/CCMR_IC:
  extends: CCMR_partial
  description: LPTIM input capture mode register 1.
  fields:
  - name: CCP
    description: Capture/compare 1 output polarity. Only bit2 is used to set polarity when output mode is enabled, bit3 is don't care. This field is used to select the IC1 polarity for capture operations.
    bit_offset: 2
    bit_size: 2
    array:
      len: 2
      stride: 16
    enum: CCP_IC
fieldset/CCMR_OC:
  extends: CCMR_partial
  description: LPTIM output compare mode register 1.
  fields:
  - name: CCP
    description: Capture/compare 1 output polarity. Only bit2 is used to set polarity when output mode is enabled, bit3 is don't care. This field is used to select the IC1 polarity for capture operations.
    bit_offset: 2
    bit_size: 2
    array:
      len: 2
      stride: 16
    enum: CCP_OC
fieldset/CCMR_partial:
  description: internal use only - common fields between CCMR input mode and output mode
  fields:
  - name: CCSEL
    description: Capture/compare 1 selection This bitfield defines the direction of the channel input (capture) or output mode.
    bit_offset: 0
    bit_size: 1
    array:
      len: 2
      stride: 16
    enum: CCSEL
  - name: CCE
    description: Capture/compare 1 output enable. This bit determines if a capture of the counter value can actually be done into the input capture/compare register 1 (LPTIM_CCR1) or not.
    bit_offset: 1
    bit_size: 1
    array:
      len: 2
      stride: 16
  - name: ICPSC
    description: Input capture 1 prescaler This bitfield defines the ratio of the prescaler acting on the CC1 input (IC1).
    bit_offset: 8
    bit_size: 2
    array:
      len: 2
      stride: 16
    enum: Filter
  - name: ICF
    description: Input capture 1 filter This bitfield defines the number of consecutive equal samples that should be detected when a level change occurs on an external input capture signal before it is considered as a valid level transition. An internal clock source must be present to use this feature.
    bit_offset: 12
    bit_size: 2
    array:
      len: 2
      stride: 16
    enum: Filter
fieldset/CCR:
  description: LPTIM compare register 1.
  fields:
  - name: CCR
    description: 'Capture/compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the capture/compare 1 register. Depending on the PRELOAD option, the CCR1 register is immediately updated if the PRELOAD bit is reset and updated at next LPTIM update event if PREOAD bit is reset. The capture/compare register 1 contains the value to be compared to the counter LPTIM_CNT and signaled on OC1 output. If channel CC1 is configured as input: CCR1 contains the counter value transferred by the last input capture 1 event. The LPTIM_CCR1 register is read-only and cannot be programmed. If LPTIM does not implement any channel: The compare register 1 contains the value to be compared to the counter LPTIM_CNT and signaled on LPTIM output.'
    bit_offset: 0
    bit_size: 16
fieldset/CFGR:
  description: LPTIM configuration register.
  fields:
  - name: CKSEL
    description: Clock selector The CKSEL bit selects which clock source the LPTIM uses:.
    bit_offset: 0
    bit_size: 1
    enum: CKSEL
  - name: CKPOL
    description: 'Clock Polarity When the LPTIM is clocked by an external clock source, CKPOL bits is used to configure the active edge or edges used by the counter: If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active. Refer to for more details about Encoder mode sub-modes.'
    bit_offset: 1
    bit_size: 2
    enum: CKPOL
  - name: CKFLT
    description: Configurable digital filter for external clock The CKFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an external clock signal before it is considered as a valid level transition. An internal clock source must be present to use this feature.
    bit_offset: 3
    bit_size: 2
    enum: Filter
  - name: TRGFLT
    description: Configurable digital filter for trigger The TRGFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an internal trigger before it is considered as a valid level transition. An internal clock source must be present to use this feature.
    bit_offset: 6
    bit_size: 2
    enum: Filter
  - name: PRESC
    description: Clock prescaler The PRESC bits configure the prescaler division factor. It can be one among the following division factors:.
    bit_offset: 9
    bit_size: 3
    enum: PRESC
  - name: TRIGSEL
    description: 'Trigger selector The TRIGSEL bits select the trigger source that serves as a trigger event for the LPTIM among the below 8 available sources: See for details.'
    bit_offset: 13
    bit_size: 3
  - name: TRIGEN
    description: Trigger enable and polarity The TRIGEN bits controls whether the LPTIM counter is started by an external trigger or not. If the external trigger option is selected, three configurations are possible for the trigger active edge:.
    bit_offset: 17
    bit_size: 2
    enum: TRIGEN
  - name: TIMOUT
    description: Timeout enable The TIMOUT bit controls the Timeout feature.
    bit_offset: 19
    bit_size: 1
  - name: WAVE
    description: Waveform shape The WAVE bit controls the output shape.
    bit_offset: 20
    bit_size: 1
  - name: WAVPOL
    description: 'Waveform shape polarity The WAVEPOL bit controls the output polarity Note: If the LPTIM implements at least one capture/compare channel, this bit is reserved. Please refer to.'
    bit_offset: 21
    bit_size: 1
  - name: PRELOAD
    description: Registers update mode The PRELOAD bit controls the LPTIM_ARR, LPTIM_RCR and the LPTIM_CCRx registers update modality.
    bit_offset: 22
    bit_size: 1
  - name: COUNTMODE
    description: counter mode enabled The COUNTMODE bit selects which clock source is used by the LPTIM to clock the counter:.
    bit_offset: 23
    bit_size: 1
  - name: ENC
    description: 'Encoder mode enable The ENC bit controls the Encoder mode Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.'
    bit_offset: 24
    bit_size: 1
fieldset/CFGR2:
  description: LPTIM configuration register 2.
  fields:
  - name: INSEL
    description: LPTIM input 1 selection The IN1SEL bits control the LPTIM input 1 multiplexer, which connects LPTIM input 1 to one of the available inputs. For connection details refer to.
    bit_offset: 0
    bit_size: 2
    array:
      len: 2
      stride: 4
  - name: ICSEL
    description: LPTIM input capture 1 selection The IC1SEL bits control the LPTIM Input capture 1 multiplexer, which connects LPTIM Input capture 1 to one of the available inputs. For connection details refer to.
    bit_offset: 16
    bit_size: 2
    array:
      len: 2
      stride: 4
fieldset/CNT:
  description: LPTIM counter register.
  fields:
  - name: CNT
    description: Counter value When the LPTIM is running with an asynchronous clock, reading the LPTIM_CNT register may return unreliable values. So in this case it is necessary to perform two consecutive read accesses and verify that the two returned values are identical.
    bit_offset: 0
    bit_size: 16
fieldset/CR:
  description: LPTIM control register.
  fields:
  - name: ENABLE
    description: LPTIM enable The ENABLE bit is set and cleared by software.
    bit_offset: 0
    bit_size: 1
  - name: SNGSTRT
    description: LPTIM start in Single mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = ‘00’), setting this bit starts the LPTIM in single pulse mode. If the software start is disabled (TRIGEN[1:0] different than ‘00’), setting this bit starts the LPTIM in single pulse mode as soon as an external trigger is detected. If this bit is set when the LPTIM is in continuous counting mode, then the LPTIM stops at the following match between LPTIM_ARR and LPTIM_CNT registers. This bit can only be set when the LPTIM is enabled. It is automatically reset by hardware.
    bit_offset: 1
    bit_size: 1
  - name: CNTSTRT
    description: Timer start in Continuous mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = ‘00’), setting this bit starts the LPTIM in Continuous mode. If the software start is disabled (TRIGEN[1:0] different than ‘00’), setting this bit starts the timer in Continuous mode as soon as an external trigger is detected. If this bit is set when a single pulse mode counting is ongoing, then the timer does not stop at the next match between the LPTIM_ARR and LPTIM_CNT registers and the LPTIM counter keeps counting in Continuous mode. This bit can be set only when the LPTIM is enabled. It is automatically reset by hardware.
    bit_offset: 2
    bit_size: 1
  - name: COUNTRST
    description: Counter reset This bit is set by software and cleared by hardware. When set to '1' this bit triggers a synchronous reset of the LPTIM_CNT counter register. Due to the synchronous nature of this reset, it only takes place after a synchronization delay of 3 LPTimer core clock cycles (LPTimer core clock may be different from APB clock). This bit can be set only when the LPTIM is enabled. It is automatically reset by hardware. COUNTRST must never be set to '1' by software before it is already cleared to '0' by hardware. Software should consequently check that COUNTRST bit is already cleared to '0' before attempting to set it to '1'.
    bit_offset: 3
    bit_size: 1
  - name: RSTARE
    description: Reset after read enable This bit is set and cleared by software. When RSTARE is set to '1', any read access to LPTIM_CNT register asynchronously resets LPTIM_CNT register content. This bit can be set only when the LPTIM is enabled.
    bit_offset: 4
    bit_size: 1
fieldset/DIER_BASIC:
  description: LPTIM interrupt enable register.
  fields:
  - name: CCIE
    description: Capture/compare 1 interrupt enable.
    bit_offset: 0
    bit_size: 1
    array:
      len: 1
      stride: 9
  - name: ARRMIE
    description: Autoreload match Interrupt Enable.
    bit_offset: 1
    bit_size: 1
  - name: EXTTRIGIE
    description: External trigger valid edge Interrupt Enable.
    bit_offset: 2
    bit_size: 1
  - name: CMPOKIE
    description: Compare register 1 update OK interrupt enable.
    bit_offset: 3
    bit_size: 1
    array:
      len: 1
      stride: 16
  - name: ARROKIE
    description: Autoreload register update OK Interrupt Enable.
    bit_offset: 4
    bit_size: 1
  - name: UPIE
    description: 'Direction change to UP Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.'
    bit_offset: 5
    bit_size: 1
  - name: DOWNIE
    description: 'Direction change to down Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.'
    bit_offset: 6
    bit_size: 1
  - name: UEIE
    description: Update event interrupt enable.
    bit_offset: 7
    bit_size: 1
  - name: REPOKIE
    description: Repetition register update OK interrupt Enable.
    bit_offset: 8
    bit_size: 1
fieldset/DIER_IC:
  description: LPTIM interrupt enable register.
  fields:
  - name: CCIE
    description: Capture/compare 1 interrupt enable.
    bit_offset: 0
    bit_size: 1
    array:
      len: 2
      stride: 9
  - name: ARRMIE
    description: Autoreload match Interrupt Enable.
    bit_offset: 1
    bit_size: 1
  - name: EXTTRIGIE
    description: External trigger valid edge Interrupt Enable.
    bit_offset: 2
    bit_size: 1
  - name: ARROKIE
    description: Autoreload register update OK Interrupt Enable.
    bit_offset: 4
    bit_size: 1
  - name: UPIE
    description: 'Direction change to UP Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.'
    bit_offset: 5
    bit_size: 1
  - name: DOWNIE
    description: 'Direction change to down Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.'
    bit_offset: 6
    bit_size: 1
  - name: UEIE
    description: Update event interrupt enable.
    bit_offset: 7
    bit_size: 1
  - name: REPOKIE
    description: Repetition register update OK interrupt Enable.
    bit_offset: 8
    bit_size: 1
  - name: CCOIE
    description: 'Capture/compare 1 over-capture interrupt enable Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to.'
    bit_offset: 12
    bit_size: 1
    array:
      len: 2
      stride: 1
  - name: CCDE
    description: 'Capture/compare 1 DMA request enable Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to.'
    bit_offset: 16
    bit_size: 1
    array:
      len: 2
      stride: 9
  - name: UEDE
    description: 'Update event DMA request enable Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to.'
    bit_offset: 23
    bit_size: 1
fieldset/DIER_OC_ADV:
  extends: DIER_BASIC
  description: LPTIM interrupt enable register.
  fields:
  - name: CCIE
    description: Capture/compare 1 interrupt enable.
    bit_offset: 0
    bit_size: 1
    array:
      len: 2
      stride: 9
  - name: CMPOKIE
    description: Compare register 1 update OK interrupt enable.
    bit_offset: 3
    bit_size: 1
    array:
      len: 2
      stride: 16
fieldset/ICR_BASIC:
  description: LPTIM interrupt clear register.
  fields:
  - name: CCCF
    description: Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register.
    bit_offset: 0
    bit_size: 1
    array:
      len: 1
      stride: 9
  - name: ARRMCF
    description: Autoreload match clear flag Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register.
    bit_offset: 1
    bit_size: 1
  - name: EXTTRIGCF
    description: External trigger valid edge clear flag Writing 1 to this bit clears the EXTTRIG flag in the LPTIM_ISR register.
    bit_offset: 2
    bit_size: 1
  - name: CMPOKCF
    description: Compare register 1 update OK clear flag Writing 1 to this bit clears the CMP1OK flag in the LPTIM_ISR register.
    bit_offset: 3
    bit_size: 1
    array:
      len: 1
      stride: 16
  - name: ARROKCF
    description: Autoreload register update OK clear flag Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register.
    bit_offset: 4
    bit_size: 1
  - name: UPCF
    description: 'Direction change to UP clear flag Writing 1 to this bit clear the UP flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.'
    bit_offset: 5
    bit_size: 1
  - name: DOWNCF
    description: 'Direction change to down clear flag Writing 1 to this bit clear the DOWN flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.'
    bit_offset: 6
    bit_size: 1
  - name: UECF
    description: Update event clear flag Writing 1 to this bit clear the UE flag in the LPTIM_ISR register.
    bit_offset: 7
    bit_size: 1
  - name: REPOKCF
    description: Repetition register update OK clear flag Writing 1 to this bit clears the REPOK flag in the LPTIM_ISR register.
    bit_offset: 8
    bit_size: 1
  - name: DIEROKCF
    description: Interrupt enable register update OK clear flag Writing 1 to this bit clears the DIEROK flag in the LPTIM_ISR register.
    bit_offset: 24
    bit_size: 1
fieldset/ICR_IC:
  description: LPTIM interrupt clear register.
  fields:
  - name: CCCF
    description: Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register.
    bit_offset: 0
    bit_size: 1
    array:
      len: 2
      stride: 9
  - name: ARRMCF
    description: Autoreload match clear flag Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register.
    bit_offset: 1
    bit_size: 1
  - name: EXTTRIGCF
    description: External trigger valid edge clear flag Writing 1 to this bit clears the EXTTRIG flag in the LPTIM_ISR register.
    bit_offset: 2
    bit_size: 1
  - name: ARROKCF
    description: Autoreload register update OK clear flag Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register.
    bit_offset: 4
    bit_size: 1
  - name: UPCF
    description: 'Direction change to UP clear flag Writing 1 to this bit clear the UP flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.'
    bit_offset: 5
    bit_size: 1
  - name: DOWNCF
    description: 'Direction change to down clear flag Writing 1 to this bit clear the DOWN flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.'
    bit_offset: 6
    bit_size: 1
  - name: UECF
    description: Update event clear flag Writing 1 to this bit clear the UE flag in the LPTIM_ISR register.
    bit_offset: 7
    bit_size: 1
  - name: REPOKCF
    description: Repetition register update OK clear flag Writing 1 to this bit clears the REPOK flag in the LPTIM_ISR register.
    bit_offset: 8
    bit_size: 1
  - name: CCOCF
    description: 'Capture/compare 1 over-capture clear flag Writing 1 to this bit clears the CC1OF flag in the LPTIM_ISR register. Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to.'
    bit_offset: 12
    bit_size: 1
    array:
      len: 2
      stride: 1
  - name: DIEROKCF
    description: Interrupt enable register update OK clear flag Writing 1 to this bit clears the DIEROK flag in the LPTIM_ISR register.
    bit_offset: 24
    bit_size: 1
fieldset/ICR_OC_ADV:
  extends: ICR_BASIC
  description: LPTIM interrupt clear register.
  fields:
  - name: CCCF
    description: Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register.
    bit_offset: 0
    bit_size: 1
    array:
      len: 2
      stride: 9
  - name: CMPOKCF
    description: Compare register 1 update OK clear flag Writing 1 to this bit clears the CMP1OK flag in the LPTIM_ISR register.
    bit_offset: 3
    bit_size: 1
    array:
      len: 2
      stride: 16
fieldset/ISR_BASIC:
  description: LPTIM interrupt and status register.
  fields:
  - name: CCIF
    description: Compare 1 interrupt flag The CC1IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. The CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register.
    bit_offset: 0
    bit_size: 1
    array:
      len: 1
      stride: 9
  - name: ARRM
    description: Autoreload match ARRM is set by hardware to inform application that LPTIM_CNT register’s value reached the LPTIM_ARR register’s value. ARRM flag can be cleared by writing 1 to the ARRMCF bit in the LPTIM_ICR register.
    bit_offset: 1
    bit_size: 1
  - name: EXTTRIG
    description: External trigger edge event EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. EXTTRIG flag can be cleared by writing 1 to the EXTTRIGCF bit in the LPTIM_ICR register.
    bit_offset: 2
    bit_size: 1
  - name: CMPOK
    description: Compare register 1 update OK CMP1OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR1 register has been successfully completed. CMP1OK flag can be cleared by writing 1 to the CMP1OKCF bit in the LPTIM_ICR register.
    bit_offset: 3
    bit_size: 1
    array:
      len: 1
      stride: 16
  - name: ARROK
    description: Autoreload register update OK ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR register has been successfully completed. ARROK flag can be cleared by writing 1 to the ARROKCF bit in the LPTIM_ICR register.
    bit_offset: 4
    bit_size: 1
  - name: UP
    description: 'Counter direction change down to up In Encoder mode, UP bit is set by hardware to inform application that the counter direction has changed from down to up. UP flag can be cleared by writing 1 to the UPCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.'
    bit_offset: 5
    bit_size: 1
  - name: DOWN
    description: 'Counter direction change up to down In Encoder mode, DOWN bit is set by hardware to inform application that the counter direction has changed from up to down. DOWN flag can be cleared by writing 1 to the DOWNCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.'
    bit_offset: 6
    bit_size: 1
  - name: UE
    description: LPTIM update event occurred UE is set by hardware to inform application that an update event was generated. UE flag can be cleared by writing 1 to the UECF bit in the LPTIM_ICR register.
    bit_offset: 7
    bit_size: 1
  - name: REPOK
    description: Repetition register update OK REPOK is set by hardware to inform application that the APB bus write operation to the LPTIM_RCR register has been successfully completed. REPOK flag can be cleared by writing 1 to the REPOKCF bit in the LPTIM_ICR register.
    bit_offset: 8
    bit_size: 1
  - name: DIEROK
    description: Interrupt enable register update OK DIEROK is set by hardware to inform application that the APB bus write operation to the LPTIM_DIER register has been successfully completed. DIEROK flag can be cleared by writing 1 to the DIEROKCF bit in the LPTIM_ICR register.
    bit_offset: 24
    bit_size: 1
fieldset/ISR_IC:
  description: LPTIM interrupt and status register.
  fields:
  - name: CCIF
    description: 'capture 1 interrupt flag If channel CC1 is configured as input: CC1IF is set by hardware to inform application that the current value of the counter is captured in LPTIM_CCR1 register. The corresponding interrupt or DMA request is generated if enabled. The CC1OF flag is set if the CC1IF flag was already high.'
    bit_offset: 0
    bit_size: 1
    array:
      len: 2
      stride: 9
  - name: ARRM
    description: Autoreload match ARRM is set by hardware to inform application that LPTIM_CNT register’s value reached the LPTIM_ARR register’s value. ARRM flag can be cleared by writing 1 to the ARRMCF bit in the LPTIM_ICR register.
    bit_offset: 1
    bit_size: 1
  - name: EXTTRIG
    description: External trigger edge event EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. EXTTRIG flag can be cleared by writing 1 to the EXTTRIGCF bit in the LPTIM_ICR register.
    bit_offset: 2
    bit_size: 1
  - name: ARROK
    description: Autoreload register update OK ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR register has been successfully completed. ARROK flag can be cleared by writing 1 to the ARROKCF bit in the LPTIM_ICR register.
    bit_offset: 4
    bit_size: 1
  - name: UP
    description: 'Counter direction change down to up In Encoder mode, UP bit is set by hardware to inform application that the counter direction has changed from down to up. UP flag can be cleared by writing 1 to the UPCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.'
    bit_offset: 5
    bit_size: 1
  - name: DOWN
    description: 'Counter direction change up to down In Encoder mode, DOWN bit is set by hardware to inform application that the counter direction has changed from up to down. DOWN flag can be cleared by writing 1 to the DOWNCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.'
    bit_offset: 6
    bit_size: 1
  - name: UE
    description: LPTIM update event occurred UE is set by hardware to inform application that an update event was generated. UE flag can be cleared by writing 1 to the UECF bit in the LPTIM_ICR register.
    bit_offset: 7
    bit_size: 1
  - name: REPOK
    description: Repetition register update OK REPOK is set by hardware to inform application that the APB bus write operation to the LPTIM_RCR register has been successfully completed. REPOK flag can be cleared by writing 1 to the REPOKCF bit in the LPTIM_ICR register.
    bit_offset: 8
    bit_size: 1
  - name: CCOF
    description: 'Capture 1 over-capture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing 1 to the CC1OCF bit in the LPTIM_ICR register. Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to.'
    bit_offset: 12
    bit_size: 1
    array:
      len: 2
      stride: 1
  - name: DIEROK
    description: Interrupt enable register update OK DIEROK is set by hardware to inform application that the APB bus write operation to the LPTIM_DIER register has been successfully completed. DIEROK flag can be cleared by writing 1 to the DIEROKCF bit in the LPTIM_ICR register.
    bit_offset: 24
    bit_size: 1
fieldset/ISR_OC_ADV:
  extends: ISR_BASIC
  description: LPTIM interrupt and status register.
  fields:
  - name: CCIF
    description: Compare 1 interrupt flag The CC1IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. The CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register.
    bit_offset: 0
    bit_size: 1
    array:
      len: 2
      stride: 9
  - name: CMPOK
    description: Compare register 1 update OK CMP1OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR1 register has been successfully completed. CMP1OK flag can be cleared by writing 1 to the CMP1OKCF bit in the LPTIM_ICR register.
    bit_offset: 3
    bit_size: 1
    array:
      len: 2
      stride: 16
fieldset/RCR:
  description: LPTIM repetition register.
  fields:
  - name: REP
    description: Repetition register value REP is the repetition value for the LPTIM.
    bit_offset: 0
    bit_size: 8
enum/CCP_IC:
  bit_size: 2
  variants:
  - name: Rising
    value: 0
  - name: Falling
    value: 1
  - name: Both
    value: 3
enum/CCP_OC:
  bit_size: 2
  variants:
  - name: ActiveHigh
    value: 0
  - name: ActiveLow
    value: 1
enum/CCSEL:
  bit_size: 1
  variants:
  - name: OutputCompare
    description: channel is configured in output PWM mode
    value: 0
  - name: InputCapture
    description: channel is configured in input capture mode
    value: 1
enum/CKPOL:
  bit_size: 2
  variants:
  - name: Rising
    description: the rising edge is the active edge used for counting. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active.
    value: 0
  - name: Falling
    description: the falling edge is the active edge used for counting. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active.
    value: 1
  - name: Both
    description: both edges are active edges. When both external clock signal edges are considered active ones, the LPTIM must also be clocked by an internal clock source with a frequency equal to at least four times the external clock frequency. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 3 is active.
    value: 2
enum/CKSEL:
  bit_size: 1
  variants:
  - name: Internal
    description: LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators)
    value: 0
  - name: External
    description: LPTIM is clocked by an external clock source through the LPTIM external Input1
    value: 1
enum/Filter:
  bit_size: 2
  variants:
  - name: Count1
    value: 0
  - name: Count2
    value: 1
  - name: Count4
    value: 2
  - name: Count8
    value: 3
enum/PRESC:
  bit_size: 3
  variants:
  - name: Div1
    value: 0
  - name: Div2
    value: 1
  - name: Div4
    value: 2
  - name: Div8
    value: 3
  - name: Div16
    value: 4
  - name: Div32
    value: 5
  - name: Div64
    value: 6
  - name: Div128
    value: 7
enum/TRIGEN:
  bit_size: 2
  variants:
  - name: Software
    description: software trigger (counting start is initiated by software)
    value: 0
  - name: RisingEdge
    description: rising edge is the active edge
    value: 1
  - name: FallingEdge
    description: falling edge is the active edge
    value: 2
  - name: BothEdge
    description: both edges are active edges
    value: 3