e857389850Add OR register. OR1 is the same as OR. The content is different across chip serials. Leave entire register to HAL to parse. OR2 and OR3 are just AF1 and AF2.
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2024-02-05 15:40:49 +08:00
b3871b47d8mapping bug fix
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2024-02-02 00:04:54 +08:00
eb88e4bfb6tailoring from timer_v1 to timer_l0
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2024-02-01 22:04:57 +08:00
281787fbb1branch timer_l0 from timer_v1
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2024-02-01 19:41:44 +08:00
9fa345af29add TIM_BASIC_NO_CR2, common part of TIM_BASIC and TIM_1CH_CMP
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2024-01-30 19:00:09 +08:00
10a1a61baelet TIM_ADV based on TIM_2CH_CMP
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2024-01-27 00:05:52 +08:00
cd490fd7f3let TIM_GP16 based on TIM_2CH
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2024-01-26 22:10:48 +08:00
6b5e0c6b4eadd TIM_CORE, common part of TIM_BASIC and TIM_1CH
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2024-01-26 15:26:33 +08:00
db6e501fd3make 2CH_CMP based on 1CH_CMP
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2024-01-25 15:57:26 +08:00
771c51b438bug fix
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2024-01-22 19:23:26 +08:00
982b30aa6aupdate timer mapping
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2024-01-22 18:11:36 +08:00
abb0f63c4atailoring timer_v1 from timer_v2
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2024-01-22 17:43:40 +08:00
81d09e5782branch timer_v1 from timer_v2
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2024-01-22 16:36:26 +08:00
ab11ed85fbremove redundant CCR fieldset, and bug fix
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2024-01-22 16:31:39 +08:00
7518e37532merge all TIMs into timer_v2
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2024-01-22 01:48:01 +08:00
1b83acf50bch2_cmp, ch2, ch1_cmp, ch1 merged
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2024-01-22 00:30:01 +08:00
0ed4c863d21ch_cmp, 1ch merged
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2024-01-22 00:04:45 +08:00
d2ec8c049c2ch_cmp, 2ch, 1ch merged
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2024-01-21 23:51:48 +08:00
864e7a70782ch_cmp, 2ch merged
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2024-01-21 23:33:30 +08:00
65a7e873c6adv, gp16, gp32, basic merged
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2024-01-21 23:11:27 +08:00
a3e7e74535adv, gp16, gp32 merged
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2024-01-21 22:48:07 +08:00
6eba236edeadv, gp16 merged
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2024-01-21 22:28:36 +08:00
9ede4ad2c0merging adv, gp16
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2024-01-21 22:26:49 +08:00
cb85778273naming block, as start point of merging
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2024-01-21 19:49:07 +08:00
6356128ba2tailoring from tim2chcmp to timbasic
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2024-01-20 21:34:10 +08:00
0096f150c0branch from tim2chcmp to timbasic
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2024-01-20 21:32:35 +08:00
8c321f182ctailoring from tim2chcmp to tim1chcmp
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2024-01-20 21:09:26 +08:00
b4d5936b9bbranch from tim2chcmp to tim1chcmp
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2024-01-20 21:08:27 +08:00
8361dffb8dbug fix
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2024-01-20 21:07:27 +08:00
75011dc243tailoring from tim2ch to tim1ch
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2024-01-20 20:52:53 +08:00
1e35b09edftailoring from tim2chcmp to tim2ch
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2024-01-20 20:13:43 +08:00
dd1d4c772bbranch from tim2chcmp to tim2ch
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2024-01-20 20:12:12 +08:00
8c0ab318catailoring form timadv to tim2chcmp
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2024-01-20 19:34:37 +08:00
4bdc25368fbranch from timadv to tim2chcmp
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2024-01-20 19:29:29 +08:00
0bb68b7dcbbug fix
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2024-01-20 19:28:10 +08:00
6e36b80628tailoring from gp16 to gp32
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2024-01-20 16:01:31 +08:00
864508ced7branching gp32 from gp16
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2024-01-20 15:58:28 +08:00
ffd1d9a48fredesign access at dither mode
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2024-01-20 15:37:50 +08:00
ee78a5d925tailoring from adv to gp16
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2024-01-20 15:03:04 +08:00
033aaaecb3branch gp16 from adv
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2024-01-20 15:00:26 +08:00
70282b4d94timadv, enum level
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2024-01-20 13:27:37 +08:00
1cd8d830f3timadv, fieldset level
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2024-01-20 12:43:26 +08:00
396ccfda7dtimadv, block level
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2024-01-20 01:30:11 +08:00