Commit Graph

  • 87b06bac89 rcc: separate fields for bus and kernel clock. Dario Nieuwenhuis 2024-02-16 01:07:41 +01:00
  • 917db8f71e Do not lowercase clock names. Dario Nieuwenhuis 2024-02-16 00:26:37 +01:00
  • e2c7a7eae0 rcc: fix tons of wrong muxes. Dario Nieuwenhuis 2024-02-16 00:11:14 +01:00
  • c8698f3cd8 chiptool fmt. Dario Nieuwenhuis 2024-02-15 23:25:16 +01:00
  • 3a9e43b7e9 aaaaa Dario Nieuwenhuis 2024-02-15 22:40:49 +01:00
  • c5482f1459
    Merge pull request #392 from eZioPan/discountinous-field Dario Nieuwenhuis 2024-02-15 19:45:33 +00:00
  • f2c85fb49c update timer_v1 eZio Pan 2024-02-13 21:03:22 +08:00
  • 1045313d2c update timer_v2 eZio Pan 2024-02-13 19:22:37 +08:00
  • 5907efbaf2 update chiptool eZio Pan 2024-02-13 11:54:13 +08:00
  • 156c0ec278
    Merge pull request #394 from eZioPan/remove-clippy-warning Dario Nieuwenhuis 2024-02-15 19:34:21 +00:00
  • 8c4122d7c6 remove clippy warning and error from genrated files. eZio Pan 2024-02-15 23:39:08 +08:00
  • 3cc1a1603e rcc: fix wrong usart1 mux in f0, f3. Dario Nieuwenhuis 2024-02-14 17:23:30 +01:00
  • a7d09dbb0a
    Merge pull request #393 from msrd0/fix-my-own-typo Dario Nieuwenhuis 2024-02-14 08:58:07 +00:00
  • 3612060bbe
    Fix typo in syscfg_h7 Dominic 2024-02-14 09:47:37 +01:00
  • ab89051030 rcc: Rename TIMI2C -> TIMIC. Dario Nieuwenhuis 2024-02-14 00:53:34 +01:00
  • 8010c4e7b8 cleanup rcc code a bit more. Dario Nieuwenhuis 2024-02-14 00:30:23 +01:00
  • 7734584b20 rcc: more accurate f0 mapping. Dario Nieuwenhuis 2024-02-13 01:04:42 +01:00
  • 156cb15b80 RCC: rename NoMCO -> DISABLE Dario Nieuwenhuis 2024-02-13 00:23:34 +01:00
  • 8a3ad0b738 chiptool fmt. Dario Nieuwenhuis 2024-02-12 20:48:59 +01:00
  • 7725fc62f7 pwr: add sdlevel enum. Dario Nieuwenhuis 2024-02-12 20:41:01 +01:00
  • c6b8d61400
    Merge pull request #391 from msrd0/syscfg-ur17-tcm-axi Dario Nieuwenhuis 2024-02-12 18:52:11 +00:00
  • 39dcea050b
    Add TCM_AXI_SHARED_CFG to SYSCFG_UR18 for STM32H7 Dominic 2024-02-12 18:13:40 +01:00
  • 8ae5bb5fe6 rcc: more accurate f3 versions. Dario Nieuwenhuis 2024-02-12 02:03:25 +01:00
  • 5bf4bec597 rcc: more generous fallback stripping all peripheral numbers. Dario Nieuwenhuis 2024-02-10 02:48:24 +01:00
  • 0c921dde2e Refactor RCC code to find more muxes. Dario Nieuwenhuis 2024-02-10 02:40:36 +01:00
  • 028efe4e6e
    Merge pull request #364 from eZioPan/timer_v2 Dario Nieuwenhuis 2024-02-09 22:42:17 +00:00
  • 36a3262735
    Merge pull request #390 from caleb-garrett/hash Dario Nieuwenhuis 2024-02-08 20:08:11 +00:00
  • 3fdcc771f3 Added hash v4. Caleb Garrett 2024-02-08 14:39:43 -05:00
  • d7c933984f
    Merge pull request #382 from lucasgranberg/main Dario Nieuwenhuis 2024-02-07 18:24:39 +00:00
  • 19c010e2e1
    Merge pull request #389 from msrd0/syscfg_ur18 Dario Nieuwenhuis 2024-02-07 18:24:02 +00:00
  • 90698114d6
    Merge pull request #387 from msrd0/octospi1en Dario Nieuwenhuis 2024-02-07 18:23:45 +00:00
  • b23e88a617
    Merge pull request #388 from msrd0/octospi2 Dario Nieuwenhuis 2024-02-07 18:23:12 +00:00
  • ae595edcf2
    Add SYSCFG_UR18 register Dominic 2024-02-07 17:01:41 +01:00
  • 334a42bce7
    Fix register address for OCTOSPI2 peripheral Dominic 2024-02-07 16:58:16 +01:00
  • 01ef0b5999
    Add OCTOSPI1 register bits Dominic 2024-02-07 16:44:29 +01:00
  • b07168e665
    Merge pull request #381 from shufps/main Dario Nieuwenhuis 2024-02-07 13:47:49 +00:00
  • 90b8b692b7 add comp v3 to STM32WL (non E) Lucas Granberg 2024-02-07 15:37:57 +02:00
  • 8c8af96abd add comp_v3 and apply to stm32wl Lucas Granberg 2024-02-07 14:55:12 +02:00
  • 2f59dea33f cargo fmt shufps 2024-02-07 09:02:18 +01:00
  • 7c7194d546 adds adc support for L0 shufps 2024-02-07 08:57:52 +01:00
  • f0101a2249
    Merge pull request #377 from AdinAck/main Dario Nieuwenhuis 2024-02-06 16:59:03 +00:00
  • 5674011dd7
    Merge pull request #379 from caleb-garrett/hash Dario Nieuwenhuis 2024-02-06 00:04:14 +00:00
  • 44c579f350 Corrected hash v3 array lengths. Caleb Garrett 2024-02-05 18:35:15 -05:00
  • e857389850 Add OR register. OR1 is the same as OR. The content is different across chip serials. Leave entire register to HAL to parse. OR2 and OR3 are just AF1 and AF2. eZio Pan 2024-02-05 15:40:49 +08:00
  • b3871b47d8 mapping bug fix eZio Pan 2024-02-02 00:04:54 +08:00
  • eb88e4bfb6 tailoring from timer_v1 to timer_l0 eZio Pan 2024-02-01 22:04:57 +08:00
  • 281787fbb1 branch timer_l0 from timer_v1 eZio Pan 2024-02-01 19:41:44 +08:00
  • 9fa345af29 add TIM_BASIC_NO_CR2, common part of TIM_BASIC and TIM_1CH_CMP eZio Pan 2024-01-30 19:00:09 +08:00
  • 10a1a61bae let TIM_ADV based on TIM_2CH_CMP eZio Pan 2024-01-27 00:05:52 +08:00
  • cd490fd7f3 let TIM_GP16 based on TIM_2CH eZio Pan 2024-01-26 22:10:48 +08:00
  • 6b5e0c6b4e add TIM_CORE, common part of TIM_BASIC and TIM_1CH eZio Pan 2024-01-26 15:26:33 +08:00
  • db6e501fd3 make 2CH_CMP based on 1CH_CMP eZio Pan 2024-01-25 15:57:26 +08:00
  • 771c51b438 bug fix eZio Pan 2024-01-22 19:23:26 +08:00
  • 982b30aa6a update timer mapping eZio Pan 2024-01-22 18:11:36 +08:00
  • abb0f63c4a tailoring timer_v1 from timer_v2 eZio Pan 2024-01-22 17:43:40 +08:00
  • 81d09e5782 branch timer_v1 from timer_v2 eZio Pan 2024-01-22 16:36:26 +08:00
  • ab11ed85fb remove redundant CCR fieldset, and bug fix eZio Pan 2024-01-22 16:31:39 +08:00
  • 7518e37532 merge all TIMs into timer_v2 eZio Pan 2024-01-22 01:48:01 +08:00
  • 1b83acf50b ch2_cmp, ch2, ch1_cmp, ch1 merged eZio Pan 2024-01-22 00:30:01 +08:00
  • 0ed4c863d2 1ch_cmp, 1ch merged eZio Pan 2024-01-22 00:04:45 +08:00
  • d2ec8c049c 2ch_cmp, 2ch, 1ch merged eZio Pan 2024-01-21 23:51:48 +08:00
  • 864e7a7078 2ch_cmp, 2ch merged eZio Pan 2024-01-21 23:33:30 +08:00
  • 65a7e873c6 adv, gp16, gp32, basic merged eZio Pan 2024-01-21 23:11:27 +08:00
  • a3e7e74535 adv, gp16, gp32 merged eZio Pan 2024-01-21 22:48:07 +08:00
  • 6eba236ede adv, gp16 merged eZio Pan 2024-01-21 22:28:36 +08:00
  • 9ede4ad2c0 merging adv, gp16 eZio Pan 2024-01-21 22:26:49 +08:00
  • cb85778273 naming block, as start point of merging eZio Pan 2024-01-21 19:49:07 +08:00
  • 6356128ba2 tailoring from tim2chcmp to timbasic eZio Pan 2024-01-20 21:34:10 +08:00
  • 0096f150c0 branch from tim2chcmp to timbasic eZio Pan 2024-01-20 21:32:35 +08:00
  • 8c321f182c tailoring from tim2chcmp to tim1chcmp eZio Pan 2024-01-20 21:09:26 +08:00
  • b4d5936b9b branch from tim2chcmp to tim1chcmp eZio Pan 2024-01-20 21:08:27 +08:00
  • 8361dffb8d bug fix eZio Pan 2024-01-20 21:07:27 +08:00
  • 75011dc243 tailoring from tim2ch to tim1ch eZio Pan 2024-01-20 20:52:53 +08:00
  • 1e35b09edf tailoring from tim2chcmp to tim2ch eZio Pan 2024-01-20 20:13:43 +08:00
  • dd1d4c772b branch from tim2chcmp to tim2ch eZio Pan 2024-01-20 20:12:12 +08:00
  • 8c0ab318ca tailoring form timadv to tim2chcmp eZio Pan 2024-01-20 19:34:37 +08:00
  • 4bdc25368f branch from timadv to tim2chcmp eZio Pan 2024-01-20 19:29:29 +08:00
  • 0bb68b7dcb bug fix eZio Pan 2024-01-20 19:28:10 +08:00
  • 6e36b80628 tailoring from gp16 to gp32 eZio Pan 2024-01-20 16:01:31 +08:00
  • 864508ced7 branching gp32 from gp16 eZio Pan 2024-01-20 15:58:28 +08:00
  • ffd1d9a48f redesign access at dither mode eZio Pan 2024-01-20 15:37:50 +08:00
  • ee78a5d925 tailoring from adv to gp16 eZio Pan 2024-01-20 15:03:04 +08:00
  • 033aaaecb3 branch gp16 from adv eZio Pan 2024-01-20 15:00:26 +08:00
  • 70282b4d94 timadv, enum level eZio Pan 2024-01-20 13:27:37 +08:00
  • 1cd8d830f3 timadv, fieldset level eZio Pan 2024-01-20 12:43:26 +08:00
  • 396ccfda7d timadv, block level eZio Pan 2024-01-20 01:30:11 +08:00
  • d04eaeb0d5 Rename ICSEL -> I2CSEL Dario Nieuwenhuis 2024-02-05 00:36:48 +01:00
  • aa5dbf859f
    Merge pull request #378 from caleb-garrett/hash Dario Nieuwenhuis 2024-02-04 21:56:48 +00:00
  • 3dd8acfcc6 Undo YAML autoformat. Caleb Garrett 2024-02-04 16:52:13 -05:00
  • e702b4d564 fix pwr for wb35xx Dario Nieuwenhuis 2024-02-04 22:40:36 +01:00
  • eb0cad0476 Corrected hash STR register to RW. Caleb Garrett 2024-02-04 09:20:02 -05:00
  • 3e3b53df78 h5: more mux fix. Dario Nieuwenhuis 2024-02-02 23:20:36 +01:00
  • 79e839f9b5 h5: fix some bad rcc muxes. Dario Nieuwenhuis 2024-02-02 22:44:37 +01:00
  • dffe8dacce Add clock mux for F4 and F7. Dario Nieuwenhuis 2024-02-02 02:15:32 +01:00
  • 768b3e8e31 Fix missing AF numbers in H7 _C pins. Dario Nieuwenhuis 2024-02-01 23:46:31 +01:00
  • fcdcb0471b Fix missing DAC RCC on H7. Dario Nieuwenhuis 2024-02-01 23:40:12 +01:00
  • c6ad5e265a cleanup rcc bit matching. Dario Nieuwenhuis 2024-02-01 23:36:45 +01:00
  • 9e844dc5ac prevent "fatal: gc is already running" errors Dario Nieuwenhuis 2024-02-01 18:07:10 +01:00
  • 0cb3a4fcae always use non-_C GPIOs for digital signals on H7. Dario Nieuwenhuis 2024-02-01 01:35:33 +01:00
  • ee4b4abcc4 update g0 regex for single character Adin Ackerman 2024-01-30 18:32:48 -08:00