eZio Pan
9fdc197974
icache_v1 block array to fieldset array
2024-02-21 23:04:03 +08:00
eZio Pan
76f7173b98
remove 32bit fieldset
2024-02-21 21:26:48 +08:00
Dario Nieuwenhuis
2e0c6b6f79
Merge pull request #399 from eZioPan/dcache_v1
...
dcache v1
2024-02-21 13:13:55 +00:00
Dario Nieuwenhuis
f54653612c
Merge pull request #398 from eZioPan/tamp_h5
...
tamp h5
2024-02-21 13:12:48 +00:00
eZio Pan
3c8de38cdc
desc fix
2024-02-21 21:10:11 +08:00
eZio Pan
09b1d3b63a
apply transform
2024-02-21 21:10:05 +08:00
eZio Pan
442d176e8b
apply transform
2024-02-21 21:06:39 +08:00
eZio Pan
cc06ad6644
extract
2024-02-21 20:11:18 +08:00
eZio Pan
18a1eb503c
extract
2024-02-21 16:45:00 +08:00
eZio Pan
f40897c303
extract
2024-02-21 16:17:22 +08:00
Dario Nieuwenhuis
e2c7a7eae0
rcc: fix tons of wrong muxes.
2024-02-16 00:11:14 +01:00
Dario Nieuwenhuis
c8698f3cd8
chiptool fmt.
2024-02-15 23:25:16 +01:00
Dario Nieuwenhuis
3a9e43b7e9
aaaaa
2024-02-15 22:40:49 +01:00
eZio Pan
f2c85fb49c
update timer_v1
2024-02-15 20:42:08 +01:00
eZio Pan
1045313d2c
update timer_v2
2024-02-15 20:42:08 +01:00
Dario Nieuwenhuis
3cc1a1603e
rcc: fix wrong usart1 mux in f0, f3.
2024-02-14 17:23:48 +01:00
Dominic
3612060bbe
Fix typo in syscfg_h7
2024-02-14 09:47:37 +01:00
Dario Nieuwenhuis
ab89051030
rcc: Rename TIMI2C -> TIMIC.
2024-02-14 00:53:34 +01:00
Dario Nieuwenhuis
7734584b20
rcc: more accurate f0 mapping.
2024-02-13 01:04:42 +01:00
Dario Nieuwenhuis
156cb15b80
RCC: rename NoMCO -> DISABLE
2024-02-13 00:23:34 +01:00
Dario Nieuwenhuis
8a3ad0b738
chiptool fmt.
2024-02-12 20:48:59 +01:00
Dario Nieuwenhuis
7725fc62f7
pwr: add sdlevel enum.
2024-02-12 20:48:43 +01:00
Dominic
39dcea050b
Add TCM_AXI_SHARED_CFG to SYSCFG_UR18 for STM32H7
2024-02-12 18:13:40 +01:00
Dario Nieuwenhuis
8ae5bb5fe6
rcc: more accurate f3 versions.
2024-02-12 02:03:25 +01:00
Dario Nieuwenhuis
0c921dde2e
Refactor RCC code to find more muxes.
...
Fixes #383
2024-02-10 02:40:36 +01:00
Dario Nieuwenhuis
028efe4e6e
Merge pull request #364 from eZioPan/timer_v2
...
timer v2
2024-02-09 22:42:17 +00:00
Dario Nieuwenhuis
36a3262735
Merge pull request #390 from caleb-garrett/hash
...
Add HASH v4
2024-02-08 20:08:11 +00:00
Caleb Garrett
3fdcc771f3
Added hash v4.
2024-02-08 14:39:43 -05:00
Dario Nieuwenhuis
d7c933984f
Merge pull request #382 from lucasgranberg/main
...
add comp_v3 and apply to stm32wle
2024-02-07 18:24:39 +00:00
Dario Nieuwenhuis
19c010e2e1
Merge pull request #389 from msrd0/syscfg_ur18
...
Add SYSCFG_UR18 register
2024-02-07 18:24:02 +00:00
Dario Nieuwenhuis
90698114d6
Merge pull request #387 from msrd0/octospi1en
...
Add OCTOSPI1 register bits
2024-02-07 18:23:45 +00:00
Dominic
ae595edcf2
Add SYSCFG_UR18 register
2024-02-07 17:01:41 +01:00
Dominic
01ef0b5999
Add OCTOSPI1 register bits
...
Those were previously only called QUADSPI, which is needed on some
chips like the STM32H745, but those bits are used as OCTOSPI1 bits
on other chips like the STM32H723.
2024-02-07 16:44:29 +01:00
Lucas Granberg
8c8af96abd
add comp_v3 and apply to stm32wl
2024-02-07 14:55:12 +02:00
shufps
7c7194d546
adds adc support for L0
2024-02-07 08:57:52 +01:00
Dario Nieuwenhuis
f0101a2249
Merge pull request #377 from AdinAck/main
...
[READY NOW!] Initial Comparator Support
2024-02-06 16:59:03 +00:00
Dario Nieuwenhuis
5674011dd7
Merge pull request #379 from caleb-garrett/hash
...
Corrected hash v3 register arrays
2024-02-06 00:04:14 +00:00
Caleb Garrett
44c579f350
Corrected hash v3 array lengths.
2024-02-05 18:35:15 -05:00
eZio Pan
e857389850
Add OR register.
...
OR1 is the same as OR. The content is different across chip serials. Leave entire register to HAL to parse.
OR2 and OR3 are just AF1 and AF2.
2024-02-05 16:27:10 +08:00
eZio Pan
eb88e4bfb6
tailoring from timer_v1 to timer_l0
2024-02-05 16:27:10 +08:00
eZio Pan
281787fbb1
branch timer_l0 from timer_v1
2024-02-05 16:27:10 +08:00
eZio Pan
9fa345af29
add TIM_BASIC_NO_CR2, common part of TIM_BASIC and TIM_1CH_CMP
2024-02-05 16:27:10 +08:00
eZio Pan
10a1a61bae
let TIM_ADV based on TIM_2CH_CMP
2024-02-05 16:27:10 +08:00
eZio Pan
cd490fd7f3
let TIM_GP16 based on TIM_2CH
2024-02-05 16:27:10 +08:00
eZio Pan
6b5e0c6b4e
add TIM_CORE, common part of TIM_BASIC and TIM_1CH
2024-02-05 16:27:10 +08:00
eZio Pan
db6e501fd3
make 2CH_CMP based on 1CH_CMP
2024-02-05 16:27:10 +08:00
eZio Pan
771c51b438
bug fix
2024-02-05 16:27:10 +08:00
eZio Pan
abb0f63c4a
tailoring timer_v1 from timer_v2
2024-02-05 16:27:10 +08:00
eZio Pan
81d09e5782
branch timer_v1 from timer_v2
2024-02-05 16:27:10 +08:00
eZio Pan
ab11ed85fb
remove redundant CCR fieldset, and bug fix
2024-02-05 16:27:10 +08:00
