Dario Nieuwenhuis
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87b06bac89
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rcc: separate fields for bus and kernel clock.
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2024-02-16 01:07:41 +01:00 |
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xoviat
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54fedeeefa
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don't serialize default stop mode
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2023-11-05 16:11:58 -06:00 |
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xoviat
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b9efaf36d8
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add stop mode rcc data
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2023-11-05 15:52:50 -06:00 |
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Dario Nieuwenhuis
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4baa9a0079
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Merge pull request #265 from xoviat/sel
rcc: pipe through sel mux and generate ir
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2023-10-02 20:40:01 +00:00 |
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xoviat
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4a893c37da
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add man impl. pin signals
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2023-10-01 13:28:31 -05:00 |
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xoviat
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1595920962
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rcc: pipe through sel mux
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2023-09-25 19:26:46 -05:00 |
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JuliDi
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cf933a89de
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add proper sorting
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2023-09-14 16:26:54 +02:00 |
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JuliDi
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4484603dbd
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first working state with bad sorting
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2023-09-14 16:26:53 +02:00 |
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JackN
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6ed3e9d688
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Device::nvic_priority_bits as an `Option<u8>
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2023-03-22 17:26:38 -04:00 |
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JackN
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9c8ef4b931
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Add NVIC_PRIO_BITS to data and metapac
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2023-03-22 14:18:37 -04:00 |
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Dario Nieuwenhuis
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a2333b8afb
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New repo structure: includes stm32-metapac, doesn't commit generated files.
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2023-03-20 01:56:23 +01:00 |
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Grant Miller
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6b3a7bc0c2
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Rewrite python script in rust
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2022-11-12 17:12:51 -06:00 |
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