eZio Pan
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cc525f1b25
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timer: remove PSC fieldset
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2024-03-13 01:06:29 +08:00 |
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eZio Pan
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dd7fb87c83
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remove 32-bit fieldset from TIM
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2024-02-28 16:33:52 +08:00 |
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eZio Pan
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d9353ac72e
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tim fix: move BIE from GP16 to ADV
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2024-02-28 16:29:03 +08:00 |
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Dario Nieuwenhuis
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c8698f3cd8
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chiptool fmt.
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2024-02-15 23:25:16 +01:00 |
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eZio Pan
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1045313d2c
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update timer_v2
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2024-02-15 20:42:08 +01:00 |
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eZio Pan
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e857389850
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Add OR register.
OR1 is the same as OR. The content is different across chip serials. Leave entire register to HAL to parse.
OR2 and OR3 are just AF1 and AF2.
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2024-02-05 16:27:10 +08:00 |
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eZio Pan
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9fa345af29
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add TIM_BASIC_NO_CR2, common part of TIM_BASIC and TIM_1CH_CMP
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2024-02-05 16:27:10 +08:00 |
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eZio Pan
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10a1a61bae
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let TIM_ADV based on TIM_2CH_CMP
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2024-02-05 16:27:10 +08:00 |
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eZio Pan
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cd490fd7f3
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let TIM_GP16 based on TIM_2CH
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2024-02-05 16:27:10 +08:00 |
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eZio Pan
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6b5e0c6b4e
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add TIM_CORE, common part of TIM_BASIC and TIM_1CH
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2024-02-05 16:27:10 +08:00 |
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eZio Pan
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db6e501fd3
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make 2CH_CMP based on 1CH_CMP
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2024-02-05 16:27:10 +08:00 |
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eZio Pan
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ab11ed85fb
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remove redundant CCR fieldset, and bug fix
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2024-02-05 16:27:10 +08:00 |
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eZio Pan
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7518e37532
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merge all TIMs into timer_v2
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2024-02-05 16:27:10 +08:00 |
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eZio Pan
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65a7e873c6
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adv, gp16, gp32, basic merged
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2024-02-05 16:27:10 +08:00 |
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eZio Pan
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a3e7e74535
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adv, gp16, gp32 merged
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2024-02-05 16:27:10 +08:00 |
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eZio Pan
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6eba236ede
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adv, gp16 merged
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2024-02-05 16:27:10 +08:00 |
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eZio Pan
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9ede4ad2c0
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merging adv, gp16
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2024-02-05 16:27:10 +08:00 |
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