xoviat
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fb84c0ac55
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rcc: fixup clock names and expand checking
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2023-10-16 17:53:26 -05:00 |
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xoviat
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b9a89a1851
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rcc: cleanup variants and rename ahb -> clk
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2023-10-15 18:01:50 -05:00 |
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xoviat
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8b8686a852
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rcc: more mux and enum cleanup
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2023-10-15 10:37:36 -05:00 |
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xoviat
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5d51e3b706
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rcc: add more mux data
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2023-10-14 17:20:25 -05:00 |
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xoviat
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68d77f487b
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rcc: add more mux data
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2023-10-14 11:41:21 -05:00 |
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xoviat
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8a09bbb62c
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rcc: more cleanup
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2023-10-13 22:20:18 -05:00 |
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xoviat
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aa5e909e11
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rcc: more enum cleanup
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2023-10-13 20:54:24 -05:00 |
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xoviat
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c4cd46927d
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rcc: rename h5 clock enum variants and add check
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2023-10-12 20:48:35 -05:00 |
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xoviat
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421c595a13
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rcc: lower reg data
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2023-10-08 18:05:16 -05:00 |
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xoviat
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61c9f8c691
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rcc: fix mux determinism
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2023-10-08 15:43:06 -05:00 |
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xoviat
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1595920962
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rcc: pipe through sel mux
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2023-09-25 19:26:46 -05:00 |
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xoviat
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604ea4029c
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generate rccperipheral for rtc
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2023-09-25 15:57:52 -05:00 |
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xoviat
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d71fac77e6
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g4: fix rcc adc generation
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2023-09-11 15:55:53 -05:00 |
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Don Reilly
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7b0a28e989
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fixed missing edge case
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2023-08-09 10:34:10 -05:00 |
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Don Reilly
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f4e0487ae5
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map all (most?) edge cases of ADC
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2023-08-08 15:15:36 -05:00 |
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Dario Nieuwenhuis
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b96d1bddd3
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Add H5, and newer U5s.
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2023-03-27 12:17:53 +02:00 |
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Dario Nieuwenhuis
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a2333b8afb
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New repo structure: includes stm32-metapac, doesn't commit generated files.
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2023-03-20 01:56:23 +01:00 |
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