Dario Nieuwenhuis
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bdbf126746
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flash: set for all l0 chips.
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2023-09-26 05:06:10 +02:00 |
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xoviat
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b99b81e3ad
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Merge branch 'main' of https://github.com/embassy-rs/stm32-data into rtc
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2023-09-25 15:59:32 -05:00 |
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xoviat
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604ea4029c
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generate rccperipheral for rtc
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2023-09-25 15:57:52 -05:00 |
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Dario Nieuwenhuis
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4f83d5d9cf
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pwr: add f0, f1.
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2023-09-25 00:27:32 +02:00 |
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Dario Nieuwenhuis
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2f97514774
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pwr: add all VOS enums.
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2023-09-18 02:57:23 +02:00 |
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Dario Nieuwenhuis
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43c1e7b3be
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Add STM32WBA support.
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2023-09-16 02:34:03 +02:00 |
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xoviat
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c3548f2b7a
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add pwr l0
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2023-09-14 17:10:04 -05:00 |
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xoviat
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4e6a74f69c
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Merge pull request #252 from xoviat/adc-g4
g4: fix rcc adc generation and cleanup enums
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2023-09-11 21:08:12 +00:00 |
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xoviat
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d71fac77e6
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g4: fix rcc adc generation
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2023-09-11 15:55:53 -05:00 |
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xoviat
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b37cec1e73
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Merge pull request #251 from xoviat/sdmmc
u5: add sdmmc
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2023-09-10 19:08:48 +00:00 |
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xoviat
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539d2dd7fe
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u5: add sdmmc
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2023-09-10 14:05:55 -05:00 |
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xoviat
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85e6808094
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Merge pull request #241 from ExplodingWaffle/main
Add UCPD
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2023-09-10 18:24:38 +00:00 |
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xoviat
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bbff2b9e6b
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Merge pull request #249 from andresv/add-aes
Add AES registers
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2023-09-10 18:19:31 +00:00 |
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Andres Vahter
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5236cc71ce
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chips: add AES entries to perimap
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2023-09-07 23:08:54 +03:00 |
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Olle Sandberg
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9c71725bf2
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Support STM32WL5x ADC peripheral
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2023-09-05 12:22:56 +02:00 |
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Olle Sandberg
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ab99fff0af
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Support STM32WLEx ADC peripheral
Use adc_g0 since very similar to the WLE one.
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2023-09-05 11:59:10 +02:00 |
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Daehyeok Mun
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697ff5ff6e
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Support STM32G4 ADC peripheral
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2023-09-03 21:19:35 -07:00 |
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ExplodingWaffle
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82f8d72be7
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add ucpd
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2023-09-01 15:59:29 +01:00 |
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Dominik Sliwa
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6b2f2c3ac3
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split H7 flash for stm32h7a3/b3/b0 chips
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2023-08-18 22:13:58 +02:00 |
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Don Reilly
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7b0a28e989
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fixed missing edge case
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2023-08-09 10:34:10 -05:00 |
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Don Reilly
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f4e0487ae5
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map all (most?) edge cases of ADC
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2023-08-08 15:15:36 -05:00 |
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Don Reilly
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42273a7f02
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rework f3 series rcc take 2
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2023-08-07 14:38:22 -05:00 |
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Don Reilly
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5953194935
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cleaning up mess after fixing headers.rs
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2023-08-05 22:14:32 -05:00 |
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Don Reilly
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0a3e4c2052
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remove unneccessary paranthesis
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2023-08-05 18:31:18 -05:00 |
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Don Reilly
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39d4db37fe
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get common registers for adc12(34)
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2023-08-05 18:27:00 -05:00 |
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xoviat
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6bbb04dd90
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spi: fix stm32f479
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2023-08-04 19:00:04 -05:00 |
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Dario Nieuwenhuis
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1f8ab493e0
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Fix missing RNG interrupt in many chips.
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2023-07-31 01:25:09 +02:00 |
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Tyler Gilbert
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170ecab8cb
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Fix Issue #225.
The STM32U5 uses the same CRS peripheral as the L0, G0, and G4 products. This adds the association of the CRS v1 peripheral to the U5 CRS registers.
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2023-07-30 08:37:22 -05:00 |
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JuliDi
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0bc6cd3536
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add aditf5_v3_1 ADC
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2023-07-25 12:32:24 +02:00 |
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Dario Nieuwenhuis
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9d536f55a8
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Merge pull request #221 from xoviat/adc
adc: add f3
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2023-07-22 15:42:34 +00:00 |
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JuliDi
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57ccc6a59b
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add DAC v3
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2023-07-22 16:25:15 +02:00 |
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xoviat
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feb4f685ed
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adc: add f3
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2023-07-11 21:10:08 -05:00 |
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Dario Nieuwenhuis
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0ad838d889
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Merge pull request #213 from xoviat/hrtim
hrtim: add common registers and v2
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2023-07-08 08:40:13 +00:00 |
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Dario Nieuwenhuis
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793aeb9289
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Merge pull request #209 from JcBernack/rng-update
update RNG registers and mapping
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2023-07-07 15:24:57 +00:00 |
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Dario Nieuwenhuis
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d54274df23
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Merge pull request #216 from xoviat/fdcan
add fdcan
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2023-07-07 14:53:43 +00:00 |
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xoviat
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1e9103cd22
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fdcan: add registers
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2023-07-04 13:04:54 -05:00 |
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xoviat
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39ac6fe76e
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hrtim: fix version
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2023-07-02 15:30:43 -05:00 |
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xoviat
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c496da8628
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hrtim/v2: add registers
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2023-07-02 14:13:46 -05:00 |
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xoviat
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32f14c91a6
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hrtim: add v1.1
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2023-07-02 13:47:53 -05:00 |
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Dario Nieuwenhuis
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6cc7497a33
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Update chiptool, makes PAC generation repeatable.
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2023-07-02 15:42:12 +02:00 |
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xoviat
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c7e4df5ef1
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data-gen: add some yaml validation
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2023-07-01 17:18:40 -05:00 |
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Jan Christoph Bernack
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fc5867835f
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select RNG version based on family
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2023-07-01 03:40:43 +02:00 |
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Jan Christoph Bernack
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f1b05d243d
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update RNG registers and mapping
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2023-06-30 17:44:07 +02:00 |
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Dario Nieuwenhuis
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0b37690ca9
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Update chiptool.
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2023-06-29 01:12:05 +02:00 |
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Dario Nieuwenhuis
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eac1dc7600
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Fix unused mut.
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2023-06-29 01:00:03 +02:00 |
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Dario Nieuwenhuis
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883442f2ad
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Switch to bender CI
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2023-06-28 17:44:05 +02:00 |
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Kevin Lannen
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efc220eb38
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CRS: Use L0 CRS definitions for G0 and G4
Comparing the register definitions these peripherals are identical.
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2023-06-20 09:48:09 -06:00 |
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Dario Nieuwenhuis
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2dd3ecfc70
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Update chiptool (reg access is now safe, creating regs from raw ptrs is unsafe)
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2023-06-19 02:39:00 +02:00 |
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Dario Nieuwenhuis
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19f5df6144
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Merge pull request #193 from xoviat/can
can: skip duplicate interrupt in f107
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2023-06-18 10:43:41 +00:00 |
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xoviat
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e388dcebe7
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can: fix missing interrupts
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2023-06-17 19:13:00 -05:00 |
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