a7b126b078
eth-v2: Fix descriptors address fields
2021-06-13 08:16:11 -03:00
8e71f3da8e
Merge pull request #44 from Tiwalun/stm32wb55-support
...
Add RCC and SYSCFG for STM32WB55
2021-06-11 22:46:34 +02:00
6c872019d0
Add RCC and SYSCFG for STM32WB55
2021-06-11 22:36:40 +02:00
e3cc9b041c
Add a single yaml for eth_v2
2021-06-11 00:15:56 -03:00
2d0ecd1ec0
Add ethernet (v2) dma and mac
2021-06-11 00:15:56 -03:00
f202deb4c1
Add some enums to ADC fields.
2021-06-10 15:33:17 -04:00
b7c071aa71
Clean up a bit.
2021-06-10 10:38:02 -04:00
fc64e88b92
Extract ADCv3 (arrayification is not possible, slight diffs in field widths)
...
Extract ADC_COMMON
Create framework for extra synthetic hand-crafted peripherals.
Add VREFINTCAL reg/block/peripheral for STM32L4+.
2021-06-10 10:38:02 -04:00
23fed4339b
ADC v3 attempt #2 .
2021-06-10 10:37:32 -04:00
af3e9e60a3
Add missing RCC block for H7AB family
2021-06-10 08:57:46 +02:00
e58aa40b74
Minor register fixes for RCC L4
2021-06-07 15:31:44 +02:00
06fd321be1
Fix regs
2021-06-07 13:50:49 +02:00
5f350c7c25
Fix duplicate regs
2021-06-07 12:41:13 +02:00
c1aae8d3d8
Run through transform again
2021-06-07 12:22:09 +02:00
1d0b8db2ee
Regen and update transform
2021-06-07 12:03:15 +02:00
f31ba7bfcb
Separate block for H7AB
2021-06-03 15:43:21 +02:00
fea5e31f8b
Regen and remove *ON enums
2021-06-03 15:13:46 +02:00
529b991404
Do merge
2021-06-03 14:31:27 +02:00
332fc1728b
Add script for merging regs
2021-06-03 14:02:53 +02:00
aa9257548c
Remove enums from h7 regs
2021-06-03 12:27:42 +02:00
18a99a3a3b
Add RCC register for STM32F4 and STM32L4
...
Register block based in STM32F427ZI and STM32L4R9.
Use bool for reset registers.
Define clock mapping for RNG peripherals. There are no 1 <-> 1 mapping
of RNG peripheral to clock in the Cubedb sources. The mapping will
pre-select the clock source for RNG for now.
2021-06-03 11:33:24 +02:00
9ad584c149
Remove enums from enable registers
...
Add transform for RCC
2021-06-02 16:32:43 +02:00
b511ab77e9
Merge pull request #32 from lulf/add-dbgmcu-and-crs
...
Add DBGMCU for L0 and CRS from headers
2021-05-28 00:11:10 +02:00
10a1de11b1
Split TSEL back up. They are distinct.
2021-05-27 16:19:35 -04:00
26e98df986
DAC v2-ish regs.
2021-05-27 16:16:41 -04:00
25caa7875b
Add DBGMCU for L0 and CRS from headers
2021-05-26 15:17:55 +02:00
627ec79b3d
Add i2c v1 reg block.
2021-05-25 10:53:29 -04:00
84b6d351dc
Add H7 DBGMCU
2021-05-21 19:55:56 -03:00
e101180bb0
Remove duplicates from H7 FLASH
2021-05-21 19:55:56 -03:00
15bc0b7340
H7: Add FLASH and PWR
2021-05-21 19:55:56 -03:00
2dda36bd49
H7 RCC: Make more arrays
2021-05-21 19:55:56 -03:00
4199b328ee
Add H7 RCC
2021-05-21 19:55:55 -03:00
9dd8da11d4
It's just a high-latency file...
2021-05-21 13:53:06 -04:00
4472e6e81c
Move v3 to v2 because they are identical, but replace with f7x variant due to better docs.
2021-05-21 13:45:52 -04:00
3c43f87999
Merge pull request #26 from lulf/stm32l0-rcc
...
Add RCC register block for STM32L0
2021-05-21 17:59:46 +02:00
8ea824f9b7
Merge pull request #27 from bobmcwhirter/i2c
...
Add I2C v3 (l4+/h7)
2021-05-21 17:52:07 +02:00
9ff282e2a4
Add I2C v3 (l4+/h7)
2021-05-21 11:49:09 -04:00
2ff87b75ce
Add RCC register block for STM32L0
2021-05-20 13:26:25 +02:00
da67ddf088
Merge pull request #25 from lulf/stm32l0-syscfg
...
Add SYSCFG register mapping for stm32l0 family
2021-05-19 11:22:33 +02:00
a942bdfbad
Add SYSCFG register mapping for stm32l0 family
2021-05-19 10:31:58 +02:00
af21df21a5
Extract SPIv3 minus I2S.
2021-05-17 09:40:43 -04:00
abf5d3f2a2
Add usart v2
2021-05-17 01:53:12 +02:00
5e59f22819
dma_v2: merge ISR and IFCR fieldsets
2021-05-16 02:53:43 +02:00
74ab5e93c8
Implement h7 syscfg
2021-05-08 00:43:48 -03:00
997900038d
Add SPI v1.
2021-05-07 15:55:48 -04:00
350d7cb38d
Merge pull request #16 from bobmcwhirter/spi_v2
...
SPI v2 first draft.
2021-05-07 20:37:37 +02:00
1a7fde6868
Better SPI v2.
2021-05-07 13:43:48 -04:00
0de8be5be4
SPI v2 first draft.
2021-05-07 11:27:36 -04:00
b993c3ad41
Fix arrayizing problem in transform
2021-05-05 23:22:40 -03:00
8202642b61
Initial sdmmc_v2 support
2021-05-05 23:22:40 -03:00
