guangzong/stm32-data
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4 Commits

Author SHA1 Message Date
Michael Zill
b782384611 Arrayfied IER, ICR, ISR and MISR 
IRQ registers have for all 4 variants the same name.
V1 - array size = 2 (2 cores)
V2 - array size = 1 (1 core)
V3 - array size = 2 (2 cores)
V4 - array size = 1 (1 core)

HSEM added to GHOST_PERIS
 2024-04-08 13:38:36 +02:00
Michael Zill
840e5ec5db Fixed length COREID in v1, v2 renamed MASTERID to COREID 2024-04-08 13:36:40 +02:00
Michael Zill
e029a55f7a Arrayfied v2, v3, v4 - removed enums, aligned yaml structure 
The following list shows the different hsem yaml versions and the coresponding chips.

    wba is on purpose not included at is complex and very different from the others which will
    also make the HSEM implementation in the HAL more complex. I leave this out for another PR.

    h747
    wb55

    h735
    h7b3
    h753v
    h753
    h743
    h743v

    wl5x_cm0p
    wl5x_cm4

    wle5
 2024-04-08 13:36:40 +02:00
Michael Zill
44967f3776 Initial add 2024-04-08 13:36:40 +02:00