Adam Greig
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544184c70e
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rcc: add override so SAI23SEL is used
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2024-03-09 18:53:48 +00:00 |
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Torin Cooper-Bennun
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d1f376978d
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fix ADC, DAC clock muxes for H5, U5
the clock selection bit is named ADCDACSEL, shared between all ADCs and
DACs
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2024-03-04 10:52:06 +00:00 |
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Dario Nieuwenhuis
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59bb84fbcb
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rcc/c0: fix HSI -> HSISYS/HSIKER
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2024-03-03 23:50:04 +01:00 |
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Dario Nieuwenhuis
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d67103f97f
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More accurate USB muxes.
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2024-03-01 22:50:31 +01:00 |
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Eli Orona
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4ed2d3f65a
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Update rcc.rs
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2024-02-25 16:16:25 -08:00 |
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Dario Nieuwenhuis
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87b06bac89
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rcc: separate fields for bus and kernel clock.
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2024-02-16 01:07:41 +01:00 |
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Dario Nieuwenhuis
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917db8f71e
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Do not lowercase clock names.
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2024-02-16 00:26:37 +01:00 |
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Dario Nieuwenhuis
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e2c7a7eae0
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rcc: fix tons of wrong muxes.
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2024-02-16 00:11:14 +01:00 |
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Dario Nieuwenhuis
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8010c4e7b8
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cleanup rcc code a bit more.
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2024-02-14 00:30:23 +01:00 |
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Dario Nieuwenhuis
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5bf4bec597
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rcc: more generous fallback stripping all peripheral numbers.
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2024-02-10 02:48:24 +01:00 |
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Dario Nieuwenhuis
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0c921dde2e
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Refactor RCC code to find more muxes.
Fixes #383
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2024-02-10 02:40:36 +01:00 |
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Dario Nieuwenhuis
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dffe8dacce
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Add clock mux for F4 and F7.
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2024-02-02 02:15:32 +01:00 |
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Dario Nieuwenhuis
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fcdcb0471b
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Fix missing DAC RCC on H7.
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2024-02-01 23:40:12 +01:00 |
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Dario Nieuwenhuis
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c6ad5e265a
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cleanup rcc bit matching.
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2024-02-01 23:36:45 +01:00 |
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eZio Pan
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d20904a208
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refactor with clippy
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2023-12-24 19:07:32 +08:00 |
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Sam
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1cc9a2fcca
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limit ADC1 clocks fallback for stm32l series
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2023-12-08 18:55:54 +01:00 |
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Sam
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08c1f451b6
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ADC stm32l151c8 specifics
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2023-12-08 18:55:53 +01:00 |
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Torin Cooper-Bennun
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90ff5316eb
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rcc: fix FDCAN: multiple FDCANs share the same RCC fields
the RCC fields are named either FDCAN or FDCAN12
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2023-11-21 10:45:51 +00:00 |
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Dario Nieuwenhuis
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c551c07bf1
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rcc: consistency fixes.
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2023-11-13 01:00:53 +01:00 |
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xoviat
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b9efaf36d8
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add stop mode rcc data
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2023-11-05 15:52:50 -06:00 |
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Dario Nieuwenhuis
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b59a5c1812
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rcc: add missing enums to wb, wl.
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2023-10-23 00:30:16 +02:00 |
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xoviat
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8fecdeff9c
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rcc: solve hashmap determinism for good
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2023-10-20 18:43:46 -05:00 |
|
xoviat
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39e82b76a4
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rcc: solve data mutability
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2023-10-19 21:01:17 -05:00 |
|
xoviat
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8bd7ff51b0
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rcc: expand checker to all chips
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2023-10-18 21:01:57 -05:00 |
|
xoviat
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3d9c8b70e3
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rcc: check l4plus and l5
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2023-10-17 17:21:06 -05:00 |
|
xoviat
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c61495fd4e
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rcc: more cleanup
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2023-10-17 16:57:33 -05:00 |
|
xoviat
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fb84c0ac55
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rcc: fixup clock names and expand checking
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2023-10-16 17:53:26 -05:00 |
|
xoviat
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b9a89a1851
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rcc: cleanup variants and rename ahb -> clk
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2023-10-15 18:01:50 -05:00 |
|
xoviat
|
8b8686a852
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rcc: more mux and enum cleanup
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2023-10-15 10:37:36 -05:00 |
|
xoviat
|
5d51e3b706
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rcc: add more mux data
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2023-10-14 17:20:25 -05:00 |
|
xoviat
|
68d77f487b
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rcc: add more mux data
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2023-10-14 11:41:21 -05:00 |
|
xoviat
|
8a09bbb62c
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rcc: more cleanup
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2023-10-13 22:20:18 -05:00 |
|
xoviat
|
aa5e909e11
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rcc: more enum cleanup
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2023-10-13 20:54:24 -05:00 |
|
xoviat
|
c4cd46927d
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rcc: rename h5 clock enum variants and add check
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2023-10-12 20:48:35 -05:00 |
|
xoviat
|
421c595a13
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rcc: lower reg data
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2023-10-08 18:05:16 -05:00 |
|
xoviat
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61c9f8c691
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rcc: fix mux determinism
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2023-10-08 15:43:06 -05:00 |
|
xoviat
|
1595920962
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rcc: pipe through sel mux
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2023-09-25 19:26:46 -05:00 |
|
xoviat
|
604ea4029c
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generate rccperipheral for rtc
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2023-09-25 15:57:52 -05:00 |
|
xoviat
|
d71fac77e6
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g4: fix rcc adc generation
|
2023-09-11 15:55:53 -05:00 |
|
Don Reilly
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7b0a28e989
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fixed missing edge case
|
2023-08-09 10:34:10 -05:00 |
|
Don Reilly
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f4e0487ae5
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map all (most?) edge cases of ADC
|
2023-08-08 15:15:36 -05:00 |
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Dario Nieuwenhuis
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b96d1bddd3
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Add H5, and newer U5s.
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2023-03-27 12:17:53 +02:00 |
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Dario Nieuwenhuis
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a2333b8afb
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New repo structure: includes stm32-metapac, doesn't commit generated files.
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2023-03-20 01:56:23 +01:00 |
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