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Author SHA1 Message Date
Dario Nieuwenhuis
d260d9f2cf remove gpio_af 2021-06-23 02:34:00 +02:00
Dario Nieuwenhuis
29f70ac45f Add DMAMUX 2021-06-23 02:30:55 +02:00
Dario Nieuwenhuis
983fa80ef3 Merge pull request #50 from bobmcwhirter/dma 
DMA
 2021-06-23 00:47:11 +02:00
Dario Nieuwenhuis
ac4feed6b2 Merge pull request #49 from embassy-rs/f0-rcc 
F0 rcc, flash and syscfg
 2021-06-22 23:57:12 +02:00
Thales Fragoso
6656c5c059 Add F0 syscfg 2021-06-22 23:53:50 +02:00
Thales Fragoso
26e4f541ba Add F0 FLASH 2021-06-22 23:53:50 +02:00
Thales Fragoso
ae8455a336 Add F0 RCCs 2021-06-22 23:53:37 +02:00
Dario Nieuwenhuis
9c5e1072d8 Merge pull request #48 from Tiwalun/smt32wb55-exti 
Add EXTI and IPCC for STM32WB55
 2021-06-22 23:50:00 +02:00
Bob McWhirter
93900325cb Adjust parse.py to include DMA channel/request per chip and peripheral. 2021-06-22 10:23:57 -04:00
Dominik Boehi
51395f941a Use arrays and blocks for everything in EXTI 2021-06-21 19:13:26 +02:00
Dominik Boehi
481e607977 Add IPCC peripheral to STM32WB55 2021-06-21 19:13:24 +02:00
Dominik Boehi
454854d527 Add EXTI for STM32WB55 2021-06-21 19:12:00 +02:00
Dario Nieuwenhuis
77d4ae203b Add DBGMCU for all chips 2021-06-21 01:27:36 +02:00
Dario Nieuwenhuis
a39cc5e6d2 Merge pull request #47 from lulf/dual-core 
Add support for parsing dual core chips
 2021-06-16 16:24:40 +02:00
Ulf Lilleengen
3ef6421aa8 Add more peripherals for wl5x 2021-06-16 16:07:00 +02:00
Ulf Lilleengen
9161dbcac9 Regenerate with dual core support 
* Add support for WL55 chip family
 2021-06-16 15:10:42 +02:00
Ulf Lilleengen
d4fad162ac Add support for parsing dual core chips 
This modifies the chip format to include an array of cores, and within
each core the interrupts and peripherals for that core.
 2021-06-16 15:10:02 +02:00
Dario Nieuwenhuis
83b10acc02 Merge pull request #46 from bobmcwhirter/adc_common_more_families 
Adc common more families
 2021-06-14 19:28:35 +02:00
Bob McWhirter
c511da9664 And WB55 VREFINT. 2021-06-14 11:56:04 -04:00
Bob McWhirter
dea6d819dd Add VREFINT for STM32L4 family and reparse. 2021-06-14 11:43:49 -04:00
Bob McWhirter
6cdfc6c1e8 Better parsing around ADC_COMMON base addr. 2021-06-14 11:43:48 -04:00
Dario Nieuwenhuis
e478047c78 Merge pull request #45 from embassy-rs/eth-v2 
Eth v2
 2021-06-13 20:54:17 +02:00
Thales Fragoso
6a6eed71a5 eth-v2: Remove separate eth dma and mac 2021-06-13 08:17:21 -03:00
Thales Fragoso
a7b126b078 eth-v2: Fix descriptors address fields 2021-06-13 08:16:11 -03:00
Dario Nieuwenhuis
8e71f3da8e Merge pull request #44 from Tiwalun/stm32wb55-support 
Add RCC and SYSCFG for STM32WB55
 2021-06-11 22:46:34 +02:00
Dominik Boehi
6c872019d0 Add RCC and SYSCFG for STM32WB55 2021-06-11 22:36:40 +02:00
Dario Nieuwenhuis
bd443787e2 Merge pull request #43 from bobmcwhirter/adc_v3_take2 
Adc v3 take2
 2021-06-11 12:10:02 +02:00
Thales Fragoso
e3cc9b041c Add a single yaml for eth_v2 2021-06-11 00:15:56 -03:00
Thales Fragoso
2d0ecd1ec0 Add ethernet (v2) dma and mac 2021-06-11 00:15:56 -03:00
Bob McWhirter
f202deb4c1 Add some enums to ADC fields. 2021-06-10 15:33:17 -04:00
Bob McWhirter
b7c071aa71 Clean up a bit. 2021-06-10 10:38:02 -04:00
Bob McWhirter
fc64e88b92 Extract ADCv3 (arrayification is not possible, slight diffs in field widths) 
Extract ADC_COMMON
Create framework for extra synthetic hand-crafted peripherals.
Add VREFINTCAL reg/block/peripheral for STM32L4+.
 2021-06-10 10:38:02 -04:00
Bob McWhirter
23fed4339b ADC v3 attempt #2. 2021-06-10 10:37:32 -04:00
Ulf Lilleengen
af3e9e60a3 Add missing RCC block for H7AB family 2021-06-10 08:57:46 +02:00
Dario Nieuwenhuis
4837bee5df Remove reference to nonexistent rcc_h7ab 2021-06-10 03:00:05 +02:00
Dario Nieuwenhuis
767e8d93f8 Merge pull request #42 from bobmcwhirter/more_dac 
More dac
 2021-06-08 21:08:31 +02:00
Bob McWhirter
0619fbc974 Add another regexp for DAC. 2021-06-08 15:04:58 -04:00
Dario Nieuwenhuis
978efded08 Merge pull request #41 from lulf/add-missing-clock-h7spi6 
Add missing clock selection for SPI6
 2021-06-08 16:51:14 +02:00
Ulf Lilleengen
fe163b5ab1 Add missing SPI6 clock for all H7 family 2021-06-08 16:49:51 +02:00
Ulf Lilleengen
e83e6824e5 Merge pull request #40 from lulf/minor-reg-fixes 
Minor register fixes for RCC L4
 2021-06-07 15:32:19 +02:00
Ulf Lilleengen
e58aa40b74 Minor register fixes for RCC L4 2021-06-07 15:31:44 +02:00
Dario Nieuwenhuis
33baa6c918 Merge pull request #39 from lulf/add-rcc-f4 
Add RCC register for F4, L4
 2021-06-07 14:40:05 +02:00
Ulf Lilleengen
06fd321be1 Fix regs 2021-06-07 13:50:49 +02:00
Ulf Lilleengen
5f350c7c25 Fix duplicate regs 2021-06-07 12:41:13 +02:00
Ulf Lilleengen
c1aae8d3d8 Run through transform again 2021-06-07 12:22:09 +02:00
Ulf Lilleengen
1d0b8db2ee Regen and update transform 2021-06-07 12:03:15 +02:00
Ulf Lilleengen
f31ba7bfcb Separate block for H7AB 2021-06-03 15:43:21 +02:00
Ulf Lilleengen
fea5e31f8b Regen and remove *ON enums 2021-06-03 15:13:46 +02:00
Ulf Lilleengen
ec2f881773 Readd 2021-06-03 14:31:34 +02:00
Ulf Lilleengen
529b991404 Do merge 2021-06-03 14:31:27 +02:00