Lucas Granberg
|
90b8b692b7
|
add comp v3 to STM32WL (non E)
|
2024-02-07 15:37:57 +02:00 |
|
Lucas Granberg
|
8c8af96abd
|
add comp_v3 and apply to stm32wl
|
2024-02-07 14:55:12 +02:00 |
|
shufps
|
2f59dea33f
|
cargo fmt
|
2024-02-07 09:02:18 +01:00 |
|
shufps
|
7c7194d546
|
adds adc support for L0
|
2024-02-07 08:57:52 +01:00 |
|
Dario Nieuwenhuis
|
f0101a2249
|
Merge pull request #377 from AdinAck/main
[READY NOW!] Initial Comparator Support
|
2024-02-06 16:59:03 +00:00 |
|
Dario Nieuwenhuis
|
5674011dd7
|
Merge pull request #379 from caleb-garrett/hash
Corrected hash v3 register arrays
|
2024-02-06 00:04:14 +00:00 |
|
Caleb Garrett
|
44c579f350
|
Corrected hash v3 array lengths.
|
2024-02-05 18:35:15 -05:00 |
|
eZio Pan
|
e857389850
|
Add OR register.
OR1 is the same as OR. The content is different across chip serials. Leave entire register to HAL to parse.
OR2 and OR3 are just AF1 and AF2.
|
2024-02-05 16:27:10 +08:00 |
|
eZio Pan
|
b3871b47d8
|
mapping bug fix
|
2024-02-05 16:27:10 +08:00 |
|
eZio Pan
|
eb88e4bfb6
|
tailoring from timer_v1 to timer_l0
|
2024-02-05 16:27:10 +08:00 |
|
eZio Pan
|
281787fbb1
|
branch timer_l0 from timer_v1
|
2024-02-05 16:27:10 +08:00 |
|
eZio Pan
|
9fa345af29
|
add TIM_BASIC_NO_CR2, common part of TIM_BASIC and TIM_1CH_CMP
|
2024-02-05 16:27:10 +08:00 |
|
eZio Pan
|
10a1a61bae
|
let TIM_ADV based on TIM_2CH_CMP
|
2024-02-05 16:27:10 +08:00 |
|
eZio Pan
|
cd490fd7f3
|
let TIM_GP16 based on TIM_2CH
|
2024-02-05 16:27:10 +08:00 |
|
eZio Pan
|
6b5e0c6b4e
|
add TIM_CORE, common part of TIM_BASIC and TIM_1CH
|
2024-02-05 16:27:10 +08:00 |
|
eZio Pan
|
db6e501fd3
|
make 2CH_CMP based on 1CH_CMP
|
2024-02-05 16:27:10 +08:00 |
|
eZio Pan
|
771c51b438
|
bug fix
|
2024-02-05 16:27:10 +08:00 |
|
eZio Pan
|
982b30aa6a
|
update timer mapping
|
2024-02-05 16:27:10 +08:00 |
|
eZio Pan
|
abb0f63c4a
|
tailoring timer_v1 from timer_v2
|
2024-02-05 16:27:10 +08:00 |
|
eZio Pan
|
81d09e5782
|
branch timer_v1 from timer_v2
|
2024-02-05 16:27:10 +08:00 |
|
eZio Pan
|
ab11ed85fb
|
remove redundant CCR fieldset, and bug fix
|
2024-02-05 16:27:10 +08:00 |
|
eZio Pan
|
7518e37532
|
merge all TIMs into timer_v2
|
2024-02-05 16:27:10 +08:00 |
|
eZio Pan
|
1b83acf50b
|
ch2_cmp, ch2, ch1_cmp, ch1 merged
|
2024-02-05 16:27:10 +08:00 |
|
eZio Pan
|
0ed4c863d2
|
1ch_cmp, 1ch merged
|
2024-02-05 16:27:10 +08:00 |
|
eZio Pan
|
d2ec8c049c
|
2ch_cmp, 2ch, 1ch merged
|
2024-02-05 16:27:10 +08:00 |
|
eZio Pan
|
864e7a7078
|
2ch_cmp, 2ch merged
|
2024-02-05 16:27:10 +08:00 |
|
eZio Pan
|
65a7e873c6
|
adv, gp16, gp32, basic merged
|
2024-02-05 16:27:10 +08:00 |
|
eZio Pan
|
a3e7e74535
|
adv, gp16, gp32 merged
|
2024-02-05 16:27:10 +08:00 |
|
eZio Pan
|
6eba236ede
|
adv, gp16 merged
|
2024-02-05 16:27:10 +08:00 |
|
eZio Pan
|
9ede4ad2c0
|
merging adv, gp16
|
2024-02-05 16:27:10 +08:00 |
|
eZio Pan
|
cb85778273
|
naming block, as start point of merging
|
2024-02-05 16:27:10 +08:00 |
|
eZio Pan
|
6356128ba2
|
tailoring from tim2chcmp to timbasic
|
2024-02-05 16:27:10 +08:00 |
|
eZio Pan
|
0096f150c0
|
branch from tim2chcmp to timbasic
|
2024-02-05 16:27:10 +08:00 |
|
eZio Pan
|
8c321f182c
|
tailoring from tim2chcmp to tim1chcmp
|
2024-02-05 16:27:10 +08:00 |
|
eZio Pan
|
b4d5936b9b
|
branch from tim2chcmp to tim1chcmp
|
2024-02-05 16:27:10 +08:00 |
|
eZio Pan
|
8361dffb8d
|
bug fix
|
2024-02-05 16:27:10 +08:00 |
|
eZio Pan
|
75011dc243
|
tailoring from tim2ch to tim1ch
|
2024-02-05 16:27:10 +08:00 |
|
eZio Pan
|
1e35b09edf
|
tailoring from tim2chcmp to tim2ch
|
2024-02-05 16:27:10 +08:00 |
|
eZio Pan
|
dd1d4c772b
|
branch from tim2chcmp to tim2ch
|
2024-02-05 16:27:10 +08:00 |
|
eZio Pan
|
8c0ab318ca
|
tailoring form timadv to tim2chcmp
|
2024-02-05 16:27:10 +08:00 |
|
eZio Pan
|
4bdc25368f
|
branch from timadv to tim2chcmp
|
2024-02-05 16:27:10 +08:00 |
|
eZio Pan
|
0bb68b7dcb
|
bug fix
|
2024-02-05 16:27:10 +08:00 |
|
eZio Pan
|
6e36b80628
|
tailoring from gp16 to gp32
|
2024-02-05 16:27:10 +08:00 |
|
eZio Pan
|
864508ced7
|
branching gp32 from gp16
|
2024-02-05 16:27:10 +08:00 |
|
eZio Pan
|
ffd1d9a48f
|
redesign access at dither mode
|
2024-02-05 16:27:10 +08:00 |
|
eZio Pan
|
ee78a5d925
|
tailoring from adv to gp16
|
2024-02-05 16:27:10 +08:00 |
|
eZio Pan
|
033aaaecb3
|
branch gp16 from adv
|
2024-02-05 16:27:10 +08:00 |
|
eZio Pan
|
70282b4d94
|
timadv, enum level
|
2024-02-05 16:27:10 +08:00 |
|
eZio Pan
|
1cd8d830f3
|
timadv, fieldset level
|
2024-02-05 16:27:10 +08:00 |
|
eZio Pan
|
396ccfda7d
|
timadv, block level
|
2024-02-05 16:27:10 +08:00 |
|