eZio Pan
|
868dec1630
|
timer: add 16-bit register info
|
2024-03-13 01:11:26 +08:00 |
|
eZio Pan
|
cc525f1b25
|
timer: remove PSC fieldset
|
2024-03-13 01:06:29 +08:00 |
|
eZio Pan
|
d9353ac72e
|
tim fix: move BIE from GP16 to ADV
|
2024-02-28 16:29:03 +08:00 |
|
eZio Pan
|
ecbb085fdf
|
remove non-exist ECR register from timer_v1 and timer_l0
|
2024-02-23 21:57:20 +08:00 |
|
eZio Pan
|
e857389850
|
Add OR register.
OR1 is the same as OR. The content is different across chip serials. Leave entire register to HAL to parse.
OR2 and OR3 are just AF1 and AF2.
|
2024-02-05 16:27:10 +08:00 |
|
eZio Pan
|
eb88e4bfb6
|
tailoring from timer_v1 to timer_l0
|
2024-02-05 16:27:10 +08:00 |
|
eZio Pan
|
281787fbb1
|
branch timer_l0 from timer_v1
|
2024-02-05 16:27:10 +08:00 |
|