Adin Ackerman
675a67c3af
add comparators to G0 and G4
2024-01-30 15:57:55 -08:00
Caleb Garrett
0ec4390269
Corrected cryp perimap.
2024-01-30 09:46:13 -05:00
Caleb Garrett
d3663f608b
Added cryp perimap.
2024-01-29 21:48:24 -05:00
Dario Nieuwenhuis
67a5ba0be1
Merge pull request #375 from caleb-garrett/hash
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Add HASH
2024-01-30 01:55:55 +00:00
Carlos Barrales Ruiz
b14a4f1f18
Fix UART definitions present in STM32F1 series (sci2_v1_1)
2024-01-30 01:01:13 +01:00
Caleb Garrett
6fae02614a
Added hash registers and perimap.
2024-01-29 18:48:07 -05:00
Taylor Carpenter
136f53de04
Match all versions of CRC by chip family
2024-01-28 20:11:54 -05:00
Taylor Carpenter
2acb6a4682
Fix crc version mapping
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CRC version mapping is now done by family before failing back to the IP version listed in MCU XML
Versions now match what is on spreadsheet
2024-01-27 00:55:33 -05:00
Cryowatt
33331ec8e2
Adding SAI 1.2 mapping to PERIMAP
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Adding registers for sai_v1_2
Transformed and cleaned
Adding SAI 1.2 mapping to PERIMAP
v5 was the same as v2, deleting v5
Removed trailing whitespace
2024-01-26 16:13:23 -08:00
Karun
64a23e1213
update perimap for stm32u5[34]5 octospi implementations
2024-01-23 15:55:19 -05:00
eZio Pan
f0d25d27c6
make eth mapping more precise
2024-01-22 20:31:56 +08:00
eZio Pan
7131cf46dd
apply chiptool validate on yaml parse
2024-01-08 16:30:57 +08:00
Tyler Gilbert
59598d3ff8
Add cordic to all MCUs that have it. Read/write WDATA/RDATA directly for ease of use
2024-01-07 15:16:08 -06:00
Tyler Gilbert
ce5c765eed
add cordic_v1 for stm32u5
2024-01-03 21:05:54 -06:00
Dario Nieuwenhuis
617ad260f5
Merge pull request #343 from tyler-gilbert/add-icache-v1-for-stm32u5
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Add icache_v1 for use with STM32U5
2024-01-04 00:57:57 +00:00
Tyler Gilbert
f7ad1d5b0f
Add icache_v1 for use with STM32U5
2024-01-03 18:09:28 -06:00
Tyler Gilbert
b133fdbc97
Add support for ADF_v1 available on STM32U5
2024-01-03 16:28:25 -06:00
Dario Nieuwenhuis
a535002553
Merge pull request #325 from chrenderle/main
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Add rtc registers for stm32l5
2024-01-01 21:11:26 +00:00
Christian Enderle
0ddf28abe3
dbgmcu: add support for stm32l5
2023-12-28 11:11:40 +01:00
Christian Enderle
28306c1d75
Added rtc registers for stm32l5
2023-12-26 11:32:15 +01:00
eZio Pan
d20904a208
refactor with clippy
2023-12-24 19:07:32 +08:00
Dario Nieuwenhuis
3634020845
Fix qspi for all chips.
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Co-Authored-By: Tupelov <64274155+Tupelov@users.noreply.github.com>
2023-12-08 21:54:03 +01:00
Sam
830341361e
STM32L1 to use ADC1 address instead of incorrect ADC address
2023-12-08 18:55:54 +01:00
Sam
08c1f451b6
ADC stm32l151c8 specifics
2023-12-08 18:55:53 +01:00
Sam
b53fd35116
ADC afit_v1_1 implementation
2023-12-08 18:55:38 +01:00
Dario Nieuwenhuis
b6181ce3f3
Merge pull request #308 from tcbennun/fdcan-fix
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fdcan: add H7 support; fix regs for others; add message RAM blocks
2023-12-08 17:21:24 +00:00
Torin Cooper-Bennun
27c71ac451
fdcan: generate register blocks for message RAM
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this is a special case, as most data sources don't mention this as a
separate peripheral at all, and those that do don't handle the offsets
in the case of multiple FDCANS
H7 chips have a single 10KB block shared between all FDCANs
2023-11-21 10:45:51 +00:00
Torin Cooper-Bennun
f65fd694e1
fdcan: fix register block definitions; separate version for H7
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the Cube XMLs refer to "fdcan_v1_0" and "fdcan_v1_1" but these seem to
have no bearing on the actual registers used. Thus chips.rs should make
no distinction between v1_0 and v1_1.
the previous YAML seems to have been generated from a G4 SVD, but this
series' SVDs consistently have several errata.
I have therefore replaced can_fdcan.yaml with can_fdcan_v1.yaml, built
from an H5 SVD which appears to match the RMs of G0, G4, H5 and L5
chips.
the H7 series has a totally different FDCAN, so I've added a separate
YAML for it.
2023-11-21 10:45:51 +00:00
Adam Greig
78232c013e
Rework DACs for all STM32
2023-11-19 04:51:20 +00:00
Adam Greig
7ce7dc901f
Add DACv4 support for STM32G4
2023-11-19 04:51:19 +00:00
Dario Nieuwenhuis
221d24f6f8
Parse interrupts on demand for each chip instead of upfront.
2023-11-17 23:42:07 +01:00
Dario Nieuwenhuis
8381654ade
crs: add for l5.
2023-11-05 23:37:05 +01:00
Dario Nieuwenhuis
e78c8c9d94
crs: add for all chips.
2023-11-05 23:12:27 +01:00
Dario Nieuwenhuis
cf3f969fe8
Add stm32wba spi.
2023-10-22 22:31:20 +02:00
Olle Sandberg
9f019bd9ba
wwdg: register definitions for window watchdog v2
2023-10-19 14:49:41 +02:00
JackN
47a5753bef
TSC: Add new TSCperipheral to perimap
2023-10-16 10:25:09 -04:00
Dario Nieuwenhuis
9330e31117
rng: add wb support.
2023-10-16 04:58:26 +02:00
Dario Nieuwenhuis
73e3f8a965
rcc: separate L4 and L4+
2023-10-16 03:11:00 +02:00
JackN
0f0517404e
GFXMMU: Add new peripherals to perimap
2023-10-13 17:12:57 -04:00
JackN
af1a5f5877
OCTOSPI: Merge peri yamls
2023-10-12 17:44:41 -04:00
JackN
e99c97f0f6
OCTOSPI: Merge peripheral yamls and consolidate enums
2023-10-12 15:43:04 -04:00
JackN
2ab8cf7d44
Remove blanket matches from perimap
2023-10-12 10:45:54 -04:00
JackN
dc7bc1272a
Add OCTOSPIM and OCTOSPI to perimap
2023-10-12 10:24:00 -04:00
Dario Nieuwenhuis
6bfa5a0dce
rtc/bd fixes.
2023-10-11 03:41:10 +02:00
Dario Nieuwenhuis
f40f5a40c1
Not all L0s have HSI48/CRS.
2023-10-11 01:21:26 +02:00
Dario Nieuwenhuis
a7bf7f02d1
Fix MCO/MCO1 inconsistency in G0, C0.
2023-10-07 01:13:03 +02:00
xoviat
e7a291e659
sort pins by key
2023-10-05 20:04:58 -05:00
xoviat
2271da1671
Merge branch 'main' of https://github.com/embassy-rs/stm32-data into h7-lsedrv-errata
2023-10-05 19:30:38 -05:00
xoviat
ab12bb45b1
sort pins to avoid diff
2023-10-05 19:08:51 -05:00
Matt Ickstadt
568a7058a1
Create rcc_h7rm04ee.yaml as a copy of rcc_h7.yaml
2023-10-05 10:35:43 -05:00
