Adam Greig
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78232c013e
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Rework DACs for all STM32
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2023-11-19 04:51:20 +00:00 |
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Adam Greig
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7ce7dc901f
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Add DACv4 support for STM32G4
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2023-11-19 04:51:19 +00:00 |
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Dario Nieuwenhuis
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f6d1ffc1a2
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Fix G0 USB interrupts.
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2023-11-18 01:39:07 +01:00 |
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Dario Nieuwenhuis
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4852f5040a
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Ensure no duplicate irqs with the same signal.
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2023-11-18 00:39:24 +01:00 |
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Dario Nieuwenhuis
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f5a4c58efa
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Remove USB_DRD_FS rename hack.
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2023-11-18 00:00:14 +01:00 |
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Dario Nieuwenhuis
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f0866ffbc4
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Check for non-existing interrupts earlier.
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2023-11-17 23:55:55 +01:00 |
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Dario Nieuwenhuis
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221d24f6f8
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Parse interrupts on demand for each chip instead of upfront.
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2023-11-17 23:42:07 +01:00 |
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Dario Nieuwenhuis
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c551c07bf1
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rcc: consistency fixes.
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2023-11-13 01:00:53 +01:00 |
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Dario Nieuwenhuis
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8381654ade
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crs: add for l5.
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2023-11-05 23:37:05 +01:00 |
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xoviat
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04d773b7b3
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Merge pull request #303 from xoviat/low-power
add stop mode rcc data
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2023-11-05 22:29:38 +00:00 |
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Dario Nieuwenhuis
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e78c8c9d94
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crs: add for all chips.
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2023-11-05 23:12:27 +01:00 |
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xoviat
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b9efaf36d8
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add stop mode rcc data
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2023-11-05 15:52:50 -06:00 |
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Dario Nieuwenhuis
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b59a5c1812
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rcc: add missing enums to wb, wl.
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2023-10-23 00:30:16 +02:00 |
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Dario Nieuwenhuis
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cf3f969fe8
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Add stm32wba spi.
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2023-10-22 22:31:20 +02:00 |
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xoviat
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8fecdeff9c
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rcc: solve hashmap determinism for good
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2023-10-20 18:43:46 -05:00 |
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xoviat
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39e82b76a4
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rcc: solve data mutability
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2023-10-19 21:01:17 -05:00 |
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Olle Sandberg
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9f019bd9ba
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wwdg: register definitions for window watchdog v2
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2023-10-19 14:49:41 +02:00 |
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xoviat
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8bd7ff51b0
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rcc: expand checker to all chips
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2023-10-18 21:01:57 -05:00 |
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xoviat
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3d9c8b70e3
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rcc: check l4plus and l5
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2023-10-17 17:21:06 -05:00 |
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xoviat
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c61495fd4e
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rcc: more cleanup
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2023-10-17 16:57:33 -05:00 |
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xoviat
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fb84c0ac55
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rcc: fixup clock names and expand checking
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2023-10-16 17:53:26 -05:00 |
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JackN
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47a5753bef
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TSC: Add new TSCperipheral to perimap
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2023-10-16 10:25:09 -04:00 |
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Dario Nieuwenhuis
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9330e31117
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rng: add wb support.
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2023-10-16 04:58:26 +02:00 |
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Dario Nieuwenhuis
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73e3f8a965
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rcc: separate L4 and L4+
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2023-10-16 03:11:00 +02:00 |
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xoviat
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b9a89a1851
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rcc: cleanup variants and rename ahb -> clk
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2023-10-15 18:01:50 -05:00 |
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xoviat
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8b8686a852
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rcc: more mux and enum cleanup
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2023-10-15 10:37:36 -05:00 |
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xoviat
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5d51e3b706
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rcc: add more mux data
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2023-10-14 17:20:25 -05:00 |
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xoviat
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68d77f487b
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rcc: add more mux data
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2023-10-14 11:41:21 -05:00 |
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xoviat
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b14427f2d1
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Merge branch 'main' of https://github.com/embassy-rs/stm32-data into rcc
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2023-10-13 22:22:05 -05:00 |
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xoviat
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8a09bbb62c
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rcc: more cleanup
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2023-10-13 22:20:18 -05:00 |
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xoviat
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e90a83a4f0
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Merge pull request #281 from noppej/gfxmmu
Add GFXMMU peripheral
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2023-10-14 02:26:15 +00:00 |
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xoviat
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aa5e909e11
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rcc: more enum cleanup
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2023-10-13 20:54:24 -05:00 |
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JackN
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0f0517404e
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GFXMMU: Add new peripherals to perimap
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2023-10-13 17:12:57 -04:00 |
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xoviat
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c4cd46927d
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rcc: rename h5 clock enum variants and add check
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2023-10-12 20:48:35 -05:00 |
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JackN
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af1a5f5877
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OCTOSPI: Merge peri yamls
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2023-10-12 17:44:41 -04:00 |
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JackN
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e99c97f0f6
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OCTOSPI: Merge peripheral yamls and consolidate enums
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2023-10-12 15:43:04 -04:00 |
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JackN
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2ab8cf7d44
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Remove blanket matches from perimap
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2023-10-12 10:45:54 -04:00 |
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JackN
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dc7bc1272a
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Add OCTOSPIM and OCTOSPI to perimap
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2023-10-12 10:24:00 -04:00 |
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Dario Nieuwenhuis
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6bfa5a0dce
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rtc/bd fixes.
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2023-10-11 03:41:10 +02:00 |
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Dario Nieuwenhuis
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f40f5a40c1
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Not all L0s have HSI48/CRS.
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2023-10-11 01:21:26 +02:00 |
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xoviat
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421c595a13
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rcc: lower reg data
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2023-10-08 18:05:16 -05:00 |
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xoviat
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61c9f8c691
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rcc: fix mux determinism
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2023-10-08 15:43:06 -05:00 |
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Dario Nieuwenhuis
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a7bf7f02d1
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Fix MCO/MCO1 inconsistency in G0, C0.
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2023-10-07 01:13:03 +02:00 |
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xoviat
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e7a291e659
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sort pins by key
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2023-10-05 20:04:58 -05:00 |
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xoviat
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2271da1671
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Merge branch 'main' of https://github.com/embassy-rs/stm32-data into h7-lsedrv-errata
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2023-10-05 19:30:38 -05:00 |
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xoviat
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ab12bb45b1
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sort pins to avoid diff
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2023-10-05 19:08:51 -05:00 |
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Matt Ickstadt
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568a7058a1
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Create rcc_h7rm04ee.yaml as a copy of rcc_h7.yaml
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2023-10-05 10:35:43 -05:00 |
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xoviat
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06d13dfd24
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Merge pull request #267 from oll3/tamp_block
add TAMP register block for g0, g4, l5, u5 and wl
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2023-10-02 21:00:10 +00:00 |
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Dario Nieuwenhuis
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4baa9a0079
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Merge pull request #265 from xoviat/sel
rcc: pipe through sel mux and generate ir
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2023-10-02 20:40:01 +00:00 |
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xoviat
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92ae3d5870
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optimize hashset gen.
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2023-10-01 13:44:30 -05:00 |
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