Karun Koppula
505f4dabf5
Fix register address mapping
2024-01-26 19:36:41 -05:00
Dario Nieuwenhuis
46e3f5fe3a
gen/header: less strict irq parsing, it was missing some irqs.
2024-01-03 02:00:23 +01:00
Dario Nieuwenhuis
3634020845
Fix qspi for all chips.
...
Co-Authored-By: Tupelov <64274155+Tupelov@users.noreply.github.com>
2023-12-08 21:54:03 +01:00
Sam
08c1f451b6
ADC stm32l151c8 specifics
2023-12-08 18:55:53 +01:00
Torin Cooper-Bennun
27c71ac451
fdcan: generate register blocks for message RAM
...
this is a special case, as most data sources don't mention this as a
separate peripheral at all, and those that do don't handle the offsets
in the case of multiple FDCANS
H7 chips have a single 10KB block shared between all FDCANs
2023-11-21 10:45:51 +00:00
Dario Nieuwenhuis
221d24f6f8
Parse interrupts on demand for each chip instead of upfront.
2023-11-17 23:42:07 +01:00
Don Reilly
5953194935
cleaning up mess after fixing headers.rs
2023-08-05 22:14:32 -05:00
Dario Nieuwenhuis
f5a068eab6
Split USBRAM from USB, add 32bit USBRAM support, fix some sizes/versions.
2023-04-06 18:26:42 +02:00
Dario Nieuwenhuis
42eec07973
Fix missing USB in a few chips.
2023-04-06 18:26:41 +02:00
Dario Nieuwenhuis
7a95245738
h5: fix usb.
2023-04-05 05:48:41 +02:00
Dario Nieuwenhuis
a2333b8afb
New repo structure: includes stm32-metapac, doesn't commit generated files.
2023-03-20 01:56:23 +01:00
