guangzong/stm32-data
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92 Commits

Author SHA1 Message Date
Dario Nieuwenhuis
60b4b7d155 Add dmamux yamls, use them instead of xml/c parsing. 2021-07-17 07:23:48 +02:00
Bob McWhirter
bbd3378cdc Separate out DMAMUX1 and DMAMUX2 requests. 2021-07-16 15:43:54 -04:00
Bob McWhirter
02dd4e13f2 Parse in the dma HAL headers for the actual request numbers. 
Then apply them to fix up where possible because the XML is crap.
 2021-07-16 13:44:40 -04:00
Dario Nieuwenhuis
134d22af37 Add H7 SMPS 2021-07-16 00:38:49 +02:00
Dario Nieuwenhuis
48b70bdf76 Merge USARTv2 and USARTv3, they're identical. 2021-07-15 00:20:17 +02:00
Dario Nieuwenhuis
6f66c9abdd Correctly map some weird F0 chips that have BDMAv2 2021-07-14 23:47:45 +02:00
Dario Nieuwenhuis
bc9f64650f Parse BDMAv2 req numbers 2021-07-14 23:38:06 +02:00
Bob McWhirter
892c520abd Clean up parse.py. 2021-07-12 15:55:13 -04:00
Bob McWhirter
b187661675 Change DMA-vs-BDMA parsing to ensure we capture everything without trampling. 2021-07-12 15:55:13 -04:00
Bob McWhirter
4823bfee64 Slightly improve DMA parsing wrt H7 weirdness. 2021-07-12 15:55:13 -04:00
Bob McWhirter
7a7b14ed4b Adjust parse to remove L or H from clock name. 2021-07-12 15:55:13 -04:00
Bob McWhirter
db5538e86d Update the RCC scrobbling bits for clock discovery. 2021-07-06 14:20:10 -04:00
Thales Fragoso
e9b6cf4283 Always start DMA channels at zero 2021-07-03 15:24:16 -03:00
Thales Fragoso
12a8134dbb F0: Manually add usart1 clock 2021-07-03 01:38:39 -03:00
Bob McWhirter
cd3ae3473d Another special-casing of RCC for H7 default clocks. 2021-07-01 13:50:55 -04:00
Bob McWhirter
298b89c886 Let's hardcode some H7 default clocks for selectables. 2021-07-01 11:29:27 -04:00
Bob McWhirter
2d17494980 Adjust parse to also label UARTs for v3. 2021-06-30 14:35:52 -04:00
Bob McWhirter
b02a84bf0e Map USARTv3. 2021-06-30 13:34:43 -04:00
Dario Nieuwenhuis
ebd5d47c05 Merge pull request #54 from ctron/feature/fix_i2c_1 
[#52]: Fix missing I2C
 2021-06-29 18:31:33 +02:00
Bob McWhirter
ed248082b8 Cleanup of parse. 2021-06-29 10:52:43 -04:00
Jens Reimann
c4d429e5f7 [#52]: Fix missing I2C 2021-06-28 09:39:25 +02:00
Bob McWhirter
3e1b2d7c8c Adjust parse.py to include datasheet, reference-manual and application-note links. 2021-06-23 11:58:00 -04:00
Dario Nieuwenhuis
3f3a98b3f1 Set block for DMAMUX. 2021-06-23 04:14:38 +02:00
Dario Nieuwenhuis
ac9c476561 Split DMA/BDMA into v1 (no selection) and v2 (has request selection). 2021-06-23 04:02:06 +02:00
Dario Nieuwenhuis
e3c6e44b76 Rename DMAv1 to BDMA, to allow DMA and BDMA to coexist in H7 2021-06-23 02:47:27 +02:00
Dario Nieuwenhuis
29f70ac45f Add DMAMUX 2021-06-23 02:30:55 +02:00
Dario Nieuwenhuis
983fa80ef3 Merge pull request #50 from bobmcwhirter/dma 
DMA
 2021-06-23 00:47:11 +02:00
Thales Fragoso
6656c5c059 Add F0 syscfg 2021-06-22 23:53:50 +02:00
Thales Fragoso
26e4f541ba Add F0 FLASH 2021-06-22 23:53:50 +02:00
Thales Fragoso
ae8455a336 Add F0 RCCs 2021-06-22 23:53:37 +02:00
Bob McWhirter
93900325cb Adjust parse.py to include DMA channel/request per chip and peripheral. 2021-06-22 10:23:57 -04:00
Dominik Boehi
481e607977 Add IPCC peripheral to STM32WB55 2021-06-21 19:13:24 +02:00
Dominik Boehi
454854d527 Add EXTI for STM32WB55 2021-06-21 19:12:00 +02:00
Dario Nieuwenhuis
77d4ae203b Add DBGMCU for all chips 2021-06-21 01:27:36 +02:00
Ulf Lilleengen
3ef6421aa8 Add more peripherals for wl5x 2021-06-16 16:07:00 +02:00
Ulf Lilleengen
d4fad162ac Add support for parsing dual core chips 
This modifies the chip format to include an array of cores, and within
each core the interrupts and peripherals for that core.
 2021-06-16 15:10:02 +02:00
Bob McWhirter
6cdfc6c1e8 Better parsing around ADC_COMMON base addr. 2021-06-14 11:43:48 -04:00
Dario Nieuwenhuis
e478047c78 Merge pull request #45 from embassy-rs/eth-v2 
Eth v2
 2021-06-13 20:54:17 +02:00
Dario Nieuwenhuis
8e71f3da8e Merge pull request #44 from Tiwalun/stm32wb55-support 
Add RCC and SYSCFG for STM32WB55
 2021-06-11 22:46:34 +02:00
Dominik Boehi
6c872019d0 Add RCC and SYSCFG for STM32WB55 2021-06-11 22:36:40 +02:00
Thales Fragoso
e3cc9b041c Add a single yaml for eth_v2 2021-06-11 00:15:56 -03:00
Bob McWhirter
b7c071aa71 Clean up a bit. 2021-06-10 10:38:02 -04:00
Bob McWhirter
fc64e88b92 Extract ADCv3 (arrayification is not possible, slight diffs in field widths) 
Extract ADC_COMMON
Create framework for extra synthetic hand-crafted peripherals.
Add VREFINTCAL reg/block/peripheral for STM32L4+.
 2021-06-10 10:38:02 -04:00
Bob McWhirter
23fed4339b ADC v3 attempt #2. 2021-06-10 10:37:32 -04:00
Dario Nieuwenhuis
4837bee5df Remove reference to nonexistent rcc_h7ab 2021-06-10 03:00:05 +02:00
Bob McWhirter
0619fbc974 Add another regexp for DAC. 2021-06-08 15:04:58 -04:00
Ulf Lilleengen
fe163b5ab1 Add missing SPI6 clock for all H7 family 2021-06-08 16:49:51 +02:00
Ulf Lilleengen
f31ba7bfcb Separate block for H7AB 2021-06-03 15:43:21 +02:00
Ulf Lilleengen
18a99a3a3b Add RCC register for STM32F4 and STM32L4 
Register block based in STM32F427ZI and STM32L4R9.

Use bool for reset registers.

Define clock mapping for RNG peripherals. There are no 1 <-> 1 mapping
of RNG peripheral to clock in the Cubedb sources. The mapping will
pre-select the clock source for RNG for now.
 2021-06-03 11:33:24 +02:00
Bob McWhirter
2ae079edfe Adjust parse.py to emit peri-specific pin information. 2021-06-02 12:09:12 -04:00