eZio Pan
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24b62ea85d
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make address of registers show as hex
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2024-02-25 22:24:22 +01:00 |
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Dario Nieuwenhuis
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87b06bac89
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rcc: separate fields for bus and kernel clock.
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2024-02-16 01:07:41 +01:00 |
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eZio Pan
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5907efbaf2
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update chiptool
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2024-02-15 20:42:08 +01:00 |
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eZio Pan
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8c4122d7c6
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remove clippy warning and error from genrated files.
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2024-02-15 23:39:08 +08:00 |
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eZio Pan
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d20904a208
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refactor with clippy
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2023-12-24 19:07:32 +08:00 |
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xoviat
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69706e61e4
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macros: handle one enum field
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2023-11-06 18:01:39 -06:00 |
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xoviat
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b9efaf36d8
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add stop mode rcc data
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2023-11-05 15:52:50 -06:00 |
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xoviat
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916fa6f760
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use new enum debug macro
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2023-11-05 14:47:25 -06:00 |
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xoviat
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8a09bbb62c
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rcc: more cleanup
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2023-10-13 22:20:18 -05:00 |
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xoviat
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fc4881f7b5
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metapac-gen: sort ir
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2023-10-13 21:52:35 -05:00 |
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xoviat
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ee8e8c82dc
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gen: pretty print ir
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2023-10-08 14:46:58 -05:00 |
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xoviat
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23f9d9b236
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metapac: allow runtime inspection of ir types
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2023-09-29 18:21:03 -05:00 |
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xoviat
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38619f8b99
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metapac: generate ir
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2023-09-26 20:20:28 -05:00 |
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xoviat
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1595920962
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rcc: pipe through sel mux
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2023-09-25 19:26:46 -05:00 |
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Dario Nieuwenhuis
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2dd3ecfc70
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Update chiptool (reg access is now safe, creating regs from raw ptrs is unsafe)
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2023-06-19 02:39:00 +02:00 |
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Rasmus Melchior Jacobsen
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8019b4f48f
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Re-add WRITE_SIZE as it seems to be the same for all regions
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2023-03-25 14:24:21 +01:00 |
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Rasmus Melchior Jacobsen
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aa9cda492d
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Remove custom otp memory kind
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2023-03-25 12:44:41 +01:00 |
|
Rasmus Melchior Jacobsen
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ba962b3ca1
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Support multiple flash regions, including OTP
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2023-03-25 05:46:16 +01:00 |
|
JackN
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8e0515dc04
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Fix clippy lints
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2023-03-23 08:51:03 -04:00 |
|
JackN
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6ed3e9d688
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Device::nvic_priority_bits as an `Option<u8>
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2023-03-22 17:26:38 -04:00 |
|
JackN
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9c8ef4b931
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Add NVIC_PRIO_BITS to data and metapac
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2023-03-22 14:18:37 -04:00 |
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Dario Nieuwenhuis
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a2333b8afb
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New repo structure: includes stm32-metapac, doesn't commit generated files.
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2023-03-20 01:56:23 +01:00 |
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