Dario Nieuwenhuis
c6b8d61400
Merge pull request #391 from msrd0/syscfg-ur17-tcm-axi
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Add TCM_AXI_SHARED_CFG to SYSCFG_UR17 for STM32H7
2024-02-12 18:52:11 +00:00
Dominic
39dcea050b
Add TCM_AXI_SHARED_CFG to SYSCFG_UR18 for STM32H7
2024-02-12 18:13:40 +01:00
Dario Nieuwenhuis
8ae5bb5fe6
rcc: more accurate f3 versions.
2024-02-12 02:03:25 +01:00
Dario Nieuwenhuis
5bf4bec597
rcc: more generous fallback stripping all peripheral numbers.
2024-02-10 02:48:24 +01:00
Dario Nieuwenhuis
0c921dde2e
Refactor RCC code to find more muxes.
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Fixes #383
2024-02-10 02:40:36 +01:00
Dario Nieuwenhuis
028efe4e6e
Merge pull request #364 from eZioPan/timer_v2
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timer v2
2024-02-09 22:42:17 +00:00
Dario Nieuwenhuis
36a3262735
Merge pull request #390 from caleb-garrett/hash
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Add HASH v4
2024-02-08 20:08:11 +00:00
Caleb Garrett
3fdcc771f3
Added hash v4.
2024-02-08 14:39:43 -05:00
Dario Nieuwenhuis
d7c933984f
Merge pull request #382 from lucasgranberg/main
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add comp_v3 and apply to stm32wle
2024-02-07 18:24:39 +00:00
Dario Nieuwenhuis
19c010e2e1
Merge pull request #389 from msrd0/syscfg_ur18
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Add SYSCFG_UR18 register
2024-02-07 18:24:02 +00:00
Dario Nieuwenhuis
90698114d6
Merge pull request #387 from msrd0/octospi1en
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Add OCTOSPI1 register bits
2024-02-07 18:23:45 +00:00
Dario Nieuwenhuis
b23e88a617
Merge pull request #388 from msrd0/octospi2
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Fix register address for OCTOSPI2 peripheral
2024-02-07 18:23:12 +00:00
Dominic
ae595edcf2
Add SYSCFG_UR18 register
2024-02-07 17:01:41 +01:00
Dominic
334a42bce7
Fix register address for OCTOSPI2 peripheral
2024-02-07 16:58:16 +01:00
Dominic
01ef0b5999
Add OCTOSPI1 register bits
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Those were previously only called QUADSPI, which is needed on some
chips like the STM32H745, but those bits are used as OCTOSPI1 bits
on other chips like the STM32H723.
2024-02-07 16:44:29 +01:00
Dario Nieuwenhuis
b07168e665
Merge pull request #381 from shufps/main
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adds adc support for L0
2024-02-07 13:47:49 +00:00
Lucas Granberg
90b8b692b7
add comp v3 to STM32WL (non E)
2024-02-07 15:37:57 +02:00
Lucas Granberg
8c8af96abd
add comp_v3 and apply to stm32wl
2024-02-07 14:55:12 +02:00
shufps
2f59dea33f
cargo fmt
2024-02-07 09:02:18 +01:00
shufps
7c7194d546
adds adc support for L0
2024-02-07 08:57:52 +01:00
Dario Nieuwenhuis
f0101a2249
Merge pull request #377 from AdinAck/main
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[READY NOW!] Initial Comparator Support
2024-02-06 16:59:03 +00:00
Dario Nieuwenhuis
5674011dd7
Merge pull request #379 from caleb-garrett/hash
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Corrected hash v3 register arrays
2024-02-06 00:04:14 +00:00
Caleb Garrett
44c579f350
Corrected hash v3 array lengths.
2024-02-05 18:35:15 -05:00
eZio Pan
e857389850
Add OR register.
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OR1 is the same as OR. The content is different across chip serials. Leave entire register to HAL to parse.
OR2 and OR3 are just AF1 and AF2.
2024-02-05 16:27:10 +08:00
eZio Pan
b3871b47d8
mapping bug fix
2024-02-05 16:27:10 +08:00
eZio Pan
eb88e4bfb6
tailoring from timer_v1 to timer_l0
2024-02-05 16:27:10 +08:00
eZio Pan
281787fbb1
branch timer_l0 from timer_v1
2024-02-05 16:27:10 +08:00
eZio Pan
9fa345af29
add TIM_BASIC_NO_CR2, common part of TIM_BASIC and TIM_1CH_CMP
2024-02-05 16:27:10 +08:00
eZio Pan
10a1a61bae
let TIM_ADV based on TIM_2CH_CMP
2024-02-05 16:27:10 +08:00
eZio Pan
cd490fd7f3
let TIM_GP16 based on TIM_2CH
2024-02-05 16:27:10 +08:00
eZio Pan
6b5e0c6b4e
add TIM_CORE, common part of TIM_BASIC and TIM_1CH
2024-02-05 16:27:10 +08:00
eZio Pan
db6e501fd3
make 2CH_CMP based on 1CH_CMP
2024-02-05 16:27:10 +08:00
eZio Pan
771c51b438
bug fix
2024-02-05 16:27:10 +08:00
eZio Pan
982b30aa6a
update timer mapping
2024-02-05 16:27:10 +08:00
eZio Pan
abb0f63c4a
tailoring timer_v1 from timer_v2
2024-02-05 16:27:10 +08:00
eZio Pan
81d09e5782
branch timer_v1 from timer_v2
2024-02-05 16:27:10 +08:00
eZio Pan
ab11ed85fb
remove redundant CCR fieldset, and bug fix
2024-02-05 16:27:10 +08:00
eZio Pan
7518e37532
merge all TIMs into timer_v2
2024-02-05 16:27:10 +08:00
eZio Pan
1b83acf50b
ch2_cmp, ch2, ch1_cmp, ch1 merged
2024-02-05 16:27:10 +08:00
eZio Pan
0ed4c863d2
1ch_cmp, 1ch merged
2024-02-05 16:27:10 +08:00
eZio Pan
d2ec8c049c
2ch_cmp, 2ch, 1ch merged
2024-02-05 16:27:10 +08:00
eZio Pan
864e7a7078
2ch_cmp, 2ch merged
2024-02-05 16:27:10 +08:00
eZio Pan
65a7e873c6
adv, gp16, gp32, basic merged
2024-02-05 16:27:10 +08:00
eZio Pan
a3e7e74535
adv, gp16, gp32 merged
2024-02-05 16:27:10 +08:00
eZio Pan
6eba236ede
adv, gp16 merged
2024-02-05 16:27:10 +08:00
eZio Pan
9ede4ad2c0
merging adv, gp16
2024-02-05 16:27:10 +08:00
eZio Pan
cb85778273
naming block, as start point of merging
2024-02-05 16:27:10 +08:00
eZio Pan
6356128ba2
tailoring from tim2chcmp to timbasic
2024-02-05 16:27:10 +08:00
eZio Pan
0096f150c0
branch from tim2chcmp to timbasic
2024-02-05 16:27:10 +08:00
eZio Pan
8c321f182c
tailoring from tim2chcmp to tim1chcmp
2024-02-05 16:27:10 +08:00
