Dario Nieuwenhuis
|
893d7ff36b
|
Add per-package pinouts.
|
2024-05-09 23:30:01 +02:00 |
|
Dario Nieuwenhuis
|
87b06bac89
|
rcc: separate fields for bus and kernel clock.
|
2024-02-16 01:07:41 +01:00 |
|
xoviat
|
54fedeeefa
|
don't serialize default stop mode
|
2023-11-05 16:11:58 -06:00 |
|
xoviat
|
b9efaf36d8
|
add stop mode rcc data
|
2023-11-05 15:52:50 -06:00 |
|
Dario Nieuwenhuis
|
4baa9a0079
|
Merge pull request #265 from xoviat/sel
rcc: pipe through sel mux and generate ir
|
2023-10-02 20:40:01 +00:00 |
|
xoviat
|
4a893c37da
|
add man impl. pin signals
|
2023-10-01 13:28:31 -05:00 |
|
xoviat
|
1595920962
|
rcc: pipe through sel mux
|
2023-09-25 19:26:46 -05:00 |
|
JuliDi
|
cf933a89de
|
add proper sorting
|
2023-09-14 16:26:54 +02:00 |
|
JuliDi
|
4484603dbd
|
first working state with bad sorting
|
2023-09-14 16:26:53 +02:00 |
|
JackN
|
6ed3e9d688
|
Device::nvic_priority_bits as an `Option<u8>
|
2023-03-22 17:26:38 -04:00 |
|
JackN
|
9c8ef4b931
|
Add NVIC_PRIO_BITS to data and metapac
|
2023-03-22 14:18:37 -04:00 |
|
Dario Nieuwenhuis
|
a2333b8afb
|
New repo structure: includes stm32-metapac, doesn't commit generated files.
|
2023-03-20 01:56:23 +01:00 |
|
Grant Miller
|
6b3a7bc0c2
|
Rewrite python script in rust
|
2022-11-12 17:12:51 -06:00 |
|