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165 Commits

Author SHA1 Message Date
Tyler Gilbert
b133fdbc97 Add support for ADF_v1 available on STM32U5 2024-01-03 16:28:25 -06:00
Dario Nieuwenhuis
a535002553
Merge pull request #325 from chrenderle/main 
Add rtc registers for stm32l5
 2024-01-01 21:11:26 +00:00
Christian Enderle
0ddf28abe3 dbgmcu: add support for stm32l5 2023-12-28 11:11:40 +01:00
Christian Enderle
28306c1d75 Added rtc registers for stm32l5 2023-12-26 11:32:15 +01:00
eZio Pan
d20904a208 refactor with clippy 2023-12-24 19:07:32 +08:00
Dario Nieuwenhuis
3634020845 Fix qspi for all chips. 
Co-Authored-By: Tupelov <64274155+Tupelov@users.noreply.github.com>
 2023-12-08 21:54:03 +01:00
Sam
830341361e STM32L1 to use ADC1 address instead of incorrect ADC address 2023-12-08 18:55:54 +01:00
Sam
08c1f451b6 ADC stm32l151c8 specifics 2023-12-08 18:55:53 +01:00
Sam
b53fd35116 ADC afit_v1_1 implementation 2023-12-08 18:55:38 +01:00
Dario Nieuwenhuis
b6181ce3f3
Merge pull request #308 from tcbennun/fdcan-fix 
fdcan: add H7 support; fix regs for others; add message RAM blocks
 2023-12-08 17:21:24 +00:00
Torin Cooper-Bennun
27c71ac451 fdcan: generate register blocks for message RAM 
this is a special case, as most data sources don't mention this as a
separate peripheral at all, and those that do don't handle the offsets
in the case of multiple FDCANS

H7 chips have a single 10KB block shared between all FDCANs
 2023-11-21 10:45:51 +00:00
Torin Cooper-Bennun
f65fd694e1 fdcan: fix register block definitions; separate version for H7 
the Cube XMLs refer to "fdcan_v1_0" and "fdcan_v1_1" but these seem to
have no bearing on the actual registers used. Thus chips.rs should make
no distinction between v1_0 and v1_1.

the previous YAML seems to have been generated from a G4 SVD, but this
series' SVDs consistently have several errata.

I have therefore replaced can_fdcan.yaml with can_fdcan_v1.yaml, built
from an H5 SVD which appears to match the RMs of G0, G4, H5 and L5
chips.

the H7 series has a totally different FDCAN, so I've added a separate
YAML for it.
 2023-11-21 10:45:51 +00:00
Adam Greig
78232c013e
Rework DACs for all STM32 2023-11-19 04:51:20 +00:00
Adam Greig
7ce7dc901f
Add DACv4 support for STM32G4 2023-11-19 04:51:19 +00:00
Dario Nieuwenhuis
221d24f6f8 Parse interrupts on demand for each chip instead of upfront. 2023-11-17 23:42:07 +01:00
Dario Nieuwenhuis
8381654ade crs: add for l5. 2023-11-05 23:37:05 +01:00
Dario Nieuwenhuis
e78c8c9d94 crs: add for all chips. 2023-11-05 23:12:27 +01:00
Dario Nieuwenhuis
cf3f969fe8 Add stm32wba spi. 2023-10-22 22:31:20 +02:00
Olle Sandberg
9f019bd9ba wwdg: register definitions for window watchdog v2 2023-10-19 14:49:41 +02:00
JackN
47a5753bef TSC: Add new TSCperipheral to perimap 2023-10-16 10:25:09 -04:00
Dario Nieuwenhuis
9330e31117 rng: add wb support. 2023-10-16 04:58:26 +02:00
Dario Nieuwenhuis
73e3f8a965 rcc: separate L4 and L4+ 2023-10-16 03:11:00 +02:00
JackN
0f0517404e GFXMMU: Add new peripherals to perimap 2023-10-13 17:12:57 -04:00
JackN
af1a5f5877 OCTOSPI: Merge peri yamls 2023-10-12 17:44:41 -04:00
JackN
e99c97f0f6 OCTOSPI: Merge peripheral yamls and consolidate enums 2023-10-12 15:43:04 -04:00
JackN
2ab8cf7d44 Remove blanket matches from perimap 2023-10-12 10:45:54 -04:00
JackN
dc7bc1272a Add OCTOSPIM and OCTOSPI to perimap 2023-10-12 10:24:00 -04:00
Dario Nieuwenhuis
6bfa5a0dce rtc/bd fixes. 2023-10-11 03:41:10 +02:00
Dario Nieuwenhuis
f40f5a40c1 Not all L0s have HSI48/CRS. 2023-10-11 01:21:26 +02:00
Dario Nieuwenhuis
a7bf7f02d1 Fix MCO/MCO1 inconsistency in G0, C0. 2023-10-07 01:13:03 +02:00
xoviat
e7a291e659 sort pins by key 2023-10-05 20:04:58 -05:00
xoviat
2271da1671 Merge branch 'main' of https://github.com/embassy-rs/stm32-data into h7-lsedrv-errata 2023-10-05 19:30:38 -05:00
xoviat
ab12bb45b1 sort pins to avoid diff 2023-10-05 19:08:51 -05:00
Matt Ickstadt
568a7058a1 Create rcc_h7rm04ee.yaml as a copy of rcc_h7.yaml 2023-10-05 10:35:43 -05:00
xoviat
06d13dfd24
Merge pull request #267 from oll3/tamp_block 
add TAMP register block for g0, g4, l5, u5 and wl
 2023-10-02 21:00:10 +00:00
xoviat
92ae3d5870 optimize hashset gen. 2023-10-01 13:44:30 -05:00
xoviat
4a893c37da add man impl. pin signals 2023-10-01 13:28:31 -05:00
xoviat
8ee2862086
Merge pull request #254 from JuliDi/dont-remove-analogswitch-pins 
Handle "_C" pins
 2023-09-30 15:28:30 +00:00
xoviat
e36d73af66 Merge branch 'main' of https://github.com/embassy-rs/stm32-data into sbs 2023-09-28 18:52:19 -05:00
xoviat
97a4fb22b2 rename sbs to syscfg 2023-09-28 18:50:30 -05:00
xoviat
0041cf976c opamp: add f3 and g4 2023-09-28 18:32:30 -05:00
xoviat
1b39301d8c Merge branch 'master' into lptim-basic 2023-09-27 21:09:34 -05:00
Olle Sandberg
e7de675353 add TAMP register block for g0, g4, l5, u5 and wl 2023-09-27 07:35:27 +02:00
Dario Nieuwenhuis
bdbf126746 flash: set for all l0 chips. 2023-09-26 05:06:10 +02:00
Dario Nieuwenhuis
4f83d5d9cf pwr: add f0, f1. 2023-09-25 00:27:32 +02:00
Dario Nieuwenhuis
2f97514774 pwr: add all VOS enums. 2023-09-18 02:57:23 +02:00
Dario Nieuwenhuis
43c1e7b3be Add STM32WBA support. 2023-09-16 02:34:03 +02:00
xoviat
c3548f2b7a add pwr l0 2023-09-14 17:10:04 -05:00
JuliDi
4484603dbd
first working state with bad sorting 2023-09-14 16:26:53 +02:00
xoviat
b37cec1e73
Merge pull request #251 from xoviat/sdmmc 
u5: add sdmmc
 2023-09-10 19:08:48 +00:00