guangzong/stm32-data
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309 Commits

Author SHA1 Message Date
eZio Pan
d20904a208 refactor with clippy 2023-12-24 19:07:32 +08:00
Dario Nieuwenhuis
3634020845 Fix qspi for all chips. 
Co-Authored-By: Tupelov <64274155+Tupelov@users.noreply.github.com>
 2023-12-08 21:54:03 +01:00
Sam
830341361e STM32L1 to use ADC1 address instead of incorrect ADC address 2023-12-08 18:55:54 +01:00
Sam
1cc9a2fcca limit ADC1 clocks fallback for stm32l series 2023-12-08 18:55:54 +01:00
Sam
08c1f451b6 ADC stm32l151c8 specifics 2023-12-08 18:55:53 +01:00
Sam
b53fd35116 ADC afit_v1_1 implementation 2023-12-08 18:55:38 +01:00
Dario Nieuwenhuis
b6181ce3f3
Merge pull request #308 from tcbennun/fdcan-fix 
fdcan: add H7 support; fix regs for others; add message RAM blocks
 2023-12-08 17:21:24 +00:00
Torin Cooper-Bennun
27c71ac451 fdcan: generate register blocks for message RAM 
this is a special case, as most data sources don't mention this as a
separate peripheral at all, and those that do don't handle the offsets
in the case of multiple FDCANS

H7 chips have a single 10KB block shared between all FDCANs
 2023-11-21 10:45:51 +00:00
Torin Cooper-Bennun
90ff5316eb rcc: fix FDCAN: multiple FDCANs share the same RCC fields 
the RCC fields are named either FDCAN or FDCAN12
 2023-11-21 10:45:51 +00:00
Torin Cooper-Bennun
f65fd694e1 fdcan: fix register block definitions; separate version for H7 
the Cube XMLs refer to "fdcan_v1_0" and "fdcan_v1_1" but these seem to
have no bearing on the actual registers used. Thus chips.rs should make
no distinction between v1_0 and v1_1.

the previous YAML seems to have been generated from a G4 SVD, but this
series' SVDs consistently have several errata.

I have therefore replaced can_fdcan.yaml with can_fdcan_v1.yaml, built
from an H5 SVD which appears to match the RMs of G0, G4, H5 and L5
chips.

the H7 series has a totally different FDCAN, so I've added a separate
YAML for it.
 2023-11-21 10:45:51 +00:00
Adam Greig
78232c013e
Rework DACs for all STM32 2023-11-19 04:51:20 +00:00
Adam Greig
7ce7dc901f
Add DACv4 support for STM32G4 2023-11-19 04:51:19 +00:00
Dario Nieuwenhuis
f6d1ffc1a2 Fix G0 USB interrupts. 2023-11-18 01:39:07 +01:00
Dario Nieuwenhuis
4852f5040a Ensure no duplicate irqs with the same signal. 2023-11-18 00:39:24 +01:00
Dario Nieuwenhuis
f5a4c58efa Remove USB_DRD_FS rename hack. 2023-11-18 00:00:14 +01:00
Dario Nieuwenhuis
f0866ffbc4 Check for non-existing interrupts earlier. 2023-11-17 23:55:55 +01:00
Dario Nieuwenhuis
221d24f6f8 Parse interrupts on demand for each chip instead of upfront. 2023-11-17 23:42:07 +01:00
Dario Nieuwenhuis
c551c07bf1 rcc: consistency fixes. 2023-11-13 01:00:53 +01:00
Dario Nieuwenhuis
8381654ade crs: add for l5. 2023-11-05 23:37:05 +01:00
xoviat
04d773b7b3
Merge pull request #303 from xoviat/low-power 
add stop mode rcc data
 2023-11-05 22:29:38 +00:00
Dario Nieuwenhuis
e78c8c9d94 crs: add for all chips. 2023-11-05 23:12:27 +01:00
xoviat
b9efaf36d8 add stop mode rcc data 2023-11-05 15:52:50 -06:00
Dario Nieuwenhuis
b59a5c1812 rcc: add missing enums to wb, wl. 2023-10-23 00:30:16 +02:00
Dario Nieuwenhuis
cf3f969fe8 Add stm32wba spi. 2023-10-22 22:31:20 +02:00
xoviat
8fecdeff9c rcc: solve hashmap determinism for good 2023-10-20 18:43:46 -05:00
xoviat
39e82b76a4 rcc: solve data mutability 2023-10-19 21:01:17 -05:00
Olle Sandberg
9f019bd9ba wwdg: register definitions for window watchdog v2 2023-10-19 14:49:41 +02:00
xoviat
8bd7ff51b0 rcc: expand checker to all chips 2023-10-18 21:01:57 -05:00
xoviat
3d9c8b70e3 rcc: check l4plus and l5 2023-10-17 17:21:06 -05:00
xoviat
c61495fd4e rcc: more cleanup 2023-10-17 16:57:33 -05:00
xoviat
fb84c0ac55 rcc: fixup clock names and expand checking 2023-10-16 17:53:26 -05:00
JackN
47a5753bef TSC: Add new TSCperipheral to perimap 2023-10-16 10:25:09 -04:00
Dario Nieuwenhuis
9330e31117 rng: add wb support. 2023-10-16 04:58:26 +02:00
Dario Nieuwenhuis
73e3f8a965 rcc: separate L4 and L4+ 2023-10-16 03:11:00 +02:00
xoviat
b9a89a1851 rcc: cleanup variants and rename ahb -> clk 2023-10-15 18:01:50 -05:00
xoviat
8b8686a852 rcc: more mux and enum cleanup 2023-10-15 10:37:36 -05:00
xoviat
5d51e3b706 rcc: add more mux data 2023-10-14 17:20:25 -05:00
xoviat
68d77f487b rcc: add more mux data 2023-10-14 11:41:21 -05:00
xoviat
b14427f2d1 Merge branch 'main' of https://github.com/embassy-rs/stm32-data into rcc 2023-10-13 22:22:05 -05:00
xoviat
8a09bbb62c rcc: more cleanup 2023-10-13 22:20:18 -05:00
xoviat
e90a83a4f0
Merge pull request #281 from noppej/gfxmmu 
Add GFXMMU peripheral
 2023-10-14 02:26:15 +00:00
xoviat
aa5e909e11 rcc: more enum cleanup 2023-10-13 20:54:24 -05:00
JackN
0f0517404e GFXMMU: Add new peripherals to perimap 2023-10-13 17:12:57 -04:00
xoviat
c4cd46927d rcc: rename h5 clock enum variants and add check 2023-10-12 20:48:35 -05:00
JackN
af1a5f5877 OCTOSPI: Merge peri yamls 2023-10-12 17:44:41 -04:00
JackN
e99c97f0f6 OCTOSPI: Merge peripheral yamls and consolidate enums 2023-10-12 15:43:04 -04:00
JackN
2ab8cf7d44 Remove blanket matches from perimap 2023-10-12 10:45:54 -04:00
JackN
dc7bc1272a Add OCTOSPIM and OCTOSPI to perimap 2023-10-12 10:24:00 -04:00
Dario Nieuwenhuis
6bfa5a0dce rtc/bd fixes. 2023-10-11 03:41:10 +02:00
Dario Nieuwenhuis
f40f5a40c1 Not all L0s have HSI48/CRS. 2023-10-11 01:21:26 +02:00