1545 Commits

Author SHA1 Message Date
eZio Pan
6b5e0c6b4e add TIM_CORE, common part of TIM_BASIC and TIM_1CH 2024-02-05 16:27:10 +08:00
eZio Pan
db6e501fd3 make 2CH_CMP based on 1CH_CMP 2024-02-05 16:27:10 +08:00
eZio Pan
771c51b438 bug fix 2024-02-05 16:27:10 +08:00
eZio Pan
982b30aa6a update timer mapping 2024-02-05 16:27:10 +08:00
eZio Pan
abb0f63c4a tailoring timer_v1 from timer_v2 2024-02-05 16:27:10 +08:00
eZio Pan
81d09e5782 branch timer_v1 from timer_v2 2024-02-05 16:27:10 +08:00
eZio Pan
ab11ed85fb remove redundant CCR fieldset, and bug fix 2024-02-05 16:27:10 +08:00
eZio Pan
7518e37532 merge all TIMs into timer_v2 2024-02-05 16:27:10 +08:00
eZio Pan
1b83acf50b ch2_cmp, ch2, ch1_cmp, ch1 merged 2024-02-05 16:27:10 +08:00
eZio Pan
0ed4c863d2 1ch_cmp, 1ch merged 2024-02-05 16:27:10 +08:00
eZio Pan
d2ec8c049c 2ch_cmp, 2ch, 1ch merged 2024-02-05 16:27:10 +08:00
eZio Pan
864e7a7078 2ch_cmp, 2ch merged 2024-02-05 16:27:10 +08:00
eZio Pan
65a7e873c6 adv, gp16, gp32, basic merged 2024-02-05 16:27:10 +08:00
eZio Pan
a3e7e74535 adv, gp16, gp32 merged 2024-02-05 16:27:10 +08:00
eZio Pan
6eba236ede adv, gp16 merged 2024-02-05 16:27:10 +08:00
eZio Pan
9ede4ad2c0 merging adv, gp16 2024-02-05 16:27:10 +08:00
eZio Pan
cb85778273 naming block, as start point of merging 2024-02-05 16:27:10 +08:00
eZio Pan
6356128ba2 tailoring from tim2chcmp to timbasic 2024-02-05 16:27:10 +08:00
eZio Pan
0096f150c0 branch from tim2chcmp to timbasic 2024-02-05 16:27:10 +08:00
eZio Pan
8c321f182c tailoring from tim2chcmp to tim1chcmp 2024-02-05 16:27:10 +08:00
eZio Pan
b4d5936b9b branch from tim2chcmp to tim1chcmp 2024-02-05 16:27:10 +08:00
eZio Pan
8361dffb8d bug fix 2024-02-05 16:27:10 +08:00
eZio Pan
75011dc243 tailoring from tim2ch to tim1ch 2024-02-05 16:27:10 +08:00
eZio Pan
1e35b09edf tailoring from tim2chcmp to tim2ch 2024-02-05 16:27:10 +08:00
eZio Pan
dd1d4c772b branch from tim2chcmp to tim2ch 2024-02-05 16:27:10 +08:00
eZio Pan
8c0ab318ca tailoring form timadv to tim2chcmp 2024-02-05 16:27:10 +08:00
eZio Pan
4bdc25368f branch from timadv to tim2chcmp 2024-02-05 16:27:10 +08:00
eZio Pan
0bb68b7dcb bug fix 2024-02-05 16:27:10 +08:00
eZio Pan
6e36b80628 tailoring from gp16 to gp32 2024-02-05 16:27:10 +08:00
eZio Pan
864508ced7 branching gp32 from gp16 2024-02-05 16:27:10 +08:00
eZio Pan
ffd1d9a48f redesign access at dither mode 2024-02-05 16:27:10 +08:00
eZio Pan
ee78a5d925 tailoring from adv to gp16 2024-02-05 16:27:10 +08:00
eZio Pan
033aaaecb3 branch gp16 from adv 2024-02-05 16:27:10 +08:00
eZio Pan
70282b4d94 timadv, enum level 2024-02-05 16:27:10 +08:00
eZio Pan
1cd8d830f3 timadv, fieldset level 2024-02-05 16:27:10 +08:00
eZio Pan
396ccfda7d timadv, block level 2024-02-05 16:27:10 +08:00
Dario Nieuwenhuis
d04eaeb0d5 Rename ICSEL -> I2CSEL 2024-02-05 00:42:54 +01:00
Dario Nieuwenhuis
aa5dbf859f
Merge pull request #378 from caleb-garrett/hash
Corrected hash STR register to RW
2024-02-04 21:56:48 +00:00
Caleb Garrett
3dd8acfcc6 Undo YAML autoformat. 2024-02-04 16:52:13 -05:00
Dario Nieuwenhuis
e702b4d564 fix pwr for wb35xx 2024-02-04 22:40:36 +01:00
Caleb Garrett
eb0cad0476 Corrected hash STR register to RW. 2024-02-04 09:20:02 -05:00
Dario Nieuwenhuis
3e3b53df78 h5: more mux fix. 2024-02-02 23:20:36 +01:00
Dario Nieuwenhuis
79e839f9b5 h5: fix some bad rcc muxes. 2024-02-02 22:44:37 +01:00
Dario Nieuwenhuis
dffe8dacce Add clock mux for F4 and F7. 2024-02-02 02:15:32 +01:00
Dario Nieuwenhuis
768b3e8e31 Fix missing AF numbers in H7 _C pins. 2024-02-01 23:46:31 +01:00
Dario Nieuwenhuis
fcdcb0471b Fix missing DAC RCC on H7. 2024-02-01 23:40:12 +01:00
Dario Nieuwenhuis
c6ad5e265a cleanup rcc bit matching. 2024-02-01 23:36:45 +01:00
Dario Nieuwenhuis
9e844dc5ac prevent "fatal: gc is already running" errors 2024-02-01 18:27:05 +01:00
Dario Nieuwenhuis
0cb3a4fcae always use non-_C GPIOs for digital signals on H7. 2024-02-01 01:35:33 +01:00
Adin Ackerman
ee4b4abcc4 update g0 regex for single character 2024-01-30 18:32:48 -08:00