eZio Pan
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6b5e0c6b4e
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add TIM_CORE, common part of TIM_BASIC and TIM_1CH
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2024-02-05 16:27:10 +08:00 |
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eZio Pan
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db6e501fd3
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make 2CH_CMP based on 1CH_CMP
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2024-02-05 16:27:10 +08:00 |
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eZio Pan
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771c51b438
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bug fix
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2024-02-05 16:27:10 +08:00 |
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eZio Pan
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982b30aa6a
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update timer mapping
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2024-02-05 16:27:10 +08:00 |
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eZio Pan
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abb0f63c4a
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tailoring timer_v1 from timer_v2
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2024-02-05 16:27:10 +08:00 |
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eZio Pan
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81d09e5782
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branch timer_v1 from timer_v2
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2024-02-05 16:27:10 +08:00 |
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eZio Pan
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ab11ed85fb
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remove redundant CCR fieldset, and bug fix
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2024-02-05 16:27:10 +08:00 |
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eZio Pan
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7518e37532
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merge all TIMs into timer_v2
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2024-02-05 16:27:10 +08:00 |
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eZio Pan
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1b83acf50b
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ch2_cmp, ch2, ch1_cmp, ch1 merged
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2024-02-05 16:27:10 +08:00 |
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eZio Pan
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0ed4c863d2
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1ch_cmp, 1ch merged
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2024-02-05 16:27:10 +08:00 |
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eZio Pan
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d2ec8c049c
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2ch_cmp, 2ch, 1ch merged
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2024-02-05 16:27:10 +08:00 |
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eZio Pan
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864e7a7078
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2ch_cmp, 2ch merged
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2024-02-05 16:27:10 +08:00 |
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eZio Pan
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65a7e873c6
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adv, gp16, gp32, basic merged
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2024-02-05 16:27:10 +08:00 |
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eZio Pan
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a3e7e74535
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adv, gp16, gp32 merged
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2024-02-05 16:27:10 +08:00 |
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eZio Pan
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6eba236ede
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adv, gp16 merged
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2024-02-05 16:27:10 +08:00 |
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eZio Pan
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9ede4ad2c0
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merging adv, gp16
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2024-02-05 16:27:10 +08:00 |
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eZio Pan
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cb85778273
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naming block, as start point of merging
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2024-02-05 16:27:10 +08:00 |
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eZio Pan
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6356128ba2
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tailoring from tim2chcmp to timbasic
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2024-02-05 16:27:10 +08:00 |
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eZio Pan
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0096f150c0
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branch from tim2chcmp to timbasic
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2024-02-05 16:27:10 +08:00 |
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eZio Pan
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8c321f182c
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tailoring from tim2chcmp to tim1chcmp
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2024-02-05 16:27:10 +08:00 |
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eZio Pan
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b4d5936b9b
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branch from tim2chcmp to tim1chcmp
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2024-02-05 16:27:10 +08:00 |
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eZio Pan
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8361dffb8d
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bug fix
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2024-02-05 16:27:10 +08:00 |
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eZio Pan
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75011dc243
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tailoring from tim2ch to tim1ch
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2024-02-05 16:27:10 +08:00 |
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eZio Pan
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1e35b09edf
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tailoring from tim2chcmp to tim2ch
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2024-02-05 16:27:10 +08:00 |
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eZio Pan
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dd1d4c772b
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branch from tim2chcmp to tim2ch
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2024-02-05 16:27:10 +08:00 |
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eZio Pan
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8c0ab318ca
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tailoring form timadv to tim2chcmp
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2024-02-05 16:27:10 +08:00 |
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eZio Pan
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4bdc25368f
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branch from timadv to tim2chcmp
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2024-02-05 16:27:10 +08:00 |
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eZio Pan
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0bb68b7dcb
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bug fix
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2024-02-05 16:27:10 +08:00 |
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eZio Pan
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6e36b80628
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tailoring from gp16 to gp32
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2024-02-05 16:27:10 +08:00 |
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eZio Pan
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864508ced7
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branching gp32 from gp16
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2024-02-05 16:27:10 +08:00 |
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eZio Pan
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ffd1d9a48f
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redesign access at dither mode
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2024-02-05 16:27:10 +08:00 |
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eZio Pan
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ee78a5d925
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tailoring from adv to gp16
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2024-02-05 16:27:10 +08:00 |
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eZio Pan
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033aaaecb3
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branch gp16 from adv
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2024-02-05 16:27:10 +08:00 |
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eZio Pan
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70282b4d94
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timadv, enum level
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2024-02-05 16:27:10 +08:00 |
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eZio Pan
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1cd8d830f3
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timadv, fieldset level
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2024-02-05 16:27:10 +08:00 |
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eZio Pan
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396ccfda7d
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timadv, block level
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2024-02-05 16:27:10 +08:00 |
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Dario Nieuwenhuis
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d04eaeb0d5
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Rename ICSEL -> I2CSEL
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2024-02-05 00:42:54 +01:00 |
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Dario Nieuwenhuis
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aa5dbf859f
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Merge pull request #378 from caleb-garrett/hash
Corrected hash STR register to RW
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2024-02-04 21:56:48 +00:00 |
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Caleb Garrett
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3dd8acfcc6
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Undo YAML autoformat.
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2024-02-04 16:52:13 -05:00 |
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Dario Nieuwenhuis
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e702b4d564
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fix pwr for wb35xx
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2024-02-04 22:40:36 +01:00 |
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Caleb Garrett
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eb0cad0476
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Corrected hash STR register to RW.
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2024-02-04 09:20:02 -05:00 |
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Dario Nieuwenhuis
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3e3b53df78
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h5: more mux fix.
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2024-02-02 23:20:36 +01:00 |
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Dario Nieuwenhuis
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79e839f9b5
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h5: fix some bad rcc muxes.
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2024-02-02 22:44:37 +01:00 |
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Dario Nieuwenhuis
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dffe8dacce
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Add clock mux for F4 and F7.
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2024-02-02 02:15:32 +01:00 |
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Dario Nieuwenhuis
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768b3e8e31
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Fix missing AF numbers in H7 _C pins.
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2024-02-01 23:46:31 +01:00 |
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Dario Nieuwenhuis
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fcdcb0471b
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Fix missing DAC RCC on H7.
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2024-02-01 23:40:12 +01:00 |
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Dario Nieuwenhuis
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c6ad5e265a
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cleanup rcc bit matching.
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2024-02-01 23:36:45 +01:00 |
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Dario Nieuwenhuis
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9e844dc5ac
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prevent "fatal: gc is already running" errors
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2024-02-01 18:27:05 +01:00 |
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Dario Nieuwenhuis
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0cb3a4fcae
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always use non-_C GPIOs for digital signals on H7.
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2024-02-01 01:35:33 +01:00 |
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Adin Ackerman
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ee4b4abcc4
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update g0 regex for single character
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2024-01-30 18:32:48 -08:00 |
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