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Merge pull request #455 from dlaw/main

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Add 8 and 16 bit wide SPI data registers
This commit is contained in:
Dario Nieuwenhuis 2024-04-05 18:12:54 +00:00 committed by GitHub
commit fff3cddff0
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GPG Key ID: B5690EEEBB952194
6 changed files with 75 additions and 66 deletions
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2
data/registers/crc_v2.yaml
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@ -1,7 +1,7 @@
block/CRC:
description: Cyclic Redundancy Check calculation unit
items:
- name: DR
- name: DR32
description: Data register
byte_offset: 0
- name: DR16

2
data/registers/crc_v3.yaml
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@ -1,7 +1,7 @@
block/CRC:
description: Cyclic Redundancy Check calculation unit
items:
- name: DR
- name: DR32
description: Data register
byte_offset: 0
- name: DR16

17
data/registers/spi_v2.yaml
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@ -13,10 +13,14 @@ block/SPI:
description: status register
byte_offset: 8
fieldset: SR
- name: DR
description: data register
- name: DR16
description: data register - half-word sized
byte_offset: 12
fieldset: DR
bit_size: 16
- name: DR8
description: data register - byte sized
byte_offset: 12
bit_size: 8
- name: CRCPR
description: CRC polynomial register
byte_offset: 16
@ -171,13 +175,6 @@ fieldset/CRCPR:
description: CRC polynomial register
bit_offset: 0
bit_size: 16
fieldset/DR:
description: data register
fields:
- name: DR
description: Data register
bit_offset: 0
bit_size: 16
fieldset/I2SCFGR:
description: I2S configuration register
fields:

40
data/registers/spi_v3.yaml
View File

@ -31,16 +31,34 @@ block/SPI:
byte_offset: 24
access: Write
fieldset: IFCR
- name: TXDR
- name: TXDR32
description: Transmit Data Register
byte_offset: 32
access: Write
fieldset: TXDR
- name: RXDR
- name: TXDR16
description: Transmit Data Register - half-word sized
byte_offset: 32
bit_size: 16
access: Write
- name: TXDR8
description: Transmit Data Register - byte sized
byte_offset: 32
bit_size: 8
access: Write
- name: RXDR32
description: Receive Data Register
byte_offset: 48
access: Read
fieldset: RXDR
- name: RXDR16
description: Receive Data Register - half-word sized
byte_offset: 48
bit_size: 16
access: Read
- name: RXDR8
description: Receive Data Register - byte sized
byte_offset: 48
bit_size: 8
access: Read
- name: CRCPOLY
description: Polynomial Register
byte_offset: 64
@ -324,13 +342,6 @@ fieldset/RXCRC:
description: CRC register for receiver
bit_offset: 0
bit_size: 32
fieldset/RXDR:
description: Receive Data Register
fields:
- name: RXDR
description: Receive data register
bit_offset: 0
bit_size: 32
fieldset/SR:
description: Status Register
fields:
@ -407,13 +418,6 @@ fieldset/TXCRC:
description: CRC register for transmitter
bit_offset: 0
bit_size: 32
fieldset/TXDR:
description: Transmit Data Register
fields:
- name: TXDR
description: Transmit data register
bit_offset: 0
bit_size: 32
fieldset/UDRDR:
description: Underrun Data Register
fields:

40
data/registers/spi_v4.yaml
View File

@ -31,16 +31,34 @@ block/SPI:
byte_offset: 24
access: Write
fieldset: IFCR
- name: TXDR
- name: TXDR32
description: Transmit Data Register
byte_offset: 32
access: Write
fieldset: TXDR
- name: RXDR
- name: TXDR16
description: Transmit Data Register - half-word sized
byte_offset: 32
bit_size: 16
access: Write
- name: TXDR8
description: Transmit Data Register - byte sized
byte_offset: 32
bit_size: 8
access: Write
- name: RXDR32
description: Receive Data Register
byte_offset: 48
access: Read
fieldset: RXDR
- name: RXDR16
description: Receive Data Register - half-word sized
byte_offset: 48
bit_size: 16
access: Read
- name: RXDR8
description: Receive Data Register - byte sized
byte_offset: 48
bit_size: 8
access: Read
- name: CRCPOLY
description: Polynomial Register
byte_offset: 64
@ -323,13 +341,6 @@ fieldset/RXCRC:
description: CRC register for receiver
bit_offset: 0
bit_size: 32
fieldset/RXDR:
description: Receive Data Register
fields:
- name: RXDR
description: Receive data register
bit_offset: 0
bit_size: 32
fieldset/SR:
description: Status Register
fields:
@ -402,13 +413,6 @@ fieldset/TXCRC:
description: CRC register for transmitter
bit_offset: 0
bit_size: 32
fieldset/TXDR:
description: Transmit Data Register
fields:
- name: TXDR
description: Transmit data register
bit_offset: 0
bit_size: 32
fieldset/UDRDR:
description: Underrun Data Register
fields:

40
data/registers/spi_v5.yaml
View File

@ -34,16 +34,34 @@ block/SPI:
- name: AUTOCR
byte_offset: 28
fieldset: AUTOCR
- name: TXDR
- name: TXDR32
description: Transmit Data Register
byte_offset: 32
access: Write
fieldset: TXDR
- name: RXDR
- name: TXDR16
description: Transmit Data Register - half-word sized
byte_offset: 32
bit_size: 16
access: Write
- name: TXDR8
description: Transmit Data Register - byte sized
byte_offset: 32
bit_size: 8
access: Write
- name: RXDR32
description: Receive Data Register
byte_offset: 48
access: Read
fieldset: RXDR
- name: RXDR16
description: Receive Data Register - half-word sized
byte_offset: 48
bit_size: 16
access: Read
- name: RXDR8
description: Receive Data Register - byte sized
byte_offset: 48
bit_size: 8
access: Read
- name: CRCPOLY
description: Polynomial Register
byte_offset: 64
@ -348,13 +366,6 @@ fieldset/RXCRC:
description: CRC register for receiver
bit_offset: 0
bit_size: 32
fieldset/RXDR:
description: Receive Data Register
fields:
- name: RXDR
description: Receive data register
bit_offset: 0
bit_size: 32
fieldset/SR:
description: Status Register
fields:
@ -427,13 +438,6 @@ fieldset/TXCRC:
description: CRC register for transmitter
bit_offset: 0
bit_size: 32
fieldset/TXDR:
description: Transmit Data Register
fields:
- name: TXDR
description: Transmit data register
bit_offset: 0
bit_size: 32
fieldset/UDRDR:
description: Underrun Data Register
fields: