From 3e7e385ee72e42cbd3868884872da9147320fced Mon Sep 17 00:00:00 2001 From: Lucas Granberg Date: Wed, 8 Feb 2023 20:47:24 +0200 Subject: [PATCH 1/4] Add new RNG version v2 matching stm32wl chips --- data/registers/rng_v2.yaml | 102 +++++++++++++++++++++++++++++++++++++ src/chips.rs | 2 +- 2 files changed, 103 insertions(+), 1 deletion(-) create mode 100644 data/registers/rng_v2.yaml diff --git a/data/registers/rng_v2.yaml b/data/registers/rng_v2.yaml new file mode 100644 index 0000000..995467d --- /dev/null +++ b/data/registers/rng_v2.yaml @@ -0,0 +1,102 @@ +--- +block/RNG: + description: Random number generator + items: + - name: CR + description: control register + byte_offset: 0 + fieldset: CR + - name: SR + description: status register + byte_offset: 4 + fieldset: SR + - name: DR + description: data register + byte_offset: 8 + access: Read + - name: HTCR + description: health test control register + byte_offset: 16 +fieldset/CR: + description: control register + fields: + - name: RNGEN + description: True random number generator enable + bit_offset: 2 + bit_size: 1 + - name: IE + description: Interrupt Enable + bit_offset: 3 + bit_size: 1 + - name: CED + description: Clock error detection + bit_offset: 5 + bit_size: 1 + - name: RNG_CONFIG3 + description: RNG configuration 3 + bit_offset: 8 + bit_size: 4 + - name: NISTC + description: Non NIST compliant + bit_offset: 12 + bit_size: 1 + enum: NISTC + - name: RNG_CONFIG2 + description: RNG configuration 2 + bit_offset: 13 + bit_size: 3 + - name: CLKDIV + description: Clock divider factor + bit_offset: 16 + bit_size: 4 + - name: RNG_CONFIG1 + description: RNG configuration 1 + bit_offset: 20 + bit_size: 6 + - name: CONDRST + description: Conditioning soft reset + bit_offset: 30 + bit_size: 1 + - name: CONFIGLOCK + description: Config Lock + bit_offset: 31 + bit_size: 1 +fieldset/SR: + description: status register + fields: + - name: DRDY + description: Data Ready + bit_offset: 0 + bit_size: 1 + - name: CECS + description: Clock error current status + bit_offset: 1 + bit_size: 1 + - name: SECS + description: Seed error current status + bit_offset: 2 + bit_size: 1 + - name: CEIS + description: Clock error interrupt status + bit_offset: 5 + bit_size: 1 + - name: SEIS + description: Seed error interrupt status + bit_offset: 6 + bit_size: 1 +fieldset/HTCR: + description: health test control register + fields: + - name: HTCFG + description: health test configuration + bit_offset: 0 + bit_size: 32 +enum/NISTC: + bit_size: 1 + variants: + - name: Default + description: Hardware default values for NIST compliant RNG. In this configuration per 128-bit output two conditioning loops are performed and 256 bits of noise source are used + value: 0 + - name: Custom + description: Custom values for NIST compliant RNG + value: 1 \ No newline at end of file diff --git a/src/chips.rs b/src/chips.rs index 54f72f6..deda3aa 100644 --- a/src/chips.rs +++ b/src/chips.rs @@ -129,7 +129,7 @@ impl PeriMatcher { (".*:RNG:rng1_v1_1", ("rng", "v1", "RNG")), (".*:RNG:rng1_v2_0", ("rng", "v1", "RNG")), (".*:RNG:rng1_v2_1", ("rng", "v1", "RNG")), - (".*:RNG:rng1_v3_1", ("rng", "v1", "RNG")), + (".*:RNG:rng1_v3_1", ("rng", "v2", "RNG")), (".*:SPI:spi2_v1_4", ("spi", "f1", "SPI")), (".*:SPI:spi2s1_v2_1", ("spi", "v1", "SPI")), (".*:SPI:spi2s1_v2_2", ("spi", "v1", "SPI")), From 2c547bd506bcd919d44c68c1ac1b8d55ec31a20c Mon Sep 17 00:00:00 2001 From: Lucas Granberg Date: Wed, 8 Feb 2023 21:46:32 +0200 Subject: [PATCH 2/4] map rng_v2 to U5 and L5 series chips --- src/chips.rs | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/chips.rs b/src/chips.rs index deda3aa..bde6441 100644 --- a/src/chips.rs +++ b/src/chips.rs @@ -130,6 +130,8 @@ impl PeriMatcher { (".*:RNG:rng1_v2_0", ("rng", "v1", "RNG")), (".*:RNG:rng1_v2_1", ("rng", "v1", "RNG")), (".*:RNG:rng1_v3_1", ("rng", "v2", "RNG")), + ("STM32U5.*:RNG:.*", ("rng", "v2", "RNG")), + ("STM32L5.*:RNG:.*", ("rng", "v2", "RNG")), (".*:SPI:spi2_v1_4", ("spi", "f1", "SPI")), (".*:SPI:spi2s1_v2_1", ("spi", "v1", "SPI")), (".*:SPI:spi2s1_v2_2", ("spi", "v1", "SPI")), From 7353e48dc909a535c5fcfd1cb9405ca511e1306d Mon Sep 17 00:00:00 2001 From: Lucas Granberg Date: Thu, 9 Feb 2023 09:57:59 +0200 Subject: [PATCH 3/4] fix perimap ordering to trigger the right version for L5 --- src/chips.rs | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/chips.rs b/src/chips.rs index bde6441..4162ac7 100644 --- a/src/chips.rs +++ b/src/chips.rs @@ -126,12 +126,12 @@ impl PeriMatcher { (".*:LPUART:sci3_v1_2", ("lpuart", "v2", "LPUART")), (".*:LPUART:sci3_v1_3", ("lpuart", "v2", "LPUART")), (".*:LPUART:sci3_v1_4", ("lpuart", "v2", "LPUART")), + ("STM32L5.*:RNG:.*", ("rng", "v2", "RNG")), + ("STM32U5.*:RNG:.*", ("rng", "v2", "RNG")), (".*:RNG:rng1_v1_1", ("rng", "v1", "RNG")), (".*:RNG:rng1_v2_0", ("rng", "v1", "RNG")), (".*:RNG:rng1_v2_1", ("rng", "v1", "RNG")), (".*:RNG:rng1_v3_1", ("rng", "v2", "RNG")), - ("STM32U5.*:RNG:.*", ("rng", "v2", "RNG")), - ("STM32L5.*:RNG:.*", ("rng", "v2", "RNG")), (".*:SPI:spi2_v1_4", ("spi", "f1", "SPI")), (".*:SPI:spi2s1_v2_1", ("spi", "v1", "SPI")), (".*:SPI:spi2s1_v2_2", ("spi", "v1", "SPI")), From 04be778fa146a5ea3456b098c3797a98742a0088 Mon Sep 17 00:00:00 2001 From: Lucas Granberg Date: Thu, 9 Feb 2023 10:27:18 +0200 Subject: [PATCH 4/4] use rng1_v4_1 instead of special case for U5 --- src/chips.rs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/chips.rs b/src/chips.rs index 4162ac7..2bbc5d5 100644 --- a/src/chips.rs +++ b/src/chips.rs @@ -127,11 +127,11 @@ impl PeriMatcher { (".*:LPUART:sci3_v1_3", ("lpuart", "v2", "LPUART")), (".*:LPUART:sci3_v1_4", ("lpuart", "v2", "LPUART")), ("STM32L5.*:RNG:.*", ("rng", "v2", "RNG")), - ("STM32U5.*:RNG:.*", ("rng", "v2", "RNG")), (".*:RNG:rng1_v1_1", ("rng", "v1", "RNG")), (".*:RNG:rng1_v2_0", ("rng", "v1", "RNG")), (".*:RNG:rng1_v2_1", ("rng", "v1", "RNG")), (".*:RNG:rng1_v3_1", ("rng", "v2", "RNG")), + (".*:RNG:rng1_v4_1", ("rng", "v2", "RNG")), (".*:SPI:spi2_v1_4", ("spi", "f1", "SPI")), (".*:SPI:spi2s1_v2_1", ("spi", "v1", "SPI")), (".*:SPI:spi2s1_v2_2", ("spi", "v1", "SPI")),