[manual] Deduplicate PLLSRC entry of RCC_CFGR register

I have manually removed the single bit PLLSRC under RCC_CFGR register,
and I have manually updated the `enum/PLLSRC` to have 3 variants to match
the bit_size of PLLSRC.

data/registers/rcc_f3.yaml

@@ -609,11 +609,6 @@ fieldset/CFGR:
       bit_offset: 15
       bit_size: 2
       enum: PLLSRC
-    - name: PLLSRC
-      description: PLL entry clock source
-      bit_offset: 16
-      bit_size: 1
-      enum: PLLSRC
     - name: PLLXTPRE
       description: HSE divider for PLL entry
       bit_offset: 17
@@ -1274,14 +1269,17 @@ enum/PLLNODIV:
       description: PLL is not divided for MCO
       value: 1
 enum/PLLSRC:
-  bit_size: 1
+  bit_size: 2
   variants:
     - name: HSI_Div2
       description: HSI divided by 2 selected as PLL input clock
       value: 0
+    - name: HSI_Div_PREDIV
+      description: HSI divided by PREDIV selected as PLL input clock
+      value: 1
     - name: HSE_Div_PREDIV
       description: HSE divided by PREDIV selected as PLL input clock
-      value: 1
+      value: 2
 enum/PLLXTPRE:
   bit_size: 1
   variants: