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[manual] Deduplicate PLLSRC entry of RCC_CFGR register

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I have manually removed the single bit PLLSRC under RCC_CFGR register,
and I have manually updated the `enum/PLLSRC` to have 3 variants to match
the bit_size of PLLSRC.
This commit is contained in:
VasanthakumarV 2021-12-09 13:24:25 +05:30
parent 3275e41057
commit fdf0cc95b9
1 changed files with 5 additions and 7 deletions
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12
data/registers/rcc_f3.yaml
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@ -609,11 +609,6 @@ fieldset/CFGR:
bit_offset: 15 bit_offset: 15
bit_size: 2 bit_size: 2
enum: PLLSRC enum: PLLSRC
- name: PLLSRC
description: PLL entry clock source
bit_offset: 16
bit_size: 1
enum: PLLSRC
- name: PLLXTPRE - name: PLLXTPRE
description: HSE divider for PLL entry description: HSE divider for PLL entry
bit_offset: 17 bit_offset: 17
@ -1274,14 +1269,17 @@ enum/PLLNODIV:
description: PLL is not divided for MCO description: PLL is not divided for MCO
value: 1 value: 1
enum/PLLSRC: enum/PLLSRC:
bit_size: 1 bit_size: 2
variants: variants:
- name: HSI_Div2 - name: HSI_Div2
description: HSI divided by 2 selected as PLL input clock description: HSI divided by 2 selected as PLL input clock
value: 0 value: 0
- name: HSI_Div_PREDIV
description: HSI divided by PREDIV selected as PLL input clock
value: 1
- name: HSE_Div_PREDIV - name: HSE_Div_PREDIV
description: HSE divided by PREDIV selected as PLL input clock description: HSE divided by PREDIV selected as PLL input clock
value: 1 value: 2
enum/PLLXTPRE: enum/PLLXTPRE:
bit_size: 1 bit_size: 1
variants: variants: