Merge pull request #403 from eZioPan/iwdg_v3

iwdg v3

data/registers/iwdg_v3.yaml

@@ -0,0 +1,137 @@
+block/IWDG:
+  description: Independent watchdog
+  items:
+  - name: KR
+    description: Key register
+    byte_offset: 0
+    fieldset: KR
+  - name: PR
+    description: Prescaler register
+    byte_offset: 4
+    fieldset: PR
+  - name: RLR
+    description: Reload register
+    byte_offset: 8
+    fieldset: RLR
+  - name: SR
+    description: Status register
+    byte_offset: 12
+    fieldset: SR
+  - name: WINR
+    description: Window register
+    byte_offset: 16
+    fieldset: WINR
+  - name: EWCR
+    description: IWDG early wakeup interrupt register.
+    byte_offset: 20
+    fieldset: EWCR
+fieldset/EWCR:
+  description: IWDG early wakeup interrupt register.
+  fields:
+  - name: EWIT
+    description: 'Watchdog counter window value These bits are write access protected (see ). They are written by software to define at which position of the IWDCNT down-counter the early wakeup interrupt must be generated. The early interrupt is generated when the IWDCNT is lower or equal to EWIT[11:0] - 1. EWIT[11:0] must be bigger than 1. An interrupt is generated only if EWIE = 1. The EWU bit in the must be reset to be able to change the reload value. Note: Reading this register returns the Early wakeup comparator value and the Interrupt enable bit from the VDD voltage domain. This value may not be up to date/valid if a write operation to this register is ongoing, hence the value read from this register is valid only when the EWU bit in the is reset.'
+    bit_offset: 0
+    bit_size: 12
+  - name: EWIC
+    description: Watchdog early interrupt acknowledge The software must write a 1 into this bit in order to acknowledge the early wakeup interrupt and to clear the EWIF flag. Writing 0 has not effect, reading this flag returns a 0.
+    bit_offset: 14
+    bit_size: 1
+  - name: EWIE
+    description: Watchdog early interrupt enable Set and reset by software. The EWU bit in the must be reset to be able to change the value of this bit.
+    bit_offset: 15
+    bit_size: 1
+fieldset/KR:
+  description: Key register
+  fields:
+  - name: KEY
+    description: Key value (write only, read 0000h)
+    bit_offset: 0
+    bit_size: 16
+    enum: KEY
+fieldset/PR:
+  description: Prescaler register
+  fields:
+  - name: PR
+    description: Prescaler divider
+    bit_offset: 0
+    bit_size: 4
+    enum: PR
+fieldset/RLR:
+  description: Reload register
+  fields:
+  - name: RL
+    description: Watchdog counter reload value
+    bit_offset: 0
+    bit_size: 12
+fieldset/SR:
+  description: Status register
+  fields:
+  - name: PVU
+    description: Watchdog prescaler value update
+    bit_offset: 0
+    bit_size: 1
+  - name: RVU
+    description: Watchdog counter reload value update
+    bit_offset: 1
+    bit_size: 1
+  - name: WVU
+    description: Watchdog counter window value update
+    bit_offset: 2
+    bit_size: 1
+  - name: EWU
+    description: Watchdog interrupt comparator value update This bit is set by hardware to indicate that an update of the interrupt comparator value (EWIT[11:0]) or an update of the EWIE is ongoing. It is reset by hardware when the update operation is completed in the VDD voltage domain (takes up to three periods of the IWDG kernel clock iwdg_ker_ck). The EWIT[11:0] and EWIE fields can be updated only when EWU bit is reset.
+    bit_offset: 3
+    bit_size: 1
+  - name: EWIF
+    description: Watchdog early interrupt flag This bit is set to ‘1’ by hardware in order to indicate that an early interrupt is pending. This bit must be cleared by the software by writing the bit EWIC of IWDG_EWCR register to ‘1’.
+    bit_offset: 14
+    bit_size: 1
+fieldset/WINR:
+  description: Window register
+  fields:
+  - name: WIN
+    description: Watchdog counter window value
+    bit_offset: 0
+    bit_size: 12
+enum/KEY:
+  bit_size: 16
+  variants:
+  - name: Enable
+    description: Enable access to PR, RLR and WINR registers (0x5555)
+    value: 21845
+  - name: Reset
+    description: Reset the watchdog value (0xAAAA)
+    value: 43690
+  - name: Start
+    description: Start the watchdog (0xCCCC)
+    value: 52428
+enum/PR:
+  bit_size: 4
+  variants:
+  - name: DivideBy4
+    description: Divider /4
+    value: 0
+  - name: DivideBy8
+    description: Divider /8
+    value: 1
+  - name: DivideBy16
+    description: Divider /16
+    value: 2
+  - name: DivideBy32
+    description: Divider /32
+    value: 3
+  - name: DivideBy64
+    description: Divider /64
+    value: 4
+  - name: DivideBy128
+    description: Divider /128
+    value: 5
+  - name: DivideBy256
+    description: Divider /256
+    value: 6
+  - name: DivideBy512
+    description: Divider /512
+    value: 7
+  - name: DivideBy1024
+    description: Divider /1024
+    value: 8

stm32-data-gen/src/chips.rs

@@ -244,6 +244,7 @@ impl PeriMatcher {
             ("STM32H5.*:SBS:.*", ("syscfg", "h5", "SYSCFG")),
             (".*:IWDG:iwdg1_v1_1", ("iwdg", "v1", "IWDG")),
             (".*:IWDG:iwdg1_v2_0", ("iwdg", "v2", "IWDG")),
+            (".*:IWDG:iwdg1_v3_0", ("iwdg", "v3", "IWDG")),
             (".*:WWDG:wwdg1_v1_0", ("wwdg", "v1", "WWDG")),
             (".*:WWDG:wwdg1_v2_0", ("wwdg", "v2", "WWDG")),
             (".*:JPEG:jpeg1_v1_0", ("jpeg", "v1", "JPEG")),