Extract ADCv3 (arrayification is not possible, slight diffs in field widths)

Extract ADC_COMMON
Create framework for extra synthetic hand-crafted peripherals.
Add VREFINTCAL reg/block/peripheral for STM32L4+.

data/extra/family/STM32L4+.yaml

@@ -0,0 +1,4 @@
+peripherals:
+    VREFINTCAL: 
+        address: 0x1FFF75AA
+        block: vrefintcal_v1/VREFINTCAL

data/registers/adccommon_v3.yaml

@@ -1,5 +1,5 @@
 ---
-block/ADC_Common:
+block/ADC_COMMON:
   description: Analog-to-Digital Converter
   items:
     - name: CSR

data/registers/vrefintcal_v1.yaml

@@ -0,0 +1,15 @@
+---
+block/VREFINTCAL:
+  description: VREFINT Factory Calibration
+  items:
+    - name: DATA
+      description: Factory calibration
+      byte_offset: 0
+      fieldset: DATA
+fieldset/DATA:
+  description: Factory calibration data
+  fields:
+    - name: VALUE
+      description: Calibration value
+      bit_offset: 0
+      bit_size: 16

parse.py

@@ -239,6 +239,7 @@ perimap = [
     ('.*:DAC:dacif_v2_0', 'dac_v2/DAC'),
     ('.*:DAC:dacif_v3_0', 'dac_v2/DAC'),
     ('.*:ADC:aditf5_v2_0', 'adc_v3/ADC'),
+    ('.*:ADC_COMMON:aditf5_v2_0', 'adccommon_v3/ADC_COMMON'),
     ('STM32F4.*:SYS:.*', 'syscfg_f4/SYSCFG'),
     ('STM32L4.*:SYS:.*', 'syscfg_l4/SYSCFG'),
     ('STM32L0.*:SYS:.*', 'syscfg_l0/SYSCFG'),
@@ -361,6 +362,8 @@ def parse_chips():
             rcc = removesuffix(rcc, '_rcc_v1_0')
 
             core = r['Core']
+            family = r['@Family']
+
             # multicores have a list here. Just keep the first, to not break the schema.
             if isinstance(core, list):
                 core = core[0]
@@ -368,7 +371,7 @@ def parse_chips():
             if chip_name not in chips:
                 chips[chip_name] = OrderedDict({
                     'name': chip_name,
-                    'family': r['@Family'],
+                    'family': family,
                     'line': r['@Line'],
                     'core': core,
                     'flash': flash,
@@ -387,10 +390,12 @@ def parse_chips():
                 'package': r['@Package'],
             }))
 
+
             # Some packages have some peripehrals removed because the package had to
             # remove GPIOs useful for that peripheral. So we merge all peripherals from all packages.
             peris = chips[chip_name]['peripherals']
             pins = chips[chip_name]['pins']
+
             for ip in r['IP']:
                 pname = ip['@InstanceName']
                 pkind = ip['@Name']+':'+ip['@Version']
@@ -400,6 +405,9 @@ def parse_chips():
                     pname = 'SYSCFG'
                 if pname in FAKE_PERIPHERALS:
                     continue
+                if pname.startswith('ADC'):
+                    if not pname + '_COMMON' in peris:
+                        peris[pname + '_COMMON'] = ip['@Name'] + '_COMMON:'+removesuffix(ip['@Version'], '_Cube')
                 peris[pname] = pkind
                 pins[pname] = []
 
@@ -477,6 +485,14 @@ def parse_chips():
 
             peris[pname] = p
 
+        family_extra = "data/extra/family/" + chip['family'] + ".yaml";
+        if os.path.exists(family_extra) :
+            with open(family_extra) as extra_f:
+                extra = yaml.load(extra_f, Loader=yaml.SafeLoader)
+                for (extra_name, extra_p) in extra['peripherals'].items():
+                    print(f'adding {extra_name}')
+                    peris[extra_name] = extra_p
+
         # Handle GPIO specially.
         for p in range(20):
             port = 'GPIO' + chr(ord('A')+p)