Merge pull request #189 from dognotdog/main
adding STM32G4 flash peripheral
This commit is contained in:
Dario Nieuwenhuis
GitHub
commit
fc4d4ddd3d
382
data/registers/flash_g4.yaml
Normal file
382
data/registers/flash_g4.yaml
Normal file
@ -0,0 +1,382 @@
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---
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block/FLASH:
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description: Flash
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items:
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- name: ACR
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description: Access control register
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byte_offset: 0
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fieldset: ACR
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- name: PDKEYR
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description: Power down key register
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byte_offset: 4
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access: Write
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fieldset: PDKEYR
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- name: KEYR
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description: Flash key register
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byte_offset: 8
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access: Write
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fieldset: KEYR
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- name: OPTKEYR
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description: Option byte key register
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byte_offset: 12
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access: Write
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fieldset: OPTKEYR
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- name: SR
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description: Status register
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byte_offset: 16
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fieldset: SR
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- name: CR
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description: Flash control register
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byte_offset: 20
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fieldset: CR
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- name: ECCR
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description: Flash ECC register
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byte_offset: 24
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fieldset: ECCR
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- name: OPTR
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description: Flash option register
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byte_offset: 32
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fieldset: OPTR
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- name: PCROP1SR
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description: Flash Bank 1 PCROP Start address register
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byte_offset: 36
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fieldset: PCROP1SR
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- name: PCROP1ER
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description: Flash Bank 1 PCROP End address register
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byte_offset: 40
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fieldset: PCROP1ER
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- name: WRP1AR
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description: Flash Bank 1 WRP area A address register
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byte_offset: 44
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fieldset: WRP1AR
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- name: WRP1BR
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description: Flash Bank 1 WRP area B address register
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byte_offset: 48
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fieldset: WRP1BR
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- name: SEC1R
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description: securable area bank1 register
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byte_offset: 112
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fieldset: SEC1R
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fieldset/ACR:
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description: Access control register
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fields:
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- name: LATENCY
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description: Latency
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bit_offset: 0
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bit_size: 4
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- name: PRFTEN
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description: Prefetch enable
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bit_offset: 8
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bit_size: 1
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- name: ICEN
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description: Instruction cache enable
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bit_offset: 9
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bit_size: 1
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- name: DCEN
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description: Data cache enable
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bit_offset: 10
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bit_size: 1
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- name: ICRST
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description: Instruction cache reset
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bit_offset: 11
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bit_size: 1
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- name: DCRST
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description: Data cache reset
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bit_offset: 12
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bit_size: 1
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- name: RUN_PD
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description: Flash Power-down mode during Low-power run mode
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bit_offset: 13
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bit_size: 1
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- name: SLEEP_PD
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description: Flash Power-down mode during Low-power sleep mode
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bit_offset: 14
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bit_size: 1
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- name: DBG_SWEN
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description: Debug software enable
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bit_offset: 18
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bit_size: 1
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fieldset/CR:
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description: Flash control register
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fields:
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- name: PG
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description: Programming
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bit_offset: 0
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bit_size: 1
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- name: PER
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description: Page erase
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bit_offset: 1
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bit_size: 1
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- name: MER1
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description: Bank 1 Mass erase
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bit_offset: 2
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bit_size: 1
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- name: PNB
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description: Page number
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bit_offset: 3
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bit_size: 7
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- name: STRT
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description: Start
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bit_offset: 16
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bit_size: 1
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- name: OPTSTRT
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description: Options modification start
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bit_offset: 17
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bit_size: 1
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- name: FSTPG
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description: Fast programming
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bit_offset: 18
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bit_size: 1
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- name: EOPIE
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description: End of operation interrupt enable
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bit_offset: 24
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bit_size: 1
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- name: ERRIE
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description: Error interrupt enable
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bit_offset: 25
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bit_size: 1
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- name: RDERRIE
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description: PCROP read error interrupt enable
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bit_offset: 26
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bit_size: 1
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- name: OBL_LAUNCH
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description: Force the option byte loading
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bit_offset: 27
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bit_size: 1
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- name: SEC_PROT1
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description: Securable memory area protection enable
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bit_offset: 28
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bit_size: 1
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- name: OPTLOCK
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description: Options Lock
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bit_offset: 30
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bit_size: 1
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- name: LOCK
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description: FLASH_CR Lock
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bit_offset: 31
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bit_size: 1
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fieldset/ECCR:
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description: Flash ECC register
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fields:
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- name: ADDR_ECC
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description: ECC fail address
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bit_offset: 0
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bit_size: 19
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- name: BK_ECC
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description: ECC fail for Corrected ECC Error or Double ECC Error in info block
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bit_offset: 21
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bit_size: 1
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- name: SYSF_ECC
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description: ECC fail for Corrected ECC Error or Double ECC Error in info block
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bit_offset: 22
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bit_size: 1
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- name: ECCIE
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description: ECC correction interrupt enable
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bit_offset: 24
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bit_size: 1
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- name: ECCC2
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description: ECC correction
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bit_offset: 28
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bit_size: 1
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- name: ECCD2
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description: ECC2 detection
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bit_offset: 29
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bit_size: 1
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- name: ECCC
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description: ECC correction
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bit_offset: 30
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bit_size: 1
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- name: ECCD
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description: ECC detection
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bit_offset: 31
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bit_size: 1
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fieldset/KEYR:
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description: Flash key register
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fields:
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- name: KEYR
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description: KEYR
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bit_offset: 0
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bit_size: 32
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fieldset/OPTKEYR:
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description: Option byte key register
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fields:
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- name: OPTKEYR
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description: Option byte key
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bit_offset: 0
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bit_size: 32
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fieldset/OPTR:
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description: Flash option register
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fields:
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- name: RDP
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description: Read protection level
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bit_offset: 0
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bit_size: 8
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- name: BOR_LEV
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description: BOR reset Level
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bit_offset: 8
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bit_size: 3
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- name: nRST_STOP
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description: nRST_STOP
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bit_offset: 12
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bit_size: 1
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- name: nRST_STDBY
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description: nRST_STDBY
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bit_offset: 13
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bit_size: 1
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- name: nRST_SHDW
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description: nRST_SHDW
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bit_offset: 14
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bit_size: 1
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- name: IDWG_SW
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description: Independent watchdog selection
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bit_offset: 16
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bit_size: 1
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- name: IWDG_STOP
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description: Independent watchdog counter freeze in Stop mode
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bit_offset: 17
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bit_size: 1
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- name: IWDG_STDBY
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description: Independent watchdog counter freeze in Standby mode
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bit_offset: 18
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bit_size: 1
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- name: WWDG_SW
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description: Window watchdog selection
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bit_offset: 19
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bit_size: 1
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- name: nBOOT1
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description: Boot configuration
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bit_offset: 23
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bit_size: 1
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- name: SRAM2_PE
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description: SRAM2 parity check enable
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bit_offset: 24
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bit_size: 1
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- name: SRAM2_RST
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description: SRAM2 Erase when system reset
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bit_offset: 25
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bit_size: 1
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- name: nSWBOOT0
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description: nSWBOOT0
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bit_offset: 26
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bit_size: 1
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- name: nBOOT0
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description: nBOOT0 option bit
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bit_offset: 27
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bit_size: 1
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- name: NRST_MODE
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description: NRST_MODE
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bit_offset: 28
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bit_size: 2
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- name: IRHEN
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description: Internal reset holder enable bit
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bit_offset: 30
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bit_size: 1
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fieldset/PCROP1ER:
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description: Flash Bank 1 PCROP End address register
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fields:
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- name: PCROP1_END
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description: Bank 1 PCROP area end offset
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bit_offset: 0
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bit_size: 15
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- name: PCROP_RDP
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description: PCROP area preserved when RDP level decreased
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bit_offset: 31
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bit_size: 1
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fieldset/PCROP1SR:
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description: Flash Bank 1 PCROP Start address register
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fields:
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- name: PCROP1_STRT
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description: Bank 1 PCROP area start offset
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bit_offset: 0
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bit_size: 15
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fieldset/PDKEYR:
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description: Power down key register
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fields:
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- name: PDKEYR
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description: RUN_PD in FLASH_ACR key
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bit_offset: 0
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bit_size: 32
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fieldset/SEC1R:
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description: securable area bank1 register
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fields:
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- name: SEC_SIZE1
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description: SEC_SIZE1
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bit_offset: 0
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bit_size: 8
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- name: BOOT_LOCK
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description: used to force boot from user area
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bit_offset: 16
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bit_size: 1
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fieldset/SR:
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description: Status register
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fields:
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- name: EOP
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description: End of operation
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bit_offset: 0
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bit_size: 1
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- name: OPERR
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description: Operation error
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bit_offset: 1
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bit_size: 1
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- name: PROGERR
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description: Programming error
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bit_offset: 3
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bit_size: 1
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- name: WRPERR
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description: Write protected error
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bit_offset: 4
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bit_size: 1
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- name: PGAERR
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description: Programming alignment error
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bit_offset: 5
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bit_size: 1
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- name: SIZERR
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description: Size error
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bit_offset: 6
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bit_size: 1
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- name: PGSERR
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description: Programming sequence error
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bit_offset: 7
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bit_size: 1
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- name: MISERR
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description: Fast programming data miss error
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bit_offset: 8
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bit_size: 1
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- name: FASTERR
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description: Fast programming error
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bit_offset: 9
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bit_size: 1
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- name: RDERR
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description: PCROP read error
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bit_offset: 14
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bit_size: 1
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- name: OPTVERR
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description: Option validity error
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bit_offset: 15
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bit_size: 1
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- name: BSY
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description: Busy
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bit_offset: 16
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bit_size: 1
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fieldset/WRP1AR:
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description: Flash Bank 1 WRP area A address register
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fields:
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- name: WRP1A_STRT
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description: Bank 1 WRP first area start offset
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bit_offset: 0
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bit_size: 7
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- name: WRP1A_END
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description: Bank 1 WRP first area A end offset
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bit_offset: 16
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bit_size: 7
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fieldset/WRP1BR:
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description: Flash Bank 1 WRP area B address register
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fields:
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- name: WRP1B_STRT
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description: Bank 1 WRP second area B end offset
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bit_offset: 0
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bit_size: 7
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- name: WRP1B_END
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description: Bank 1 WRP second area B start offset
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bit_offset: 16
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bit_size: 7
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@ -311,6 +311,7 @@ impl PeriMatcher {
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("STM32WL.*:FLASH:.*", ("flash", "wl", "FLASH")),
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("STM32C0.*:FLASH:.*", ("flash", "c0", "FLASH")),
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("STM32G0.*:FLASH:.*", ("flash", "g0", "FLASH")),
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("STM32G4.*:FLASH:.*", ("flash", "g4", "FLASH")),
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("STM32H50.*:FLASH:.*", ("flash", "h50", "FLASH")),
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("STM32H5.*:FLASH:.*", ("flash", "h5", "FLASH")),
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("STM32F107.*:ETH:.*", ("eth", "v1a", "ETH")),
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