rcc: consistency fixes on f2

This commit is contained in:
Dario Nieuwenhuis 2023-11-13 01:47:21 +01:00
parent c551c07bf1
commit fbb8f77326

View File

@ -1147,14 +1147,16 @@ fieldset/PLLCFGR:
fieldset/PLLI2SCFGR:
description: PLLI2S configuration register
fields:
- name: PLLI2SN
- name: PLLN
description: PLLI2S multiplication factor for VCO
bit_offset: 6
bit_size: 9
- name: PLLI2SR
enum: PLLN
- name: PLLR
description: PLLI2S division factor for I2S clocks
bit_offset: 28
bit_size: 3
enum: PLLR
fieldset/SSCGR:
description: spread spectrum clock generation register
fields:
@ -1920,6 +1922,21 @@ enum/PLLQ:
value: 14
- name: Div15
value: 15
enum/PLLR:
bit_size: 3
variants:
- name: Div2
value: 2
- name: Div3
value: 3
- name: Div4
value: 4
- name: Div5
value: 5
- name: Div6
value: 6
- name: Div7
value: 7
enum/PLLSRC:
bit_size: 1
variants: