From f865878b4b6ff7cac30dea17162c4bd1dbd83917 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Timo=20Kr=C3=B6ger?= <timokroeger93@gmail.com>
Date: Tue, 3 Aug 2021 14:42:02 +0200
Subject: [PATCH] rcc_f4: Fix RCC bits

## LPTIM1EN / LPTIMER1EN

Only stm32f413 has LPTIM1 peripheral, ref manual bit names:
LPTIMER1EN, LPTIMER1RST, LPTIMER1LPEN, LPTIMER1SEL

action: Rename to LPTIM1(EN|RST|...) for consistency (matches peripheral name)

## FMC / FSMC

not available as peripheral in the YAML anyway.. TODO: why?

EN and RST

FSMC: f405, f407, f412, f413
FSC: f427, f429, f446, f469

action: none

## CECEN / CAN3EN

mutually exclusive peripherals, alias ok?

CECEN: f446
CAN3EN: f413

action: split off f4x3 yaml, f423 exists, but not available as svd

## USART / UART

all over the place, register names in ref manual not always consistent
stm32 follows a simple rule for the actual peripherals:
USART 1-3, 6
UART 4, 5, 7-10

action: rename enable/rst bits to rules above
---
 data/registers/rcc_f4.yaml | 50 +-------------------------------------
 1 file changed, 1 insertion(+), 49 deletions(-)

diff --git a/data/registers/rcc_f4.yaml b/data/registers/rcc_f4.yaml
index e6e749a..02ec8f2 100644
--- a/data/registers/rcc_f4.yaml
+++ b/data/registers/rcc_f4.yaml
@@ -1565,10 +1565,6 @@ fieldset/APB1ENR:
     bit_size: 1
     description: FMPI2C1 clock enable
     name: FMPI2C1EN
-  - bit_offset: 9
-    bit_size: 1
-    description: LPTimer 1 clock enable
-    name: LPTIMER1EN
   - bit_offset: 27
     bit_size: 1
     description: CAN 3 clock enable
@@ -1696,18 +1692,6 @@ fieldset/APB1LPENR:
     bit_size: 1
     description: FMPI2C1 clock enable during Sleep
     name: FMPI2C1LPEN
-  - bit_offset: 9
-    bit_size: 1
-    description: TIM14 clock enable during Sleep mode
-    name: LPTIMER1LPEN
-  - bit_offset: 19
-    bit_size: 1
-    description: USART4 clock enable during Sleep mode
-    name: USART4LPEN
-  - bit_offset: 20
-    bit_size: 1
-    description: USART5 clock enable during Sleep mode
-    name: USART5LPEN
   - bit_offset: 27
     bit_size: 1
     description: CAN3 clock enable during Sleep mode
@@ -1802,7 +1786,7 @@ fieldset/APB1RSTR:
   - bit_offset: 18
     bit_size: 1
     description: USART 3 reset
-    name: UART3RST
+    name: USART3RST
   - bit_offset: 19
     bit_size: 1
     description: USART 4 reset
@@ -1831,22 +1815,6 @@ fieldset/APB1RSTR:
     bit_size: 1
     description: FMPI2C1 reset
     name: FMPI2C1RST
-  - bit_offset: 18
-    bit_size: 1
-    description: USART3RST
-    name: USART3RST
-  - bit_offset: 9
-    bit_size: 1
-    description: LPTimer1 reset
-    name: LPTIMER1RST
-  - bit_offset: 19
-    bit_size: 1
-    description: USART4 reset
-    name: USART4RST
-  - bit_offset: 20
-    bit_size: 1
-    description: USART5 reset
-    name: USART5RST
   - bit_offset: 27
     bit_size: 1
     description: CAN 3 reset
@@ -2041,18 +2009,10 @@ fieldset/APB2LPENR:
     bit_size: 1
     description: UART9 clock enable during Sleep mode
     name: UART9LPEN
-  - bit_offset: 6
-    bit_size: 1
-    description: USART9 clock enable during Sleep mode
-    name: USART9LPEN
   - bit_offset: 7
     bit_size: 1
     description: UART10 clock enable during Sleep mode
     name: UART10LPEN
-  - bit_offset: 7
-    bit_size: 1
-    description: USART10 clock enable during Sleep mode
-    name: USART10LPEN
   - bit_offset: 22
     bit_size: 1
     description: SAI1 clock enable during Sleep mode
@@ -2140,14 +2100,6 @@ fieldset/APB2RSTR:
     bit_size: 1
     description: UART9 reset
     name: UART9RST
-  - bit_offset: 6
-    bit_size: 1
-    description: USART9 reset
-    name: USART9RST
-  - bit_offset: 7
-    bit_size: 1
-    description: USART10 reset
-    name: SART10RST
   - bit_offset: 7
     bit_size: 1
     description: UART10 reset