From f0532de10ae0c8ff6c8746beed0667ae9a2055ae Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Tue, 12 Mar 2024 15:03:34 +0800 Subject: [PATCH 1/3] cordic: add `scale` enum --- data/registers/cordic_v1.yaml | 33 ++++++++++++++++++++++++++++++++- 1 file changed, 32 insertions(+), 1 deletion(-) diff --git a/data/registers/cordic_v1.yaml b/data/registers/cordic_v1.yaml index 0cfeb42..f925b3a 100644 --- a/data/registers/cordic_v1.yaml +++ b/data/registers/cordic_v1.yaml @@ -25,9 +25,13 @@ fieldset/CSR: bit_size: 4 enum: PRECISION - name: SCALE - description: Scaling factor (2^-n for arguments, 2^n for results). + description: |- + Scaling factor. + Input value has been multiplied by 2^(-n) before for argument. + Output value will need to be multiplied by 2^n later for results. bit_offset: 8 bit_size: 3 + enum: Scale - name: IEN description: Enable interrupt. bit_offset: 16 @@ -154,6 +158,33 @@ enum/PRECISION: - name: Iters60 description: 60 iterations. value: 15 +enum/Scale: + bit_size: 3 + variants: + - name: A1_R1 + description: Argument multiplied by 1, result multiplied by 1 + value: 0 + - name: A1o2_R2 + description: Argument multiplied by 1/2, result multiplied by 2 + value: 1 + - name: A1o4_R4 + description: Argument multiplied by 1/4, result multiplied by 4 + value: 2 + - name: A1o8_R8 + description: Argument multiplied by 1/8, result multiplied by 8 + value: 3 + - name: A1o16_R16 + description: Argument multiplied by 1/16, result multiplied by 16 + value: 4 + - name: A1o32_R32 + description: Argument multiplied by 1/32, result multiplied by 32 + value: 5 + - name: A1o64_R64 + description: Argument multiplied by 1/64, result multiplied by 64 + value: 6 + - name: A1o128_R128 + description: Argument multiplied by 1/128, result multiplied by 128 + value: 7 enum/Size: bit_size: 1 variants: From cc525f1b252c91272529cbea1d3d4399b43c60b4 Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Tue, 12 Mar 2024 15:23:40 +0800 Subject: [PATCH 2/3] timer: remove `PSC` fieldset --- data/registers/timer_l0.yaml | 9 +-------- data/registers/timer_v1.yaml | 9 +-------- data/registers/timer_v2.yaml | 9 +-------- 3 files changed, 3 insertions(+), 24 deletions(-) diff --git a/data/registers/timer_l0.yaml b/data/registers/timer_l0.yaml index 333c404..b795a7f 100644 --- a/data/registers/timer_l0.yaml +++ b/data/registers/timer_l0.yaml @@ -142,7 +142,7 @@ block/TIM_CORE: - name: PSC description: prescaler byte_offset: 40 - fieldset: PSC_CORE + bit_size: 16 - name: ARR description: auto-reload register byte_offset: 44 @@ -667,13 +667,6 @@ fieldset/EGR_GP16: description: Trigger generation bit_offset: 6 bit_size: 1 -fieldset/PSC_CORE: - description: prescaler - fields: - - name: PSC - description: Prescaler value - bit_offset: 0 - bit_size: 16 fieldset/SMCR_2CH: description: slave mode control register fields: diff --git a/data/registers/timer_v1.yaml b/data/registers/timer_v1.yaml index 96c208e..e8cd3a3 100644 --- a/data/registers/timer_v1.yaml +++ b/data/registers/timer_v1.yaml @@ -350,7 +350,7 @@ block/TIM_CORE: - name: PSC description: prescaler byte_offset: 40 - fieldset: PSC_CORE + bit_size: 16 - name: ARR description: auto-reload register byte_offset: 44 @@ -1341,13 +1341,6 @@ fieldset/EGR_GP16: description: Trigger generation bit_offset: 6 bit_size: 1 -fieldset/PSC_CORE: - description: prescaler - fields: - - name: PSC - description: Prescaler value - bit_offset: 0 - bit_size: 16 fieldset/RCR_1CH_CMP: description: repetition counter register fields: diff --git a/data/registers/timer_v2.yaml b/data/registers/timer_v2.yaml index d78f891..b3cfab0 100644 --- a/data/registers/timer_v2.yaml +++ b/data/registers/timer_v2.yaml @@ -368,7 +368,7 @@ block/TIM_CORE: - name: PSC description: prescaler byte_offset: 40 - fieldset: PSC_CORE + bit_size: 16 - name: ARR description: auto-reload register (Dither mode disabled) byte_offset: 44 @@ -1586,13 +1586,6 @@ fieldset/EGR_GP16: description: Trigger generation bit_offset: 6 bit_size: 1 -fieldset/PSC_CORE: - description: prescaler - fields: - - name: PSC - description: Prescaler value - bit_offset: 0 - bit_size: 16 fieldset/RCR_1CH_CMP: description: repetition counter register fields: From 868dec16306e6c2f2d3f1ec5850dda370bd363ec Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Wed, 13 Mar 2024 01:05:52 +0800 Subject: [PATCH 3/3] timer: add 16-bit register info --- data/registers/timer_l0.yaml | 7 +++++++ data/registers/timer_v1.yaml | 13 +++++++++++++ data/registers/timer_v2.yaml | 13 +++++++++++++ 3 files changed, 33 insertions(+) diff --git a/data/registers/timer_l0.yaml b/data/registers/timer_l0.yaml index b795a7f..3e4cb28 100644 --- a/data/registers/timer_l0.yaml +++ b/data/registers/timer_l0.yaml @@ -5,6 +5,7 @@ block/TIM_1CH: - name: CR1 description: control register 1 byte_offset: 0 + bit_size: 16 fieldset: CR1_1CH - name: DIER description: DMA/Interrupt enable register @@ -18,6 +19,7 @@ block/TIM_1CH: description: event generation register byte_offset: 20 access: Write + bit_size: 16 fieldset: EGR_1CH - name: CCMR_Input description: capture/compare mode register 1 (input mode) @@ -73,6 +75,7 @@ block/TIM_2CH: description: event generation register byte_offset: 20 access: Write + bit_size: 16 fieldset: EGR_2CH - name: CCMR_Input description: capture/compare mode register 1 (input mode) @@ -121,6 +124,7 @@ block/TIM_CORE: - name: CR1 description: control register 1 byte_offset: 0 + bit_size: 16 fieldset: CR1_CORE - name: DIER description: DMA/Interrupt enable register @@ -134,6 +138,7 @@ block/TIM_CORE: description: event generation register byte_offset: 20 access: Write + bit_size: 16 fieldset: EGR_CORE - name: CNT description: counter @@ -154,6 +159,7 @@ block/TIM_GP16: - name: CR1 description: control register 1 byte_offset: 0 + bit_size: 16 fieldset: CR1_GP16 - name: CR2 description: control register 2 @@ -175,6 +181,7 @@ block/TIM_GP16: description: event generation register byte_offset: 20 access: Write + bit_size: 16 fieldset: EGR_GP16 - name: CCMR_Input description: capture/compare mode register 1-2 (input mode) diff --git a/data/registers/timer_v1.yaml b/data/registers/timer_v1.yaml index e8cd3a3..ba0cea9 100644 --- a/data/registers/timer_v1.yaml +++ b/data/registers/timer_v1.yaml @@ -5,6 +5,7 @@ block/TIM_1CH: - name: CR1 description: control register 1 byte_offset: 0 + bit_size: 16 fieldset: CR1_1CH - name: DIER description: DMA/Interrupt enable register @@ -18,6 +19,7 @@ block/TIM_1CH: description: event generation register byte_offset: 20 access: Write + bit_size: 16 fieldset: EGR_1CH - name: CCMR_Input description: capture/compare mode register 1 (input mode) @@ -73,6 +75,7 @@ block/TIM_1CH_CMP: description: event generation register byte_offset: 20 access: Write + bit_size: 16 fieldset: EGR_1CH_CMP - name: CCER description: capture/compare enable register @@ -81,6 +84,7 @@ block/TIM_1CH_CMP: - name: RCR description: repetition counter register byte_offset: 48 + bit_size: 16 fieldset: RCR_1CH_CMP - name: BDTR description: break and dead-time register @@ -122,6 +126,7 @@ block/TIM_2CH: description: event generation register byte_offset: 20 access: Write + bit_size: 16 fieldset: EGR_2CH - name: CCMR_Input description: capture/compare mode register 1 (input mode) @@ -176,6 +181,7 @@ block/TIM_2CH_CMP: description: event generation register byte_offset: 20 access: Write + bit_size: 16 fieldset: EGR_2CH_CMP - name: CCMR_Input description: capture/compare mode register 1 (input mode) @@ -225,6 +231,7 @@ block/TIM_ADV: - name: CR1 description: control register 1 byte_offset: 0 + bit_size: 16 fieldset: CR1_GP16 - name: CR2 description: control register 2 @@ -246,6 +253,7 @@ block/TIM_ADV: description: event generation register byte_offset: 20 access: Write + bit_size: 16 fieldset: EGR_ADV - name: CCMR_Input description: capture/compare mode register 1-2 (input mode) @@ -268,6 +276,7 @@ block/TIM_ADV: - name: RCR description: repetition counter register byte_offset: 48 + bit_size: 16 fieldset: RCR_ADV - name: CCR description: capture/compare register x (x=1-4) @@ -329,6 +338,7 @@ block/TIM_CORE: - name: CR1 description: control register 1 byte_offset: 0 + bit_size: 16 fieldset: CR1_CORE - name: DIER description: DMA/Interrupt enable register @@ -342,6 +352,7 @@ block/TIM_CORE: description: event generation register byte_offset: 20 access: Write + bit_size: 16 fieldset: EGR_CORE - name: CNT description: counter @@ -362,6 +373,7 @@ block/TIM_GP16: - name: CR1 description: control register 1 byte_offset: 0 + bit_size: 16 fieldset: CR1_GP16 - name: CR2 description: control register 2 @@ -383,6 +395,7 @@ block/TIM_GP16: description: event generation register byte_offset: 20 access: Write + bit_size: 16 fieldset: EGR_GP16 - name: CCMR_Input description: capture/compare mode register 1-2 (input mode) diff --git a/data/registers/timer_v2.yaml b/data/registers/timer_v2.yaml index b3cfab0..58bfed2 100644 --- a/data/registers/timer_v2.yaml +++ b/data/registers/timer_v2.yaml @@ -5,6 +5,7 @@ block/TIM_1CH: - name: CR1 description: control register 1 byte_offset: 0 + bit_size: 16 fieldset: CR1_1CH - name: DIER description: DMA/Interrupt enable register @@ -18,6 +19,7 @@ block/TIM_1CH: description: event generation register byte_offset: 20 access: Write + bit_size: 16 fieldset: EGR_1CH - name: CCMR_Input description: capture/compare mode register 1 (input mode) @@ -80,6 +82,7 @@ block/TIM_1CH_CMP: description: event generation register byte_offset: 20 access: Write + bit_size: 16 fieldset: EGR_1CH_CMP - name: CCER description: capture/compare enable register @@ -88,6 +91,7 @@ block/TIM_1CH_CMP: - name: RCR description: repetition counter register byte_offset: 48 + bit_size: 16 fieldset: RCR_1CH_CMP - name: BDTR description: break and dead-time register @@ -136,6 +140,7 @@ block/TIM_2CH: description: event generation register byte_offset: 20 access: Write + bit_size: 16 fieldset: EGR_2CH - name: CCMR_Input description: capture/compare mode register 1 (input mode) @@ -197,6 +202,7 @@ block/TIM_2CH_CMP: description: event generation register byte_offset: 20 access: Write + bit_size: 16 fieldset: EGR_2CH_CMP - name: CCMR_Input description: capture/compare mode register 1 (input mode) @@ -238,6 +244,7 @@ block/TIM_ADV: - name: CR1 description: control register 1 byte_offset: 0 + bit_size: 16 fieldset: CR1_GP16 - name: CR2 description: control register 2 @@ -259,6 +266,7 @@ block/TIM_ADV: description: event generation register byte_offset: 20 access: Write + bit_size: 16 fieldset: EGR_ADV - name: CCMR_Input description: capture/compare mode register 1-2 (input mode) @@ -281,6 +289,7 @@ block/TIM_ADV: - name: RCR description: repetition counter register byte_offset: 48 + bit_size: 16 fieldset: RCR_ADV - name: CCR description: capture/compare register x (x=1-4) @@ -347,6 +356,7 @@ block/TIM_CORE: - name: CR1 description: control register 1 byte_offset: 0 + bit_size: 16 fieldset: CR1_CORE - name: DIER description: DMA/Interrupt enable register @@ -360,6 +370,7 @@ block/TIM_CORE: description: event generation register byte_offset: 20 access: Write + bit_size: 16 fieldset: EGR_CORE - name: CNT description: counter @@ -384,6 +395,7 @@ block/TIM_GP16: - name: CR1 description: control register 1 byte_offset: 0 + bit_size: 16 fieldset: CR1_GP16 - name: CR2 description: control register 2 @@ -405,6 +417,7 @@ block/TIM_GP16: description: event generation register byte_offset: 20 access: Write + bit_size: 16 fieldset: EGR_GP16 - name: CCMR_Input description: capture/compare mode register 1-2 (input mode)