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merge input mode and output mode

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eZio Pan 2024-04-05 12:36:35 +08:00
parent d9625637f2
commit f789074a4b
1 changed files with 71 additions and 219 deletions
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data/registers/lptim_v2b.yaml
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@ -1,27 +1,19 @@
block/IC:
items:
- name: ISR
description: LPTIM interrupt and status register.
byte_offset: 0
fieldset: ISR_IC
- name: ICR
description: LPTIM interrupt clear register.
byte_offset: 4
fieldset: ICR_IC
- name: DIER
description: LPTIM interrupt enable register.
byte_offset: 8
fieldset: DIER_IC
block/LPTIM_ADV: block/LPTIM_ADV:
extends: LPTIM_BASIC extends: LPTIM_BASIC
description: Low power timer with Output Compare description: Low power timer with Output Compare
items: items:
- name: InputCapture - name: ISR
description: LPTIM interrupt and status register.
byte_offset: 0 byte_offset: 0
block: IC fieldset: ISR_ADV
- name: OutputCompare - name: ICR
byte_offset: 0 description: LPTIM interrupt clear register.
block: OC_ADV byte_offset: 4
fieldset: ICR_ADV
- name: DIER
description: LPTIM interrupt enable register.
byte_offset: 8
fieldset: DIER_ADV
- name: CCR - name: CCR
description: LPTIM compare register 1. description: LPTIM compare register 1.
array: array:
@ -83,20 +75,6 @@ block/LPTIM_BASIC:
description: LPTIM repetition register. description: LPTIM repetition register.
byte_offset: 40 byte_offset: 40
fieldset: RCR fieldset: RCR
block/OC_ADV:
items:
- name: ISR
description: LPTIM interrupt and status register.
byte_offset: 0
fieldset: ISR_OC_ADV
- name: ICR
description: LPTIM interrupt clear register.
byte_offset: 4
fieldset: ICR_OC_ADV
- name: DIER
description: LPTIM interrupt enable register.
byte_offset: 8
fieldset: DIER_OC_ADV
fieldset/ARR: fieldset/ARR:
description: LPTIM autoreload register. description: LPTIM autoreload register.
fields: fields:
@ -277,6 +255,38 @@ fieldset/CR:
description: Reset after read enable This bit is set and cleared by software. When RSTARE is set to '1', any read access to LPTIM_CNT register asynchronously resets LPTIM_CNT register content. This bit can be set only when the LPTIM is enabled. description: Reset after read enable This bit is set and cleared by software. When RSTARE is set to '1', any read access to LPTIM_CNT register asynchronously resets LPTIM_CNT register content. This bit can be set only when the LPTIM is enabled.
bit_offset: 4 bit_offset: 4
bit_size: 1 bit_size: 1
fieldset/DIER_ADV:
extends: DIER_BASIC
description: LPTIM interrupt enable register.
fields:
- name: CCIE
description: Capture/compare 1 interrupt enable.
bit_offset: 0
bit_size: 1
array:
len: 2
stride: 9
- name: CMPOKIE
description: Compare register 1 update OK interrupt enable.
bit_offset: 3
bit_size: 1
array:
len: 2
stride: 16
- name: CCOIE
description: 'Capture/compare 1 over-capture interrupt enable Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to.'
bit_offset: 12
bit_size: 1
array:
len: 2
stride: 1
- name: CCDE
description: 'Capture/compare 1 DMA request enable Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to.'
bit_offset: 16
bit_size: 1
array:
len: 2
stride: 9
fieldset/DIER_BASIC: fieldset/DIER_BASIC:
description: LPTIM interrupt enable register. description: LPTIM interrupt enable register.
fields: fields:
@ -322,80 +332,31 @@ fieldset/DIER_BASIC:
description: Repetition register update OK interrupt Enable. description: Repetition register update OK interrupt Enable.
bit_offset: 8 bit_offset: 8
bit_size: 1 bit_size: 1
fieldset/DIER_IC: fieldset/ICR_ADV:
description: LPTIM interrupt enable register. extends: ICR_BASIC
description: LPTIM interrupt clear register.
fields: fields:
- name: CCIE - name: CCCF
description: Capture/compare 1 interrupt enable. description: Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register.
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
array: array:
len: 2 len: 2
stride: 9 stride: 9
- name: ARRMIE - name: CMPOKCF
description: Autoreload match Interrupt Enable. description: Compare register 1 update OK clear flag Writing 1 to this bit clears the CMP1OK flag in the LPTIM_ISR register.
bit_offset: 1
bit_size: 1
- name: EXTTRIGIE
description: External trigger valid edge Interrupt Enable.
bit_offset: 2
bit_size: 1
- name: ARROKIE
description: Autoreload register update OK Interrupt Enable.
bit_offset: 4
bit_size: 1
- name: UPIE
description: 'Direction change to UP Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.'
bit_offset: 5
bit_size: 1
- name: DOWNIE
description: 'Direction change to down Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.'
bit_offset: 6
bit_size: 1
- name: UEIE
description: Update event interrupt enable.
bit_offset: 7
bit_size: 1
- name: REPOKIE
description: Repetition register update OK interrupt Enable.
bit_offset: 8
bit_size: 1
- name: CCOIE
description: 'Capture/compare 1 over-capture interrupt enable Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to.'
bit_offset: 12
bit_size: 1
array:
len: 2
stride: 1
- name: CCDE
description: 'Capture/compare 1 DMA request enable Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to.'
bit_offset: 16
bit_size: 1
array:
len: 2
stride: 9
- name: UEDE
description: 'Update event DMA request enable Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to.'
bit_offset: 23
bit_size: 1
fieldset/DIER_OC_ADV:
extends: DIER_BASIC
description: LPTIM interrupt enable register.
fields:
- name: CCIE
description: Capture/compare 1 interrupt enable.
bit_offset: 0
bit_size: 1
array:
len: 2
stride: 9
- name: CMPOKIE
description: Compare register 1 update OK interrupt enable.
bit_offset: 3 bit_offset: 3
bit_size: 1 bit_size: 1
array: array:
len: 2 len: 2
stride: 16 stride: 16
- name: CCOCF
description: 'Capture/compare 1 over-capture clear flag Writing 1 to this bit clears the CC1OF flag in the LPTIM_ISR register. Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to.'
bit_offset: 12
bit_size: 1
array:
len: 2
stride: 1
fieldset/ICR_BASIC: fieldset/ICR_BASIC:
description: LPTIM interrupt clear register. description: LPTIM interrupt clear register.
fields: fields:
@ -445,73 +406,31 @@ fieldset/ICR_BASIC:
description: Interrupt enable register update OK clear flag Writing 1 to this bit clears the DIEROK flag in the LPTIM_ISR register. description: Interrupt enable register update OK clear flag Writing 1 to this bit clears the DIEROK flag in the LPTIM_ISR register.
bit_offset: 24 bit_offset: 24
bit_size: 1 bit_size: 1
fieldset/ICR_IC: fieldset/ISR_ADV:
description: LPTIM interrupt clear register. extends: ISR_BASIC
description: LPTIM interrupt and status register.
fields: fields:
- name: CCCF - name: CCIF
description: Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register. description: Compare 1 interrupt flag The CC1IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. The CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register.
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
array: array:
len: 2 len: 2
stride: 9 stride: 9
- name: ARRMCF - name: CMPOK
description: Autoreload match clear flag Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register. description: Compare register 1 update OK CMP1OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR1 register has been successfully completed. CMP1OK flag can be cleared by writing 1 to the CMP1OKCF bit in the LPTIM_ICR register.
bit_offset: 1
bit_size: 1
- name: EXTTRIGCF
description: External trigger valid edge clear flag Writing 1 to this bit clears the EXTTRIG flag in the LPTIM_ISR register.
bit_offset: 2
bit_size: 1
- name: ARROKCF
description: Autoreload register update OK clear flag Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register.
bit_offset: 4
bit_size: 1
- name: UPCF
description: 'Direction change to UP clear flag Writing 1 to this bit clear the UP flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.'
bit_offset: 5
bit_size: 1
- name: DOWNCF
description: 'Direction change to down clear flag Writing 1 to this bit clear the DOWN flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.'
bit_offset: 6
bit_size: 1
- name: UECF
description: Update event clear flag Writing 1 to this bit clear the UE flag in the LPTIM_ISR register.
bit_offset: 7
bit_size: 1
- name: REPOKCF
description: Repetition register update OK clear flag Writing 1 to this bit clears the REPOK flag in the LPTIM_ISR register.
bit_offset: 8
bit_size: 1
- name: CCOCF
description: 'Capture/compare 1 over-capture clear flag Writing 1 to this bit clears the CC1OF flag in the LPTIM_ISR register. Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to.'
bit_offset: 12
bit_size: 1
array:
len: 2
stride: 1
- name: DIEROKCF
description: Interrupt enable register update OK clear flag Writing 1 to this bit clears the DIEROK flag in the LPTIM_ISR register.
bit_offset: 24
bit_size: 1
fieldset/ICR_OC_ADV:
extends: ICR_BASIC
description: LPTIM interrupt clear register.
fields:
- name: CCCF
description: Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register.
bit_offset: 0
bit_size: 1
array:
len: 2
stride: 9
- name: CMPOKCF
description: Compare register 1 update OK clear flag Writing 1 to this bit clears the CMP1OK flag in the LPTIM_ISR register.
bit_offset: 3 bit_offset: 3
bit_size: 1 bit_size: 1
array: array:
len: 2 len: 2
stride: 16 stride: 16
- name: CCOF
description: 'Capture 1 over-capture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing 1 to the CC1OCF bit in the LPTIM_ICR register. Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to.'
bit_offset: 12
bit_size: 1
array:
len: 2
stride: 1
fieldset/ISR_BASIC: fieldset/ISR_BASIC:
description: LPTIM interrupt and status register. description: LPTIM interrupt and status register.
fields: fields:
@ -561,73 +480,6 @@ fieldset/ISR_BASIC:
description: Interrupt enable register update OK DIEROK is set by hardware to inform application that the APB bus write operation to the LPTIM_DIER register has been successfully completed. DIEROK flag can be cleared by writing 1 to the DIEROKCF bit in the LPTIM_ICR register. description: Interrupt enable register update OK DIEROK is set by hardware to inform application that the APB bus write operation to the LPTIM_DIER register has been successfully completed. DIEROK flag can be cleared by writing 1 to the DIEROKCF bit in the LPTIM_ICR register.
bit_offset: 24 bit_offset: 24
bit_size: 1 bit_size: 1
fieldset/ISR_IC:
description: LPTIM interrupt and status register.
fields:
- name: CCIF
description: 'capture 1 interrupt flag If channel CC1 is configured as input: CC1IF is set by hardware to inform application that the current value of the counter is captured in LPTIM_CCR1 register. The corresponding interrupt or DMA request is generated if enabled. The CC1OF flag is set if the CC1IF flag was already high.'
bit_offset: 0
bit_size: 1
array:
len: 2
stride: 9
- name: ARRM
description: Autoreload match ARRM is set by hardware to inform application that LPTIM_CNT register’s value reached the LPTIM_ARR register’s value. ARRM flag can be cleared by writing 1 to the ARRMCF bit in the LPTIM_ICR register.
bit_offset: 1
bit_size: 1
- name: EXTTRIG
description: External trigger edge event EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. EXTTRIG flag can be cleared by writing 1 to the EXTTRIGCF bit in the LPTIM_ICR register.
bit_offset: 2
bit_size: 1
- name: ARROK
description: Autoreload register update OK ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR register has been successfully completed. ARROK flag can be cleared by writing 1 to the ARROKCF bit in the LPTIM_ICR register.
bit_offset: 4
bit_size: 1
- name: UP
description: 'Counter direction change down to up In Encoder mode, UP bit is set by hardware to inform application that the counter direction has changed from down to up. UP flag can be cleared by writing 1 to the UPCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.'
bit_offset: 5
bit_size: 1
- name: DOWN
description: 'Counter direction change up to down In Encoder mode, DOWN bit is set by hardware to inform application that the counter direction has changed from up to down. DOWN flag can be cleared by writing 1 to the DOWNCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.'
bit_offset: 6
bit_size: 1
- name: UE
description: LPTIM update event occurred UE is set by hardware to inform application that an update event was generated. UE flag can be cleared by writing 1 to the UECF bit in the LPTIM_ICR register.
bit_offset: 7
bit_size: 1
- name: REPOK
description: Repetition register update OK REPOK is set by hardware to inform application that the APB bus write operation to the LPTIM_RCR register has been successfully completed. REPOK flag can be cleared by writing 1 to the REPOKCF bit in the LPTIM_ICR register.
bit_offset: 8
bit_size: 1
- name: CCOF
description: 'Capture 1 over-capture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing 1 to the CC1OCF bit in the LPTIM_ICR register. Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to.'
bit_offset: 12
bit_size: 1
array:
len: 2
stride: 1
- name: DIEROK
description: Interrupt enable register update OK DIEROK is set by hardware to inform application that the APB bus write operation to the LPTIM_DIER register has been successfully completed. DIEROK flag can be cleared by writing 1 to the DIEROKCF bit in the LPTIM_ICR register.
bit_offset: 24
bit_size: 1
fieldset/ISR_OC_ADV:
extends: ISR_BASIC
description: LPTIM interrupt and status register.
fields:
- name: CCIF
description: Compare 1 interrupt flag The CC1IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. The CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register.
bit_offset: 0
bit_size: 1
array:
len: 2
stride: 9
- name: CMPOK
description: Compare register 1 update OK CMP1OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR1 register has been successfully completed. CMP1OK flag can be cleared by writing 1 to the CMP1OKCF bit in the LPTIM_ICR register.
bit_offset: 3
bit_size: 1
array:
len: 2
stride: 16
fieldset/RCR: fieldset/RCR:
description: LPTIM repetition register. description: LPTIM repetition register.
fields: fields: