From f6cc2cd4590baae6865a699cd14d601b9832b24e Mon Sep 17 00:00:00 2001 From: Rasmus Melchior Jacobsen Date: Tue, 7 Feb 2023 14:05:17 +0100 Subject: [PATCH] Rename versions to make room for a new v1. --- .../{fsmc_v0x1.yaml => fsmc_v1x0.yaml} | 0 data/registers/fsmc_v1x3.yaml | 113 ++++++----------- .../{fsmc_v0x3.yaml => fsmc_v2x3.yaml} | 119 ++++++++++++------ data/registers/fsmc_v3x1.yaml | 50 +------- data/registers/fsmc_v4x1.yaml | 3 +- .../{fsmc_v2x1.yaml => fsmc_v5x1.yaml} | 49 +++++++- src/chips.rs | 28 ++--- 7 files changed, 181 insertions(+), 181 deletions(-) rename data/registers/{fsmc_v0x1.yaml => fsmc_v1x0.yaml} (100%) rename data/registers/{fsmc_v0x3.yaml => fsmc_v2x3.yaml} (83%) rename data/registers/{fsmc_v2x1.yaml => fsmc_v5x1.yaml} (90%) diff --git a/data/registers/fsmc_v0x1.yaml b/data/registers/fsmc_v1x0.yaml similarity index 100% rename from data/registers/fsmc_v0x1.yaml rename to data/registers/fsmc_v1x0.yaml diff --git a/data/registers/fsmc_v1x3.yaml b/data/registers/fsmc_v1x3.yaml index 6ef193c..ba7f8b7 100644 --- a/data/registers/fsmc_v1x3.yaml +++ b/data/registers/fsmc_v1x3.yaml @@ -1,18 +1,19 @@ -# stm32f3 +# stm32f101 +# stm32f102 +# stm32f103 +# stm32f105 +# stm32f107 +# stm32f2 --- block/FSMC: description: Flexible static memory controller items: - - name: BCR1 - description: SRAM/NOR-Flash chip-select control register 1 - byte_offset: 0 - fieldset: BCR1 - name: BCR - description: SRAM/NOR-Flash chip-select control register 2-4 + description: SRAM/NOR-Flash chip-select control register 1-4 array: - len: 3 + len: 4 stride: 8 - byte_offset: 8 + byte_offset: 0 fieldset: BCR - name: BTR description: SRAM/NOR-Flash chip-select timing register 1-4 @@ -68,75 +69,8 @@ block/FSMC: byte_offset: 116 access: Read fieldset: ECCR -fieldset/BCR1: - description: SRAM/NOR-Flash chip-select control register 1 - fields: - - name: MBKEN - description: Memory bank enable bit - bit_offset: 0 - bit_size: 1 - - name: MUXEN - description: Address/data multiplexing enable bit - bit_offset: 1 - bit_size: 1 - - name: MTYP - description: Memory type - bit_offset: 2 - bit_size: 2 - enum: MTYP - - name: MWID - description: Memory data bus width - bit_offset: 4 - bit_size: 2 - enum: MWID - - name: FACCEN - description: Flash access enable - bit_offset: 6 - bit_size: 1 - - name: BURSTEN - description: Burst enable bit - bit_offset: 8 - bit_size: 1 - - name: WAITPOL - description: Wait signal polarity bit - bit_offset: 9 - bit_size: 1 - enum: WAITPOL - - name: WRAPMOD - description: WRAPMOD - bit_offset: 10 - bit_size: 1 - - name: WAITCFG - description: Wait timing configuration - bit_offset: 11 - bit_size: 1 - enum: WAITCFG - - name: WREN - description: Write enable bit - bit_offset: 12 - bit_size: 1 - - name: WAITEN - description: Wait enable bit - bit_offset: 13 - bit_size: 1 - - name: EXTMOD - description: Extended mode enable - bit_offset: 14 - bit_size: 1 - - name: ASYNCWAIT - description: Wait signal during asynchronous transfers - bit_offset: 15 - bit_size: 1 - - name: CBURSTRW - description: Write burst enable - bit_offset: 19 - bit_size: 1 - - name: CCLKEN - description: Continuous clock enable - bit_offset: 20 - bit_size: 1 fieldset/BCR: - description: SRAM/NOR-Flash chip-select control register 2-4 + description: SRAM/NOR-Flash chip-select control register fields: - name: MBKEN description: Memory bank enable bit @@ -194,6 +128,11 @@ fieldset/BCR: description: Wait signal during asynchronous transfers bit_offset: 15 bit_size: 1 + - name: CPSIZE + description: CRAM page size + bit_offset: 16 + bit_size: 3 + enum: CPSIZE - name: CBURSTRW description: Write burst enable bit_offset: 19 @@ -245,6 +184,10 @@ fieldset/BWTR: description: Data-phase duration bit_offset: 8 bit_size: 8 + - name: BUSTURN + description: Bus turnaround phase duration + bit_offset: 16 + bit_size: 4 - name: ACCMOD description: Access mode bit_offset: 28 @@ -398,6 +341,24 @@ enum/ACCMOD: - name: D description: Access mode D value: 3 +enum/CPSIZE: + bit_size: 3 + variants: + - name: NoBurstSplit + description: No burst split when crossing page boundary + value: 0 + - name: Bytes128 + description: 128 bytes CRAM page size + value: 1 + - name: Bytes256 + description: 256 bytes CRAM page size + value: 2 + - name: Bytes512 + description: 512 bytes CRAM page size + value: 3 + - name: Bytes1024 + description: 1024 bytes CRAM page size + value: 4 enum/ECCPS: bit_size: 3 variants: diff --git a/data/registers/fsmc_v0x3.yaml b/data/registers/fsmc_v2x3.yaml similarity index 83% rename from data/registers/fsmc_v0x3.yaml rename to data/registers/fsmc_v2x3.yaml index ba7f8b7..6ef193c 100644 --- a/data/registers/fsmc_v0x3.yaml +++ b/data/registers/fsmc_v2x3.yaml @@ -1,19 +1,18 @@ -# stm32f101 -# stm32f102 -# stm32f103 -# stm32f105 -# stm32f107 -# stm32f2 +# stm32f3 --- block/FSMC: description: Flexible static memory controller items: - - name: BCR - description: SRAM/NOR-Flash chip-select control register 1-4 - array: - len: 4 - stride: 8 + - name: BCR1 + description: SRAM/NOR-Flash chip-select control register 1 byte_offset: 0 + fieldset: BCR1 + - name: BCR + description: SRAM/NOR-Flash chip-select control register 2-4 + array: + len: 3 + stride: 8 + byte_offset: 8 fieldset: BCR - name: BTR description: SRAM/NOR-Flash chip-select timing register 1-4 @@ -69,8 +68,75 @@ block/FSMC: byte_offset: 116 access: Read fieldset: ECCR -fieldset/BCR: - description: SRAM/NOR-Flash chip-select control register +fieldset/BCR1: + description: SRAM/NOR-Flash chip-select control register 1 + fields: + - name: MBKEN + description: Memory bank enable bit + bit_offset: 0 + bit_size: 1 + - name: MUXEN + description: Address/data multiplexing enable bit + bit_offset: 1 + bit_size: 1 + - name: MTYP + description: Memory type + bit_offset: 2 + bit_size: 2 + enum: MTYP + - name: MWID + description: Memory data bus width + bit_offset: 4 + bit_size: 2 + enum: MWID + - name: FACCEN + description: Flash access enable + bit_offset: 6 + bit_size: 1 + - name: BURSTEN + description: Burst enable bit + bit_offset: 8 + bit_size: 1 + - name: WAITPOL + description: Wait signal polarity bit + bit_offset: 9 + bit_size: 1 + enum: WAITPOL + - name: WRAPMOD + description: WRAPMOD + bit_offset: 10 + bit_size: 1 + - name: WAITCFG + description: Wait timing configuration + bit_offset: 11 + bit_size: 1 + enum: WAITCFG + - name: WREN + description: Write enable bit + bit_offset: 12 + bit_size: 1 + - name: WAITEN + description: Wait enable bit + bit_offset: 13 + bit_size: 1 + - name: EXTMOD + description: Extended mode enable + bit_offset: 14 + bit_size: 1 + - name: ASYNCWAIT + description: Wait signal during asynchronous transfers + bit_offset: 15 + bit_size: 1 + - name: CBURSTRW + description: Write burst enable + bit_offset: 19 + bit_size: 1 + - name: CCLKEN + description: Continuous clock enable + bit_offset: 20 + bit_size: 1 +fieldset/BCR: + description: SRAM/NOR-Flash chip-select control register 2-4 fields: - name: MBKEN description: Memory bank enable bit @@ -128,11 +194,6 @@ fieldset/BCR: description: Wait signal during asynchronous transfers bit_offset: 15 bit_size: 1 - - name: CPSIZE - description: CRAM page size - bit_offset: 16 - bit_size: 3 - enum: CPSIZE - name: CBURSTRW description: Write burst enable bit_offset: 19 @@ -184,10 +245,6 @@ fieldset/BWTR: description: Data-phase duration bit_offset: 8 bit_size: 8 - - name: BUSTURN - description: Bus turnaround phase duration - bit_offset: 16 - bit_size: 4 - name: ACCMOD description: Access mode bit_offset: 28 @@ -341,24 +398,6 @@ enum/ACCMOD: - name: D description: Access mode D value: 3 -enum/CPSIZE: - bit_size: 3 - variants: - - name: NoBurstSplit - description: No burst split when crossing page boundary - value: 0 - - name: Bytes128 - description: 128 bytes CRAM page size - value: 1 - - name: Bytes256 - description: 256 bytes CRAM page size - value: 2 - - name: Bytes512 - description: 512 bytes CRAM page size - value: 3 - - name: Bytes1024 - description: 1024 bytes CRAM page size - value: 4 enum/ECCPS: bit_size: 3 variants: diff --git a/data/registers/fsmc_v3x1.yaml b/data/registers/fsmc_v3x1.yaml index cd2ce33..ebb7ecd 100644 --- a/data/registers/fsmc_v3x1.yaml +++ b/data/registers/fsmc_v3x1.yaml @@ -1,5 +1,4 @@ -# stm32l5 -# stm32g4 +# stm32l4 --- block/FSMC: description: Flexible static memory controller @@ -22,10 +21,6 @@ block/FSMC: stride: 8 byte_offset: 4 fieldset: BTR - - name: PCSCNTR - description: PSRAM chip select counter register - byte_offset: 32 - fieldset: PCSCNTR - name: BWTR description: SRAM/NOR-Flash write timing registers 1-4 array: @@ -126,14 +121,6 @@ fieldset/BCR1: description: Write FIFO disable bit_offset: 21 bit_size: 1 - - name: NBLSET - description: Byte lane (NBL) setup - bit_offset: 22 - bit_size: 2 - - name: FMCEN - description: FMC controller enable - bit_offset: 31 - bit_size: 1 fieldset/BCR: description: SRAM/NOR-Flash chip-select control register 2-4 fields: @@ -198,10 +185,6 @@ fieldset/BCR: description: Write burst enable bit_offset: 19 bit_size: 1 - - name: NBLSET - description: Byte lane (NBL) setup - bit_offset: 22 - bit_size: 2 fieldset/BTR: description: SRAM/NOR-Flash chip-select timing register fields: @@ -234,33 +217,6 @@ fieldset/BTR: bit_offset: 28 bit_size: 2 enum: ACCMOD - - name: DATAHLD - description: Data hold phase duration - bit_offset: 30 - bit_size: 2 -fieldset/PCSCNTR: - description: PSRAM chip select counter register - fields: - - name: CSCOUNT - description: Chip select counter - bit_offset: 0 - bit_size: 16 - - name: CNTB1EN - description: Counter Bank 1 enable - bit_offset: 16 - bit_size: 1 - - name: CNTB2EN - description: Counter Bank 2 enable - bit_offset: 17 - bit_size: 1 - - name: CNTB3EN - description: Counter Bank 3 enable - bit_offset: 18 - bit_size: 1 - - name: CNTB4EN - description: Counter Bank 4 enable - bit_offset: 19 - bit_size: 1 fieldset/BWTR: description: SRAM/NOR-Flash write timing registers fields: @@ -285,10 +241,6 @@ fieldset/BWTR: bit_offset: 28 bit_size: 2 enum: ACCMOD - - name: DATAHLD - description: Data hold phase duration - bit_offset: 30 - bit_size: 2 fieldset/PCR: description: PC Card/NAND Flash control register fields: diff --git a/data/registers/fsmc_v4x1.yaml b/data/registers/fsmc_v4x1.yaml index 371ca46..cd2ce33 100644 --- a/data/registers/fsmc_v4x1.yaml +++ b/data/registers/fsmc_v4x1.yaml @@ -1,4 +1,5 @@ -# stm32u5 +# stm32l5 +# stm32g4 --- block/FSMC: description: Flexible static memory controller diff --git a/data/registers/fsmc_v2x1.yaml b/data/registers/fsmc_v5x1.yaml similarity index 90% rename from data/registers/fsmc_v2x1.yaml rename to data/registers/fsmc_v5x1.yaml index ebb7ecd..371ca46 100644 --- a/data/registers/fsmc_v2x1.yaml +++ b/data/registers/fsmc_v5x1.yaml @@ -1,4 +1,4 @@ -# stm32l4 +# stm32u5 --- block/FSMC: description: Flexible static memory controller @@ -21,6 +21,10 @@ block/FSMC: stride: 8 byte_offset: 4 fieldset: BTR + - name: PCSCNTR + description: PSRAM chip select counter register + byte_offset: 32 + fieldset: PCSCNTR - name: BWTR description: SRAM/NOR-Flash write timing registers 1-4 array: @@ -121,6 +125,14 @@ fieldset/BCR1: description: Write FIFO disable bit_offset: 21 bit_size: 1 + - name: NBLSET + description: Byte lane (NBL) setup + bit_offset: 22 + bit_size: 2 + - name: FMCEN + description: FMC controller enable + bit_offset: 31 + bit_size: 1 fieldset/BCR: description: SRAM/NOR-Flash chip-select control register 2-4 fields: @@ -185,6 +197,10 @@ fieldset/BCR: description: Write burst enable bit_offset: 19 bit_size: 1 + - name: NBLSET + description: Byte lane (NBL) setup + bit_offset: 22 + bit_size: 2 fieldset/BTR: description: SRAM/NOR-Flash chip-select timing register fields: @@ -217,6 +233,33 @@ fieldset/BTR: bit_offset: 28 bit_size: 2 enum: ACCMOD + - name: DATAHLD + description: Data hold phase duration + bit_offset: 30 + bit_size: 2 +fieldset/PCSCNTR: + description: PSRAM chip select counter register + fields: + - name: CSCOUNT + description: Chip select counter + bit_offset: 0 + bit_size: 16 + - name: CNTB1EN + description: Counter Bank 1 enable + bit_offset: 16 + bit_size: 1 + - name: CNTB2EN + description: Counter Bank 2 enable + bit_offset: 17 + bit_size: 1 + - name: CNTB3EN + description: Counter Bank 3 enable + bit_offset: 18 + bit_size: 1 + - name: CNTB4EN + description: Counter Bank 4 enable + bit_offset: 19 + bit_size: 1 fieldset/BWTR: description: SRAM/NOR-Flash write timing registers fields: @@ -241,6 +284,10 @@ fieldset/BWTR: bit_offset: 28 bit_size: 2 enum: ACCMOD + - name: DATAHLD + description: Data hold phase duration + bit_offset: 30 + bit_size: 2 fieldset/PCR: description: PC Card/NAND Flash control register fields: diff --git a/src/chips.rs b/src/chips.rs index 20d99ce..21e313d 100644 --- a/src/chips.rs +++ b/src/chips.rs @@ -294,20 +294,20 @@ impl PeriMatcher { ("STM32F[24].*:ETH:.*", ("eth", "v1b", "ETH")), ("STM32F7.*:ETH:.*", ("eth", "v1c", "ETH")), (".*ETH:ethermac110_v3_0", ("eth", "v2", "ETH")), - ("STM32F4[0123].*:FMC:.*", ("fmc", "v1x3", "FMC")), - ("STM32F446.*:FMC:.*", ("fmc", "v2x1", "FMC")), - ("STM32F469.*:FMC:.*", ("fmc", "v2x1", "FMC")), - ("STM32F7.*:FMC:.*", ("fmc", "v2x1", "FMC")), - ("STM32H7.*:FMC:.*", ("fmc", "v3x1", "FMC")), - ("STM32F100.*:FSMC:.*", ("fsmc", "v0x1", "FSMC")), - ("STM32F10[12357].*:FSMC:.*", ("fsmc", "v0x3", "FSMC")), - ("STM32F2.*:FSMC:.*", ("fsmc", "v0x3", "FSMC")), - ("STM32F3.*:FSMC:.*", ("fsmc", "v1x3", "FSMC")), - ("STM32L1.*:FSMC:.*", ("fsmc", "v0x1", "FSMC")), - ("STM32L4.*:FSMC:.*", ("fsmc", "v2x1", "FSMC")), - ("STM32G4.*:FSMC:.*", ("fsmc", "v3x1", "FSMC")), - ("STM32L5.*:FSMC:.*", ("fsmc", "v3x1", "FSMC")), - ("STM32U5.*:FSMC:.*", ("fsmc", "v4x1", "FSMC")), + ("STM32F4[0123].*:FMC:.*", ("fmc", "v2x3", "FMC")), + ("STM32F446.*:FMC:.*", ("fmc", "v3x1", "FMC")), + ("STM32F469.*:FMC:.*", ("fmc", "v3x1", "FMC")), + ("STM32F7.*:FMC:.*", ("fmc", "v3x1", "FMC")), + ("STM32H7.*:FMC:.*", ("fmc", "v4x1", "FMC")), + ("STM32F100.*:FSMC:.*", ("fsmc", "v1x0", "FSMC")), + ("STM32F10[12357].*:FSMC:.*", ("fsmc", "v1x3", "FSMC")), + ("STM32F2.*:FSMC:.*", ("fsmc", "v1x3", "FSMC")), + ("STM32F3.*:FSMC:.*", ("fsmc", "v2x3", "FSMC")), + ("STM32L1.*:FSMC:.*", ("fsmc", "v1x1", "FSMC")), + ("STM32L4.*:FSMC:.*", ("fsmc", "v3x1", "FSMC")), + ("STM32G4.*:FSMC:.*", ("fsmc", "v4x1", "FSMC")), + ("STM32L5.*:FSMC:.*", ("fsmc", "v4x1", "FSMC")), + ("STM32U5.*:FSMC:.*", ("fsmc", "v5x1", "FSMC")), (".*:FSMC:.*", ("fsmc", "v1", "FSMC")), (r".*LPTIM\d.*:G0xx_lptimer1_v1_4", ("lptim", "g0", "LPTIM")), ("STM32F1.*:TIM(1|8):.*", ("timer", "v1", "TIM_ADV")),