Add STM32G0 support
Includes manually specified register layouts for EXTI and SYSCFG.
This commit is contained in:
Ben Gamari
Dario Nieuwenhuis
parent
075d283354
commit
f57a268b9f
196
data/registers/exti_g0.yaml
Normal file
196
data/registers/exti_g0.yaml
Normal file
@ -0,0 +1,196 @@
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---
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block/EXTI:
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description: External interrupt/event controller
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items:
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- name: RTSR
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description: Rising Trigger selection register (EXTI_RTSR)
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byte_offset: 0
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reset_value: 0
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fieldset: RTSR
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array:
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len: 2
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stride: 40
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- name: FTSR
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description: Falling Trigger selection register (EXTI_FTSR)
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byte_offset: 4
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reset_value: 0
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fieldset: FTSR
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array:
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len: 2
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stride: 40
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- name: SWIER
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description: Software interrupt event register (EXTI_SWIER)
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byte_offset: 8
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reset_value: 0
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fieldset: SWIER
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array:
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len: 2
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stride: 40
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- name: RPR
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description: Rising pending register (EXTI_RPR)
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byte_offset: 12
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reset_value: 0
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fieldset: RPR
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array:
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len: 2
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stride: 40
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- name: FPR
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description: Falling pending register (EXTI_FPR)
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byte_offset: 16
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reset_value: 0
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fieldset: FPR
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array:
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len: 2
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stride: 40
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- name: EXTICR
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description: external interrupt configuration register
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array:
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len: 4
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stride: 4
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byte_offset: 96
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fieldset: EXTICR
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- name: IMR
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description: internal interrupt configuration register 1
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array:
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len: 2
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stride: 16
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byte_offset: 128
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fieldset: IMR
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- name: EMR
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description: external interrupt configuration register 1
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array:
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len: 2
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stride: 16
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byte_offset: 132
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fieldset: EMR
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fieldset/EMR:
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description: Event mask register (EXTI_EMR)
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fields:
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- name: MR
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description: Event Mask on line 0
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bit_offset: 0
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bit_size: 1
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array:
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len: 32
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stride: 1
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enum: MR
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fieldset/FPR:
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description: Falling Trigger pending register (EXTI_FPR)
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fields:
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- name: FPIF
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description: Falling edge event pending for line 0
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bit_offset: 0
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bit_size: 1
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array:
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len: 32
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stride: 1
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enum: PRR
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fieldset/FTSR:
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description: Falling Trigger selection register (EXTI_FTSR)
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fields:
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- name: TR
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description: Falling trigger event configuration of line 0
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bit_offset: 0
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bit_size: 1
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array:
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len: 32
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stride: 1
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enum: TR
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fieldset/IMR:
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description: Interrupt mask register (EXTI_IMR)
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fields:
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- name: MR
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description: Interrupt Mask on line 0
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bit_offset: 0
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bit_size: 1
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array:
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len: 32
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stride: 1
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enum: MR
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fieldset/RPR:
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description: Rising Trigger pending register (EXTI_RPR)
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fields:
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- name: RPIF
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description: Rising edge event pending for line 0
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bit_offset: 0
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bit_size: 1
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array:
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len: 32
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stride: 1
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enum: PRR
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fieldset/RTSR:
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description: Rising Trigger selection register (EXTI_RTSR)
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fields:
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- name: TR
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description: Rising trigger event configuration of line 0
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bit_offset: 0
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bit_size: 1
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array:
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len: 32
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stride: 1
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enum: TR
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fieldset/SWIER:
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description: Software interrupt event register (EXTI_SWIER)
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fields:
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- name: SWIER
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description: Software Interrupt on line 0
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bit_offset: 0
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bit_size: 1
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array:
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len: 32
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stride: 1
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enum_write: SWIERW
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fieldset/EXTICR:
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description: external interrupt configuration register 1
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fields:
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- name: EXTI
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description: EXTI configuration bits
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bit_offset: 0
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bit_size: 4
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array:
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len: 4
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stride: 4
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enum/MR:
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bit_size: 1
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variants:
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- name: Masked
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description: Interrupt request line is masked
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value: 0
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- name: Unmasked
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description: Interrupt request line is unmasked
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value: 1
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enum/TR:
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bit_size: 1
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variants:
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- name: Disabled
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description: Falling edge trigger is disabled
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value: 0
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- name: Enabled
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description: Falling edge trigger is enabled
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value: 1
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enum/PRR:
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bit_size: 1
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variants:
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- name: NotPending
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description: No trigger request occurred
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value: 0
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- name: Pending
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description: Selected trigger request occurred
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value: 1
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enum/PRW:
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bit_size: 1
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variants:
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- name: Clear
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description: Clears pending bit
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value: 1
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enum/SWIERW:
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bit_size: 1
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variants:
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- name: Pend
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description: Generates an interrupt request
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value: 1
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660
data/registers/syscfg_g0.yaml
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660
data/registers/syscfg_g0.yaml
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@ -0,0 +1,660 @@
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block/SYSCFG:
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description: System configuration controller
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items:
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- byte_offset: 0
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description: SYSCFG configuration register 1
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fieldset: CFGR1
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name: CFGR1
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- byte_offset: 24
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description: SYSCFG configuration register 1
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fieldset: CFGR2
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name: CFGR2
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- byte_offset: 48
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description: VREFBUF control and status register
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fieldset: VREFBUF_CSR
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name: VREFBUF_CSR
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- byte_offset: 52
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description: VREFBUF calibration control register
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fieldset: VREFBUF_CCR
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name: VREFBUF_CCR
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- access: Read
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byte_offset: 128
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description: interrupt line 0 status register
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fieldset: ITLINE0
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name: ITLINE0
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- access: Read
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byte_offset: 132
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description: interrupt line 1 status register
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fieldset: ITLINE1
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name: ITLINE1
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- access: Read
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byte_offset: 136
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description: interrupt line 2 status register
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fieldset: ITLINE2
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name: ITLINE2
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- access: Read
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byte_offset: 140
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description: interrupt line 3 status register
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fieldset: ITLINE3
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name: ITLINE3
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- access: Read
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byte_offset: 144
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description: interrupt line 4 status register
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fieldset: ITLINE4
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name: ITLINE4
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- access: Read
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byte_offset: 148
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description: interrupt line 5 status register
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fieldset: ITLINE5
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name: ITLINE5
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- access: Read
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byte_offset: 152
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description: interrupt line 6 status register
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fieldset: ITLINE6
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name: ITLINE6
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- access: Read
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byte_offset: 156
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description: interrupt line 7 status register
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fieldset: ITLINE7
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name: ITLINE7
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- access: Read
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byte_offset: 160
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description: interrupt line 8 status register
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fieldset: ITLINE8
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name: ITLINE8
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- access: Read
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byte_offset: 164
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description: interrupt line 9 status register
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fieldset: ITLINE9
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name: ITLINE9
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- access: Read
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byte_offset: 168
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description: interrupt line 10 status register
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fieldset: ITLINE10
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name: ITLINE10
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- access: Read
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byte_offset: 172
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description: interrupt line 11 status register
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fieldset: ITLINE11
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name: ITLINE11
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- access: Read
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byte_offset: 176
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description: interrupt line 12 status register
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fieldset: ITLINE12
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name: ITLINE12
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- access: Read
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byte_offset: 180
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description: interrupt line 13 status register
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fieldset: ITLINE13
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name: ITLINE13
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- access: Read
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byte_offset: 184
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description: interrupt line 14 status register
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fieldset: ITLINE14
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name: ITLINE14
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- access: Read
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byte_offset: 188
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description: interrupt line 15 status register
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fieldset: ITLINE15
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name: ITLINE15
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- access: Read
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byte_offset: 192
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description: interrupt line 16 status register
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fieldset: ITLINE16
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name: ITLINE16
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- access: Read
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byte_offset: 196
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description: interrupt line 17 status register
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fieldset: ITLINE17
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name: ITLINE17
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- access: Read
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byte_offset: 200
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description: interrupt line 18 status register
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fieldset: ITLINE18
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name: ITLINE18
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- access: Read
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byte_offset: 204
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description: interrupt line 19 status register
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fieldset: ITLINE19
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name: ITLINE19
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- access: Read
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byte_offset: 208
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description: interrupt line 20 status register
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fieldset: ITLINE20
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name: ITLINE20
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- access: Read
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byte_offset: 212
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description: interrupt line 21 status register
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fieldset: ITLINE21
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name: ITLINE21
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- access: Read
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byte_offset: 216
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description: interrupt line 22 status register
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fieldset: ITLINE22
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name: ITLINE22
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- access: Read
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byte_offset: 220
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description: interrupt line 23 status register
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fieldset: ITLINE23
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name: ITLINE23
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- access: Read
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byte_offset: 224
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description: interrupt line 24 status register
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fieldset: ITLINE24
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name: ITLINE24
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- access: Read
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byte_offset: 228
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description: interrupt line 25 status register
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fieldset: ITLINE25
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name: ITLINE25
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- access: Read
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byte_offset: 232
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description: interrupt line 26 status register
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fieldset: ITLINE26
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name: ITLINE26
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- access: Read
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byte_offset: 236
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description: interrupt line 27 status register
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fieldset: ITLINE27
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name: ITLINE27
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- access: Read
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byte_offset: 240
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description: interrupt line 28 status register
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fieldset: ITLINE28
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name: ITLINE28
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- access: Read
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byte_offset: 244
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description: interrupt line 29 status register
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fieldset: ITLINE29
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name: ITLINE29
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- access: Read
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byte_offset: 248
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description: interrupt line 30 status register
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fieldset: ITLINE30
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name: ITLINE30
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- access: Read
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byte_offset: 252
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description: interrupt line 31 status register
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fieldset: ITLINE31
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name: ITLINE31
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fieldset/CFGR1:
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description: SYSCFG configuration register 1
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fields:
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- bit_offset: 0
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bit_size: 2
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description: Memory mapping selection bits
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name: MEM_MODE
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- bit_offset: 4
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bit_size: 1
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description: PA11 and PA12 remapping bit.
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name: PA11_PA12_RMP
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- bit_offset: 5
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bit_size: 1
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description: IR output polarity selection
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name: IR_POL
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- bit_offset: 6
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bit_size: 2
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description: IR Modulation Envelope signal selection.
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name: IR_MOD
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- bit_offset: 8
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bit_size: 1
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description: I/O analog switch voltage booster enable
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name: BOOSTEN
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- bit_offset: 9
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bit_size: 1
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description: Strobe signal bit for UCPD1
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name: UCPD1_STROBE
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- bit_offset: 10
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bit_size: 1
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description: Strobe signal bit for UCPD2
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name: UCPD2_STROBE
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- bit_offset: 16
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bit_size: 4
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description: Fast Mode Plus (FM+) driving capability activation bits
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name: I2C_PBx_FMP
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- bit_offset: 20
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bit_size: 1
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description: FM+ driving capability activation for I2C1
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name: I2C1_FMP
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- bit_offset: 21
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bit_size: 1
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description: FM+ driving capability activation for I2C2
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name: I2C2_FMP
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- bit_offset: 22
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bit_size: 2
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description: Fast Mode Plus (FM+) driving capability activation bits
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name: I2C_PAx_FMP
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fieldset/CFGR2:
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description: SYSCFG configuration register 1
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fields:
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- bit_offset: 0
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bit_size: 1
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description: Cortex-M0+ LOCKUP bit enable bit
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name: LOCKUP_LOCK
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- bit_offset: 1
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bit_size: 1
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description: SRAM parity lock bit
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name: SRAM_PARITY_LOCK
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- bit_offset: 2
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bit_size: 1
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description: PVD lock enable bit
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name: PVD_LOCK
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- bit_offset: 3
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bit_size: 1
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description: ECC error lock bit
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name: ECC_LOCK
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- bit_offset: 8
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bit_size: 1
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description: SRAM parity error flag
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name: SRAM_PEF
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- bit_offset: 16
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bit_size: 1
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description: PA1_CDEN
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name: PA1_CDEN
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- bit_offset: 17
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bit_size: 1
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description: PA3_CDEN
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name: PA3_CDEN
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- bit_offset: 18
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bit_size: 1
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description: PA5_CDEN
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name: PA5_CDEN
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- bit_offset: 19
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bit_size: 1
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description: PA6_CDEN
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name: PA6_CDEN
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- bit_offset: 20
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bit_size: 1
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description: PA13_CDEN
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name: PA13_CDEN
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- bit_offset: 21
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bit_size: 1
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description: PB0_CDEN
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name: PB0_CDEN
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- bit_offset: 22
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bit_size: 1
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description: PB1_CDEN
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name: PB1_CDEN
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- bit_offset: 23
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bit_size: 1
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description: PB2_CDEN
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name: PB2_CDEN
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fieldset/ITLINE0:
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description: interrupt line 0 status register
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fields:
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- bit_offset: 0
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bit_size: 1
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description: Window watchdog interrupt pending flag
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name: WWDG
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fieldset/ITLINE1:
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description: interrupt line 1 status register
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fields:
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- bit_offset: 0
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bit_size: 1
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description: PVD supply monitoring interrupt request pending (EXTI line 16).
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name: PVDOUT
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fieldset/ITLINE10:
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description: interrupt line 10 status register
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fields:
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- bit_offset: 0
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bit_size: 1
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description: DMA1_CH1
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name: DMA1_CH2
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- bit_offset: 1
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bit_size: 1
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description: DMA1_CH3
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name: DMA1_CH3
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fieldset/ITLINE11:
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description: interrupt line 11 status register
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fields:
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- bit_offset: 0
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bit_size: 1
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description: DMAMUX
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name: DMAMUX
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- bit_offset: 1
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bit_size: 1
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description: DMA1_CH4
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name: DMA1_CH4
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- bit_offset: 2
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bit_size: 1
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description: DMA1_CH5
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name: DMA1_CH5
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- bit_offset: 3
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bit_size: 1
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description: DMA1_CH6
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name: DMA1_CH6
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- bit_offset: 4
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bit_size: 1
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description: DMA1_CH7
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name: DMA1_CH7
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fieldset/ITLINE12:
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description: interrupt line 12 status register
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fields:
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- bit_offset: 0
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bit_size: 1
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description: ADC
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name: ADC
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- array:
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len: 2
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stride: 1
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bit_offset: 1
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bit_size: 1
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description: COMP1
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name: COMP
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fieldset/ITLINE13:
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description: interrupt line 13 status register
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fields:
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- bit_offset: 0
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bit_size: 1
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description: TIM1_CCU
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name: TIM1_CCU
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- bit_offset: 1
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bit_size: 1
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description: TIM1_TRG
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name: TIM1_TRG
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- bit_offset: 2
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||||
bit_size: 1
|
||||
description: TIM1_UPD
|
||||
name: TIM1_UPD
|
||||
- bit_offset: 3
|
||||
bit_size: 1
|
||||
description: TIM1_BRK
|
||||
name: TIM1_BRK
|
||||
fieldset/ITLINE14:
|
||||
description: interrupt line 14 status register
|
||||
fields:
|
||||
- bit_offset: 0
|
||||
bit_size: 1
|
||||
description: TIM1_CC
|
||||
name: TIM1_CC
|
||||
fieldset/ITLINE15:
|
||||
description: interrupt line 15 status register
|
||||
fields:
|
||||
- array:
|
||||
len: 1
|
||||
stride: 0
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
description: TIM2
|
||||
name: TIM
|
||||
fieldset/ITLINE16:
|
||||
description: interrupt line 16 status register
|
||||
fields:
|
||||
- array:
|
||||
len: 1
|
||||
stride: 0
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
description: TIM3
|
||||
name: TIM
|
||||
fieldset/ITLINE17:
|
||||
description: interrupt line 17 status register
|
||||
fields:
|
||||
- array:
|
||||
len: 1
|
||||
stride: 0
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
description: TIM6
|
||||
name: TIM
|
||||
- bit_offset: 1
|
||||
bit_size: 1
|
||||
description: DAC
|
||||
name: DAC
|
||||
- array:
|
||||
len: 1
|
||||
stride: 0
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
description: LPTIM1
|
||||
name: LPTIM
|
||||
fieldset/ITLINE18:
|
||||
description: interrupt line 18 status register
|
||||
fields:
|
||||
- array:
|
||||
len: 1
|
||||
stride: 0
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
description: TIM7
|
||||
name: TIM
|
||||
- array:
|
||||
len: 1
|
||||
stride: 0
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
description: LPTIM2
|
||||
name: LPTIM
|
||||
fieldset/ITLINE19:
|
||||
description: interrupt line 19 status register
|
||||
fields:
|
||||
- array:
|
||||
len: 1
|
||||
stride: 0
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
description: TIM14
|
||||
name: TIM
|
||||
fieldset/ITLINE2:
|
||||
description: interrupt line 2 status register
|
||||
fields:
|
||||
- bit_offset: 0
|
||||
bit_size: 1
|
||||
description: TAMP
|
||||
name: TAMP
|
||||
- bit_offset: 1
|
||||
bit_size: 1
|
||||
description: RTC
|
||||
name: RTC
|
||||
fieldset/ITLINE20:
|
||||
description: interrupt line 20 status register
|
||||
fields:
|
||||
- array:
|
||||
len: 1
|
||||
stride: 0
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
description: TIM15
|
||||
name: TIM
|
||||
fieldset/ITLINE21:
|
||||
description: interrupt line 21 status register
|
||||
fields:
|
||||
- array:
|
||||
len: 1
|
||||
stride: 0
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
description: TIM16
|
||||
name: TIM
|
||||
fieldset/ITLINE22:
|
||||
description: interrupt line 22 status register
|
||||
fields:
|
||||
- array:
|
||||
len: 1
|
||||
stride: 0
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
description: TIM17
|
||||
name: TIM
|
||||
fieldset/ITLINE23:
|
||||
description: interrupt line 23 status register
|
||||
fields:
|
||||
- bit_offset: 0
|
||||
bit_size: 1
|
||||
description: I2C1
|
||||
name: I2C1
|
||||
fieldset/ITLINE24:
|
||||
description: interrupt line 24 status register
|
||||
fields:
|
||||
- bit_offset: 0
|
||||
bit_size: 1
|
||||
description: I2C2
|
||||
name: I2C2
|
||||
fieldset/ITLINE25:
|
||||
description: interrupt line 25 status register
|
||||
fields:
|
||||
- array:
|
||||
len: 1
|
||||
stride: 0
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
description: SPI1
|
||||
name: SPI
|
||||
fieldset/ITLINE26:
|
||||
description: interrupt line 26 status register
|
||||
fields:
|
||||
- array:
|
||||
len: 1
|
||||
stride: 0
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
description: SPI2
|
||||
name: SPI
|
||||
fieldset/ITLINE27:
|
||||
description: interrupt line 27 status register
|
||||
fields:
|
||||
- array:
|
||||
len: 1
|
||||
stride: 0
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
description: USART1
|
||||
name: USART
|
||||
fieldset/ITLINE28:
|
||||
description: interrupt line 28 status register
|
||||
fields:
|
||||
- array:
|
||||
len: 1
|
||||
stride: 0
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
description: USART2
|
||||
name: USART
|
||||
fieldset/ITLINE29:
|
||||
description: interrupt line 29 status register
|
||||
fields:
|
||||
- array:
|
||||
len: 3
|
||||
stride: 1
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
description: USART3
|
||||
name: USART
|
||||
fieldset/ITLINE3:
|
||||
description: interrupt line 3 status register
|
||||
fields:
|
||||
- bit_offset: 0
|
||||
bit_size: 1
|
||||
description: FLASH_ITF
|
||||
name: FLASH_ITF
|
||||
- bit_offset: 1
|
||||
bit_size: 1
|
||||
description: FLASH_ECC
|
||||
name: FLASH_ECC
|
||||
fieldset/ITLINE30:
|
||||
description: interrupt line 30 status register
|
||||
fields:
|
||||
- array:
|
||||
len: 1
|
||||
stride: 0
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
description: CEC
|
||||
name: USART
|
||||
fieldset/ITLINE31:
|
||||
description: interrupt line 31 status register
|
||||
fields:
|
||||
- bit_offset: 0
|
||||
bit_size: 1
|
||||
description: RNG
|
||||
name: RNG
|
||||
- bit_offset: 1
|
||||
bit_size: 1
|
||||
description: AES
|
||||
name: AES
|
||||
fieldset/ITLINE4:
|
||||
description: interrupt line 4 status register
|
||||
fields:
|
||||
- bit_offset: 0
|
||||
bit_size: 1
|
||||
description: RCC
|
||||
name: RCC
|
||||
fieldset/ITLINE5:
|
||||
description: interrupt line 5 status register
|
||||
fields:
|
||||
- array:
|
||||
len: 2
|
||||
stride: 1
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
description: EXTI0
|
||||
name: EXTI
|
||||
fieldset/ITLINE6:
|
||||
description: interrupt line 6 status register
|
||||
fields:
|
||||
- array:
|
||||
len: 2
|
||||
stride: 1
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
description: EXTI2
|
||||
name: EXTI
|
||||
fieldset/ITLINE7:
|
||||
description: interrupt line 7 status register
|
||||
fields:
|
||||
- array:
|
||||
len: 12
|
||||
stride: 1
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
description: EXTI4
|
||||
name: EXTI
|
||||
fieldset/ITLINE8:
|
||||
description: interrupt line 8 status register
|
||||
fields:
|
||||
- array:
|
||||
len: 2
|
||||
stride: 1
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
description: UCPD1
|
||||
name: UCPD
|
||||
fieldset/ITLINE9:
|
||||
description: interrupt line 9 status register
|
||||
fields:
|
||||
- bit_offset: 0
|
||||
bit_size: 1
|
||||
description: DMA1_CH1
|
||||
name: DMA1_CH1
|
||||
fieldset/VREFBUF_CCR:
|
||||
description: VREFBUF calibration control register
|
||||
fields:
|
||||
- bit_offset: 0
|
||||
bit_size: 6
|
||||
description: Trimming code These bits are automatically initialized after reset
|
||||
with the trimming value stored in the Flash memory during the production test.
|
||||
Writing into these bits allows to tune the internal reference buffer voltage.
|
||||
name: TRIM
|
||||
fieldset/VREFBUF_CSR:
|
||||
description: VREFBUF control and status register
|
||||
fields:
|
||||
- bit_offset: 0
|
||||
bit_size: 1
|
||||
description: Voltage reference buffer mode enable This bit is used to enable the
|
||||
voltage reference buffer mode.
|
||||
name: ENVR
|
||||
- bit_offset: 1
|
||||
bit_size: 1
|
||||
description: 'High impedance mode This bit controls the analog switch to connect
|
||||
or not the VREF+ pin. Refer to Table196: VREF buffer modes for the mode descriptions
|
||||
depending on ENVR bit configuration.'
|
||||
name: HIZ
|
||||
- bit_offset: 3
|
||||
bit_size: 1
|
||||
description: Voltage reference buffer ready
|
||||
name: VRR
|
||||
- bit_offset: 4
|
||||
bit_size: 3
|
||||
description: 'Voltage reference scale These bits select the value generated by
|
||||
the voltage reference buffer. Other: Reserved'
|
||||
name: VRS
|
||||
22
parse.py
22
parse.py
@ -347,6 +347,7 @@ perimap = [
|
||||
('STM32L4.*:SYS:.*', 'syscfg_l4/SYSCFG'),
|
||||
('STM32L0.*:SYS:.*', 'syscfg_l0/SYSCFG'),
|
||||
('STM32H7.*:SYS:.*', 'syscfg_h7/SYSCFG'),
|
||||
('STM32G0.*:SYS:.*', 'syscfg_g0/SYSCFG'),
|
||||
('STM32WB55.*:SYS:.*', 'syscfg_wb55/SYSCFG'),
|
||||
('STM32WL.*:SYS:.*', 'syscfg_wl5x/SYSCFG'),
|
||||
('STM32L0.*:RCC:.*', 'rcc_l0/RCC'),
|
||||
@ -409,6 +410,7 @@ address_overrides = {
|
||||
'STM32F412VG:GPIOG_BASE': 0x40021800,
|
||||
}
|
||||
|
||||
|
||||
def lookup_address(defines, name, d):
|
||||
if addr := defines.get(d):
|
||||
return addr
|
||||
@ -661,6 +663,8 @@ def parse_chips():
|
||||
pname = 'SYSCFG'
|
||||
if pname == 'SUBGHZ':
|
||||
pname = 'SUBGHZSPI'
|
||||
if pname == 'SYSCFG_VREFBUF':
|
||||
pname = 'SYSCFG'
|
||||
if pname in FAKE_PERIPHERALS:
|
||||
continue
|
||||
if pname.startswith('ADC'):
|
||||
@ -896,6 +900,8 @@ def parse_chips():
|
||||
block = 'exti_wl5x/EXTI'
|
||||
elif chip_name.startswith("STM32H7"):
|
||||
block = 'exti_h7/EXTI'
|
||||
elif chip_name.startswith("STM32G0"):
|
||||
block = 'exti_g0/EXTI'
|
||||
else:
|
||||
block = 'exti_v1/EXTI'
|
||||
|
||||
@ -957,7 +963,15 @@ def parse_chips():
|
||||
|
||||
for (name, body) in core['peripherals'].items():
|
||||
if 'clock' not in body:
|
||||
if (peri_clock := match_peri_clock(rcc_block, name)) is not None:
|
||||
peri_clock = None
|
||||
if chip_name.startswith('STM32G0') and name.startswith('TIM'):
|
||||
peri_clock = 'APB'
|
||||
if chip_name.startswith('STM32G0') and name.startswith('SYSCFG'):
|
||||
peri_clock = 'APB'
|
||||
else:
|
||||
peri_clock = match_peri_clock(rcc_block, name)
|
||||
|
||||
if peri_clock is not None:
|
||||
core['peripherals'][name]['clock'] = peri_clock
|
||||
|
||||
# Process DMA channels
|
||||
@ -1359,8 +1373,10 @@ def filter_interrupts(peri_irqs, all_irqs):
|
||||
|
||||
return filtered
|
||||
|
||||
|
||||
memories = []
|
||||
|
||||
|
||||
def parse_memories():
|
||||
with open('data/memories.yaml', 'r') as yaml_file:
|
||||
m = yaml.load(yaml_file, Loader=SafeLoader)
|
||||
@ -1376,6 +1392,7 @@ def determine_ram_size(chip_name):
|
||||
|
||||
return None
|
||||
|
||||
|
||||
def determine_flash_size(chip_name):
|
||||
for each in memories:
|
||||
for name in each['names']:
|
||||
@ -1384,6 +1401,7 @@ def determine_flash_size(chip_name):
|
||||
|
||||
return None
|
||||
|
||||
|
||||
def determine_device_id(chip_name):
|
||||
for each in memories:
|
||||
for name in each['names']:
|
||||
@ -1391,12 +1409,12 @@ def determine_device_id(chip_name):
|
||||
return each['device-id']
|
||||
return None
|
||||
|
||||
|
||||
def is_chip_name_match(pattern, chip_name):
|
||||
pattern = pattern.replace('x', '.')
|
||||
return re.match(pattern + ".*", chip_name)
|
||||
|
||||
|
||||
|
||||
parse_memories()
|
||||
parse_interrupts()
|
||||
parse_rcc_regs()
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user