Add STM32G0 support
Includes manually specified register layouts for EXTI and SYSCFG.
This commit is contained in:
Ben Gamari
Dario Nieuwenhuis
parent
075d283354
commit
f57a268b9f
196
data/registers/exti_g0.yaml
Normal file
196
data/registers/exti_g0.yaml
Normal file
@ -0,0 +1,196 @@
|
|||||||
|
---
|
||||||
|
block/EXTI:
|
||||||
|
description: External interrupt/event controller
|
||||||
|
items:
|
||||||
|
- name: RTSR
|
||||||
|
description: Rising Trigger selection register (EXTI_RTSR)
|
||||||
|
byte_offset: 0
|
||||||
|
reset_value: 0
|
||||||
|
fieldset: RTSR
|
||||||
|
array:
|
||||||
|
len: 2
|
||||||
|
stride: 40
|
||||||
|
- name: FTSR
|
||||||
|
description: Falling Trigger selection register (EXTI_FTSR)
|
||||||
|
byte_offset: 4
|
||||||
|
reset_value: 0
|
||||||
|
fieldset: FTSR
|
||||||
|
array:
|
||||||
|
len: 2
|
||||||
|
stride: 40
|
||||||
|
- name: SWIER
|
||||||
|
description: Software interrupt event register (EXTI_SWIER)
|
||||||
|
byte_offset: 8
|
||||||
|
reset_value: 0
|
||||||
|
fieldset: SWIER
|
||||||
|
array:
|
||||||
|
len: 2
|
||||||
|
stride: 40
|
||||||
|
- name: RPR
|
||||||
|
description: Rising pending register (EXTI_RPR)
|
||||||
|
byte_offset: 12
|
||||||
|
reset_value: 0
|
||||||
|
fieldset: RPR
|
||||||
|
array:
|
||||||
|
len: 2
|
||||||
|
stride: 40
|
||||||
|
- name: FPR
|
||||||
|
description: Falling pending register (EXTI_FPR)
|
||||||
|
byte_offset: 16
|
||||||
|
reset_value: 0
|
||||||
|
fieldset: FPR
|
||||||
|
array:
|
||||||
|
len: 2
|
||||||
|
stride: 40
|
||||||
|
|
||||||
|
- name: EXTICR
|
||||||
|
description: external interrupt configuration register
|
||||||
|
array:
|
||||||
|
len: 4
|
||||||
|
stride: 4
|
||||||
|
byte_offset: 96
|
||||||
|
fieldset: EXTICR
|
||||||
|
|
||||||
|
- name: IMR
|
||||||
|
description: internal interrupt configuration register 1
|
||||||
|
array:
|
||||||
|
len: 2
|
||||||
|
stride: 16
|
||||||
|
byte_offset: 128
|
||||||
|
fieldset: IMR
|
||||||
|
|
||||||
|
- name: EMR
|
||||||
|
description: external interrupt configuration register 1
|
||||||
|
array:
|
||||||
|
len: 2
|
||||||
|
stride: 16
|
||||||
|
byte_offset: 132
|
||||||
|
fieldset: EMR
|
||||||
|
|
||||||
|
fieldset/EMR:
|
||||||
|
description: Event mask register (EXTI_EMR)
|
||||||
|
fields:
|
||||||
|
- name: MR
|
||||||
|
description: Event Mask on line 0
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
array:
|
||||||
|
len: 32
|
||||||
|
stride: 1
|
||||||
|
enum: MR
|
||||||
|
fieldset/FPR:
|
||||||
|
description: Falling Trigger pending register (EXTI_FPR)
|
||||||
|
fields:
|
||||||
|
- name: FPIF
|
||||||
|
description: Falling edge event pending for line 0
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
array:
|
||||||
|
len: 32
|
||||||
|
stride: 1
|
||||||
|
enum: PRR
|
||||||
|
fieldset/FTSR:
|
||||||
|
description: Falling Trigger selection register (EXTI_FTSR)
|
||||||
|
fields:
|
||||||
|
- name: TR
|
||||||
|
description: Falling trigger event configuration of line 0
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
array:
|
||||||
|
len: 32
|
||||||
|
stride: 1
|
||||||
|
enum: TR
|
||||||
|
fieldset/IMR:
|
||||||
|
description: Interrupt mask register (EXTI_IMR)
|
||||||
|
fields:
|
||||||
|
- name: MR
|
||||||
|
description: Interrupt Mask on line 0
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
array:
|
||||||
|
len: 32
|
||||||
|
stride: 1
|
||||||
|
enum: MR
|
||||||
|
fieldset/RPR:
|
||||||
|
description: Rising Trigger pending register (EXTI_RPR)
|
||||||
|
fields:
|
||||||
|
- name: RPIF
|
||||||
|
description: Rising edge event pending for line 0
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
array:
|
||||||
|
len: 32
|
||||||
|
stride: 1
|
||||||
|
enum: PRR
|
||||||
|
fieldset/RTSR:
|
||||||
|
description: Rising Trigger selection register (EXTI_RTSR)
|
||||||
|
fields:
|
||||||
|
- name: TR
|
||||||
|
description: Rising trigger event configuration of line 0
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
array:
|
||||||
|
len: 32
|
||||||
|
stride: 1
|
||||||
|
enum: TR
|
||||||
|
fieldset/SWIER:
|
||||||
|
description: Software interrupt event register (EXTI_SWIER)
|
||||||
|
fields:
|
||||||
|
- name: SWIER
|
||||||
|
description: Software Interrupt on line 0
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
array:
|
||||||
|
len: 32
|
||||||
|
stride: 1
|
||||||
|
enum_write: SWIERW
|
||||||
|
fieldset/EXTICR:
|
||||||
|
description: external interrupt configuration register 1
|
||||||
|
fields:
|
||||||
|
- name: EXTI
|
||||||
|
description: EXTI configuration bits
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 4
|
||||||
|
array:
|
||||||
|
len: 4
|
||||||
|
stride: 4
|
||||||
|
enum/MR:
|
||||||
|
bit_size: 1
|
||||||
|
variants:
|
||||||
|
- name: Masked
|
||||||
|
description: Interrupt request line is masked
|
||||||
|
value: 0
|
||||||
|
- name: Unmasked
|
||||||
|
description: Interrupt request line is unmasked
|
||||||
|
value: 1
|
||||||
|
enum/TR:
|
||||||
|
bit_size: 1
|
||||||
|
variants:
|
||||||
|
- name: Disabled
|
||||||
|
description: Falling edge trigger is disabled
|
||||||
|
value: 0
|
||||||
|
- name: Enabled
|
||||||
|
description: Falling edge trigger is enabled
|
||||||
|
value: 1
|
||||||
|
enum/PRR:
|
||||||
|
bit_size: 1
|
||||||
|
variants:
|
||||||
|
- name: NotPending
|
||||||
|
description: No trigger request occurred
|
||||||
|
value: 0
|
||||||
|
- name: Pending
|
||||||
|
description: Selected trigger request occurred
|
||||||
|
value: 1
|
||||||
|
enum/PRW:
|
||||||
|
bit_size: 1
|
||||||
|
variants:
|
||||||
|
- name: Clear
|
||||||
|
description: Clears pending bit
|
||||||
|
value: 1
|
||||||
|
enum/SWIERW:
|
||||||
|
bit_size: 1
|
||||||
|
variants:
|
||||||
|
- name: Pend
|
||||||
|
description: Generates an interrupt request
|
||||||
|
value: 1
|
||||||
|
|
||||||
660
data/registers/syscfg_g0.yaml
Normal file
660
data/registers/syscfg_g0.yaml
Normal file
@ -0,0 +1,660 @@
|
|||||||
|
block/SYSCFG:
|
||||||
|
description: System configuration controller
|
||||||
|
items:
|
||||||
|
- byte_offset: 0
|
||||||
|
description: SYSCFG configuration register 1
|
||||||
|
fieldset: CFGR1
|
||||||
|
name: CFGR1
|
||||||
|
- byte_offset: 24
|
||||||
|
description: SYSCFG configuration register 1
|
||||||
|
fieldset: CFGR2
|
||||||
|
name: CFGR2
|
||||||
|
- byte_offset: 48
|
||||||
|
description: VREFBUF control and status register
|
||||||
|
fieldset: VREFBUF_CSR
|
||||||
|
name: VREFBUF_CSR
|
||||||
|
- byte_offset: 52
|
||||||
|
description: VREFBUF calibration control register
|
||||||
|
fieldset: VREFBUF_CCR
|
||||||
|
name: VREFBUF_CCR
|
||||||
|
- access: Read
|
||||||
|
byte_offset: 128
|
||||||
|
description: interrupt line 0 status register
|
||||||
|
fieldset: ITLINE0
|
||||||
|
name: ITLINE0
|
||||||
|
- access: Read
|
||||||
|
byte_offset: 132
|
||||||
|
description: interrupt line 1 status register
|
||||||
|
fieldset: ITLINE1
|
||||||
|
name: ITLINE1
|
||||||
|
- access: Read
|
||||||
|
byte_offset: 136
|
||||||
|
description: interrupt line 2 status register
|
||||||
|
fieldset: ITLINE2
|
||||||
|
name: ITLINE2
|
||||||
|
- access: Read
|
||||||
|
byte_offset: 140
|
||||||
|
description: interrupt line 3 status register
|
||||||
|
fieldset: ITLINE3
|
||||||
|
name: ITLINE3
|
||||||
|
- access: Read
|
||||||
|
byte_offset: 144
|
||||||
|
description: interrupt line 4 status register
|
||||||
|
fieldset: ITLINE4
|
||||||
|
name: ITLINE4
|
||||||
|
- access: Read
|
||||||
|
byte_offset: 148
|
||||||
|
description: interrupt line 5 status register
|
||||||
|
fieldset: ITLINE5
|
||||||
|
name: ITLINE5
|
||||||
|
- access: Read
|
||||||
|
byte_offset: 152
|
||||||
|
description: interrupt line 6 status register
|
||||||
|
fieldset: ITLINE6
|
||||||
|
name: ITLINE6
|
||||||
|
- access: Read
|
||||||
|
byte_offset: 156
|
||||||
|
description: interrupt line 7 status register
|
||||||
|
fieldset: ITLINE7
|
||||||
|
name: ITLINE7
|
||||||
|
- access: Read
|
||||||
|
byte_offset: 160
|
||||||
|
description: interrupt line 8 status register
|
||||||
|
fieldset: ITLINE8
|
||||||
|
name: ITLINE8
|
||||||
|
- access: Read
|
||||||
|
byte_offset: 164
|
||||||
|
description: interrupt line 9 status register
|
||||||
|
fieldset: ITLINE9
|
||||||
|
name: ITLINE9
|
||||||
|
- access: Read
|
||||||
|
byte_offset: 168
|
||||||
|
description: interrupt line 10 status register
|
||||||
|
fieldset: ITLINE10
|
||||||
|
name: ITLINE10
|
||||||
|
- access: Read
|
||||||
|
byte_offset: 172
|
||||||
|
description: interrupt line 11 status register
|
||||||
|
fieldset: ITLINE11
|
||||||
|
name: ITLINE11
|
||||||
|
- access: Read
|
||||||
|
byte_offset: 176
|
||||||
|
description: interrupt line 12 status register
|
||||||
|
fieldset: ITLINE12
|
||||||
|
name: ITLINE12
|
||||||
|
- access: Read
|
||||||
|
byte_offset: 180
|
||||||
|
description: interrupt line 13 status register
|
||||||
|
fieldset: ITLINE13
|
||||||
|
name: ITLINE13
|
||||||
|
- access: Read
|
||||||
|
byte_offset: 184
|
||||||
|
description: interrupt line 14 status register
|
||||||
|
fieldset: ITLINE14
|
||||||
|
name: ITLINE14
|
||||||
|
- access: Read
|
||||||
|
byte_offset: 188
|
||||||
|
description: interrupt line 15 status register
|
||||||
|
fieldset: ITLINE15
|
||||||
|
name: ITLINE15
|
||||||
|
- access: Read
|
||||||
|
byte_offset: 192
|
||||||
|
description: interrupt line 16 status register
|
||||||
|
fieldset: ITLINE16
|
||||||
|
name: ITLINE16
|
||||||
|
- access: Read
|
||||||
|
byte_offset: 196
|
||||||
|
description: interrupt line 17 status register
|
||||||
|
fieldset: ITLINE17
|
||||||
|
name: ITLINE17
|
||||||
|
- access: Read
|
||||||
|
byte_offset: 200
|
||||||
|
description: interrupt line 18 status register
|
||||||
|
fieldset: ITLINE18
|
||||||
|
name: ITLINE18
|
||||||
|
- access: Read
|
||||||
|
byte_offset: 204
|
||||||
|
description: interrupt line 19 status register
|
||||||
|
fieldset: ITLINE19
|
||||||
|
name: ITLINE19
|
||||||
|
- access: Read
|
||||||
|
byte_offset: 208
|
||||||
|
description: interrupt line 20 status register
|
||||||
|
fieldset: ITLINE20
|
||||||
|
name: ITLINE20
|
||||||
|
- access: Read
|
||||||
|
byte_offset: 212
|
||||||
|
description: interrupt line 21 status register
|
||||||
|
fieldset: ITLINE21
|
||||||
|
name: ITLINE21
|
||||||
|
- access: Read
|
||||||
|
byte_offset: 216
|
||||||
|
description: interrupt line 22 status register
|
||||||
|
fieldset: ITLINE22
|
||||||
|
name: ITLINE22
|
||||||
|
- access: Read
|
||||||
|
byte_offset: 220
|
||||||
|
description: interrupt line 23 status register
|
||||||
|
fieldset: ITLINE23
|
||||||
|
name: ITLINE23
|
||||||
|
- access: Read
|
||||||
|
byte_offset: 224
|
||||||
|
description: interrupt line 24 status register
|
||||||
|
fieldset: ITLINE24
|
||||||
|
name: ITLINE24
|
||||||
|
- access: Read
|
||||||
|
byte_offset: 228
|
||||||
|
description: interrupt line 25 status register
|
||||||
|
fieldset: ITLINE25
|
||||||
|
name: ITLINE25
|
||||||
|
- access: Read
|
||||||
|
byte_offset: 232
|
||||||
|
description: interrupt line 26 status register
|
||||||
|
fieldset: ITLINE26
|
||||||
|
name: ITLINE26
|
||||||
|
- access: Read
|
||||||
|
byte_offset: 236
|
||||||
|
description: interrupt line 27 status register
|
||||||
|
fieldset: ITLINE27
|
||||||
|
name: ITLINE27
|
||||||
|
- access: Read
|
||||||
|
byte_offset: 240
|
||||||
|
description: interrupt line 28 status register
|
||||||
|
fieldset: ITLINE28
|
||||||
|
name: ITLINE28
|
||||||
|
- access: Read
|
||||||
|
byte_offset: 244
|
||||||
|
description: interrupt line 29 status register
|
||||||
|
fieldset: ITLINE29
|
||||||
|
name: ITLINE29
|
||||||
|
- access: Read
|
||||||
|
byte_offset: 248
|
||||||
|
description: interrupt line 30 status register
|
||||||
|
fieldset: ITLINE30
|
||||||
|
name: ITLINE30
|
||||||
|
- access: Read
|
||||||
|
byte_offset: 252
|
||||||
|
description: interrupt line 31 status register
|
||||||
|
fieldset: ITLINE31
|
||||||
|
name: ITLINE31
|
||||||
|
fieldset/CFGR1:
|
||||||
|
description: SYSCFG configuration register 1
|
||||||
|
fields:
|
||||||
|
- bit_offset: 0
|
||||||
|
bit_size: 2
|
||||||
|
description: Memory mapping selection bits
|
||||||
|
name: MEM_MODE
|
||||||
|
- bit_offset: 4
|
||||||
|
bit_size: 1
|
||||||
|
description: PA11 and PA12 remapping bit.
|
||||||
|
name: PA11_PA12_RMP
|
||||||
|
- bit_offset: 5
|
||||||
|
bit_size: 1
|
||||||
|
description: IR output polarity selection
|
||||||
|
name: IR_POL
|
||||||
|
- bit_offset: 6
|
||||||
|
bit_size: 2
|
||||||
|
description: IR Modulation Envelope signal selection.
|
||||||
|
name: IR_MOD
|
||||||
|
- bit_offset: 8
|
||||||
|
bit_size: 1
|
||||||
|
description: I/O analog switch voltage booster enable
|
||||||
|
name: BOOSTEN
|
||||||
|
- bit_offset: 9
|
||||||
|
bit_size: 1
|
||||||
|
description: Strobe signal bit for UCPD1
|
||||||
|
name: UCPD1_STROBE
|
||||||
|
- bit_offset: 10
|
||||||
|
bit_size: 1
|
||||||
|
description: Strobe signal bit for UCPD2
|
||||||
|
name: UCPD2_STROBE
|
||||||
|
- bit_offset: 16
|
||||||
|
bit_size: 4
|
||||||
|
description: Fast Mode Plus (FM+) driving capability activation bits
|
||||||
|
name: I2C_PBx_FMP
|
||||||
|
- bit_offset: 20
|
||||||
|
bit_size: 1
|
||||||
|
description: FM+ driving capability activation for I2C1
|
||||||
|
name: I2C1_FMP
|
||||||
|
- bit_offset: 21
|
||||||
|
bit_size: 1
|
||||||
|
description: FM+ driving capability activation for I2C2
|
||||||
|
name: I2C2_FMP
|
||||||
|
- bit_offset: 22
|
||||||
|
bit_size: 2
|
||||||
|
description: Fast Mode Plus (FM+) driving capability activation bits
|
||||||
|
name: I2C_PAx_FMP
|
||||||
|
fieldset/CFGR2:
|
||||||
|
description: SYSCFG configuration register 1
|
||||||
|
fields:
|
||||||
|
- bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
description: Cortex-M0+ LOCKUP bit enable bit
|
||||||
|
name: LOCKUP_LOCK
|
||||||
|
- bit_offset: 1
|
||||||
|
bit_size: 1
|
||||||
|
description: SRAM parity lock bit
|
||||||
|
name: SRAM_PARITY_LOCK
|
||||||
|
- bit_offset: 2
|
||||||
|
bit_size: 1
|
||||||
|
description: PVD lock enable bit
|
||||||
|
name: PVD_LOCK
|
||||||
|
- bit_offset: 3
|
||||||
|
bit_size: 1
|
||||||
|
description: ECC error lock bit
|
||||||
|
name: ECC_LOCK
|
||||||
|
- bit_offset: 8
|
||||||
|
bit_size: 1
|
||||||
|
description: SRAM parity error flag
|
||||||
|
name: SRAM_PEF
|
||||||
|
- bit_offset: 16
|
||||||
|
bit_size: 1
|
||||||
|
description: PA1_CDEN
|
||||||
|
name: PA1_CDEN
|
||||||
|
- bit_offset: 17
|
||||||
|
bit_size: 1
|
||||||
|
description: PA3_CDEN
|
||||||
|
name: PA3_CDEN
|
||||||
|
- bit_offset: 18
|
||||||
|
bit_size: 1
|
||||||
|
description: PA5_CDEN
|
||||||
|
name: PA5_CDEN
|
||||||
|
- bit_offset: 19
|
||||||
|
bit_size: 1
|
||||||
|
description: PA6_CDEN
|
||||||
|
name: PA6_CDEN
|
||||||
|
- bit_offset: 20
|
||||||
|
bit_size: 1
|
||||||
|
description: PA13_CDEN
|
||||||
|
name: PA13_CDEN
|
||||||
|
- bit_offset: 21
|
||||||
|
bit_size: 1
|
||||||
|
description: PB0_CDEN
|
||||||
|
name: PB0_CDEN
|
||||||
|
- bit_offset: 22
|
||||||
|
bit_size: 1
|
||||||
|
description: PB1_CDEN
|
||||||
|
name: PB1_CDEN
|
||||||
|
- bit_offset: 23
|
||||||
|
bit_size: 1
|
||||||
|
description: PB2_CDEN
|
||||||
|
name: PB2_CDEN
|
||||||
|
fieldset/ITLINE0:
|
||||||
|
description: interrupt line 0 status register
|
||||||
|
fields:
|
||||||
|
- bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
description: Window watchdog interrupt pending flag
|
||||||
|
name: WWDG
|
||||||
|
fieldset/ITLINE1:
|
||||||
|
description: interrupt line 1 status register
|
||||||
|
fields:
|
||||||
|
- bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
description: PVD supply monitoring interrupt request pending (EXTI line 16).
|
||||||
|
name: PVDOUT
|
||||||
|
fieldset/ITLINE10:
|
||||||
|
description: interrupt line 10 status register
|
||||||
|
fields:
|
||||||
|
- bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
description: DMA1_CH1
|
||||||
|
name: DMA1_CH2
|
||||||
|
- bit_offset: 1
|
||||||
|
bit_size: 1
|
||||||
|
description: DMA1_CH3
|
||||||
|
name: DMA1_CH3
|
||||||
|
fieldset/ITLINE11:
|
||||||
|
description: interrupt line 11 status register
|
||||||
|
fields:
|
||||||
|
- bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
description: DMAMUX
|
||||||
|
name: DMAMUX
|
||||||
|
- bit_offset: 1
|
||||||
|
bit_size: 1
|
||||||
|
description: DMA1_CH4
|
||||||
|
name: DMA1_CH4
|
||||||
|
- bit_offset: 2
|
||||||
|
bit_size: 1
|
||||||
|
description: DMA1_CH5
|
||||||
|
name: DMA1_CH5
|
||||||
|
- bit_offset: 3
|
||||||
|
bit_size: 1
|
||||||
|
description: DMA1_CH6
|
||||||
|
name: DMA1_CH6
|
||||||
|
- bit_offset: 4
|
||||||
|
bit_size: 1
|
||||||
|
description: DMA1_CH7
|
||||||
|
name: DMA1_CH7
|
||||||
|
fieldset/ITLINE12:
|
||||||
|
description: interrupt line 12 status register
|
||||||
|
fields:
|
||||||
|
- bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
description: ADC
|
||||||
|
name: ADC
|
||||||
|
- array:
|
||||||
|
len: 2
|
||||||
|
stride: 1
|
||||||
|
bit_offset: 1
|
||||||
|
bit_size: 1
|
||||||
|
description: COMP1
|
||||||
|
name: COMP
|
||||||
|
fieldset/ITLINE13:
|
||||||
|
description: interrupt line 13 status register
|
||||||
|
fields:
|
||||||
|
- bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
description: TIM1_CCU
|
||||||
|
name: TIM1_CCU
|
||||||
|
- bit_offset: 1
|
||||||
|
bit_size: 1
|
||||||
|
description: TIM1_TRG
|
||||||
|
name: TIM1_TRG
|
||||||
|
- bit_offset: 2
|
||||||
|
bit_size: 1
|
||||||
|
description: TIM1_UPD
|
||||||
|
name: TIM1_UPD
|
||||||
|
- bit_offset: 3
|
||||||
|
bit_size: 1
|
||||||
|
description: TIM1_BRK
|
||||||
|
name: TIM1_BRK
|
||||||
|
fieldset/ITLINE14:
|
||||||
|
description: interrupt line 14 status register
|
||||||
|
fields:
|
||||||
|
- bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
description: TIM1_CC
|
||||||
|
name: TIM1_CC
|
||||||
|
fieldset/ITLINE15:
|
||||||
|
description: interrupt line 15 status register
|
||||||
|
fields:
|
||||||
|
- array:
|
||||||
|
len: 1
|
||||||
|
stride: 0
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
description: TIM2
|
||||||
|
name: TIM
|
||||||
|
fieldset/ITLINE16:
|
||||||
|
description: interrupt line 16 status register
|
||||||
|
fields:
|
||||||
|
- array:
|
||||||
|
len: 1
|
||||||
|
stride: 0
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
description: TIM3
|
||||||
|
name: TIM
|
||||||
|
fieldset/ITLINE17:
|
||||||
|
description: interrupt line 17 status register
|
||||||
|
fields:
|
||||||
|
- array:
|
||||||
|
len: 1
|
||||||
|
stride: 0
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
description: TIM6
|
||||||
|
name: TIM
|
||||||
|
- bit_offset: 1
|
||||||
|
bit_size: 1
|
||||||
|
description: DAC
|
||||||
|
name: DAC
|
||||||
|
- array:
|
||||||
|
len: 1
|
||||||
|
stride: 0
|
||||||
|
bit_offset: 2
|
||||||
|
bit_size: 1
|
||||||
|
description: LPTIM1
|
||||||
|
name: LPTIM
|
||||||
|
fieldset/ITLINE18:
|
||||||
|
description: interrupt line 18 status register
|
||||||
|
fields:
|
||||||
|
- array:
|
||||||
|
len: 1
|
||||||
|
stride: 0
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
description: TIM7
|
||||||
|
name: TIM
|
||||||
|
- array:
|
||||||
|
len: 1
|
||||||
|
stride: 0
|
||||||
|
bit_offset: 1
|
||||||
|
bit_size: 1
|
||||||
|
description: LPTIM2
|
||||||
|
name: LPTIM
|
||||||
|
fieldset/ITLINE19:
|
||||||
|
description: interrupt line 19 status register
|
||||||
|
fields:
|
||||||
|
- array:
|
||||||
|
len: 1
|
||||||
|
stride: 0
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
description: TIM14
|
||||||
|
name: TIM
|
||||||
|
fieldset/ITLINE2:
|
||||||
|
description: interrupt line 2 status register
|
||||||
|
fields:
|
||||||
|
- bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
description: TAMP
|
||||||
|
name: TAMP
|
||||||
|
- bit_offset: 1
|
||||||
|
bit_size: 1
|
||||||
|
description: RTC
|
||||||
|
name: RTC
|
||||||
|
fieldset/ITLINE20:
|
||||||
|
description: interrupt line 20 status register
|
||||||
|
fields:
|
||||||
|
- array:
|
||||||
|
len: 1
|
||||||
|
stride: 0
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
description: TIM15
|
||||||
|
name: TIM
|
||||||
|
fieldset/ITLINE21:
|
||||||
|
description: interrupt line 21 status register
|
||||||
|
fields:
|
||||||
|
- array:
|
||||||
|
len: 1
|
||||||
|
stride: 0
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
description: TIM16
|
||||||
|
name: TIM
|
||||||
|
fieldset/ITLINE22:
|
||||||
|
description: interrupt line 22 status register
|
||||||
|
fields:
|
||||||
|
- array:
|
||||||
|
len: 1
|
||||||
|
stride: 0
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
description: TIM17
|
||||||
|
name: TIM
|
||||||
|
fieldset/ITLINE23:
|
||||||
|
description: interrupt line 23 status register
|
||||||
|
fields:
|
||||||
|
- bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
description: I2C1
|
||||||
|
name: I2C1
|
||||||
|
fieldset/ITLINE24:
|
||||||
|
description: interrupt line 24 status register
|
||||||
|
fields:
|
||||||
|
- bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
description: I2C2
|
||||||
|
name: I2C2
|
||||||
|
fieldset/ITLINE25:
|
||||||
|
description: interrupt line 25 status register
|
||||||
|
fields:
|
||||||
|
- array:
|
||||||
|
len: 1
|
||||||
|
stride: 0
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
description: SPI1
|
||||||
|
name: SPI
|
||||||
|
fieldset/ITLINE26:
|
||||||
|
description: interrupt line 26 status register
|
||||||
|
fields:
|
||||||
|
- array:
|
||||||
|
len: 1
|
||||||
|
stride: 0
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
description: SPI2
|
||||||
|
name: SPI
|
||||||
|
fieldset/ITLINE27:
|
||||||
|
description: interrupt line 27 status register
|
||||||
|
fields:
|
||||||
|
- array:
|
||||||
|
len: 1
|
||||||
|
stride: 0
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
description: USART1
|
||||||
|
name: USART
|
||||||
|
fieldset/ITLINE28:
|
||||||
|
description: interrupt line 28 status register
|
||||||
|
fields:
|
||||||
|
- array:
|
||||||
|
len: 1
|
||||||
|
stride: 0
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
description: USART2
|
||||||
|
name: USART
|
||||||
|
fieldset/ITLINE29:
|
||||||
|
description: interrupt line 29 status register
|
||||||
|
fields:
|
||||||
|
- array:
|
||||||
|
len: 3
|
||||||
|
stride: 1
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
description: USART3
|
||||||
|
name: USART
|
||||||
|
fieldset/ITLINE3:
|
||||||
|
description: interrupt line 3 status register
|
||||||
|
fields:
|
||||||
|
- bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
description: FLASH_ITF
|
||||||
|
name: FLASH_ITF
|
||||||
|
- bit_offset: 1
|
||||||
|
bit_size: 1
|
||||||
|
description: FLASH_ECC
|
||||||
|
name: FLASH_ECC
|
||||||
|
fieldset/ITLINE30:
|
||||||
|
description: interrupt line 30 status register
|
||||||
|
fields:
|
||||||
|
- array:
|
||||||
|
len: 1
|
||||||
|
stride: 0
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
description: CEC
|
||||||
|
name: USART
|
||||||
|
fieldset/ITLINE31:
|
||||||
|
description: interrupt line 31 status register
|
||||||
|
fields:
|
||||||
|
- bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
description: RNG
|
||||||
|
name: RNG
|
||||||
|
- bit_offset: 1
|
||||||
|
bit_size: 1
|
||||||
|
description: AES
|
||||||
|
name: AES
|
||||||
|
fieldset/ITLINE4:
|
||||||
|
description: interrupt line 4 status register
|
||||||
|
fields:
|
||||||
|
- bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
description: RCC
|
||||||
|
name: RCC
|
||||||
|
fieldset/ITLINE5:
|
||||||
|
description: interrupt line 5 status register
|
||||||
|
fields:
|
||||||
|
- array:
|
||||||
|
len: 2
|
||||||
|
stride: 1
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
description: EXTI0
|
||||||
|
name: EXTI
|
||||||
|
fieldset/ITLINE6:
|
||||||
|
description: interrupt line 6 status register
|
||||||
|
fields:
|
||||||
|
- array:
|
||||||
|
len: 2
|
||||||
|
stride: 1
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
description: EXTI2
|
||||||
|
name: EXTI
|
||||||
|
fieldset/ITLINE7:
|
||||||
|
description: interrupt line 7 status register
|
||||||
|
fields:
|
||||||
|
- array:
|
||||||
|
len: 12
|
||||||
|
stride: 1
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
description: EXTI4
|
||||||
|
name: EXTI
|
||||||
|
fieldset/ITLINE8:
|
||||||
|
description: interrupt line 8 status register
|
||||||
|
fields:
|
||||||
|
- array:
|
||||||
|
len: 2
|
||||||
|
stride: 1
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
description: UCPD1
|
||||||
|
name: UCPD
|
||||||
|
fieldset/ITLINE9:
|
||||||
|
description: interrupt line 9 status register
|
||||||
|
fields:
|
||||||
|
- bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
description: DMA1_CH1
|
||||||
|
name: DMA1_CH1
|
||||||
|
fieldset/VREFBUF_CCR:
|
||||||
|
description: VREFBUF calibration control register
|
||||||
|
fields:
|
||||||
|
- bit_offset: 0
|
||||||
|
bit_size: 6
|
||||||
|
description: Trimming code These bits are automatically initialized after reset
|
||||||
|
with the trimming value stored in the Flash memory during the production test.
|
||||||
|
Writing into these bits allows to tune the internal reference buffer voltage.
|
||||||
|
name: TRIM
|
||||||
|
fieldset/VREFBUF_CSR:
|
||||||
|
description: VREFBUF control and status register
|
||||||
|
fields:
|
||||||
|
- bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
description: Voltage reference buffer mode enable This bit is used to enable the
|
||||||
|
voltage reference buffer mode.
|
||||||
|
name: ENVR
|
||||||
|
- bit_offset: 1
|
||||||
|
bit_size: 1
|
||||||
|
description: 'High impedance mode This bit controls the analog switch to connect
|
||||||
|
or not the VREF+ pin. Refer to Table196: VREF buffer modes for the mode descriptions
|
||||||
|
depending on ENVR bit configuration.'
|
||||||
|
name: HIZ
|
||||||
|
- bit_offset: 3
|
||||||
|
bit_size: 1
|
||||||
|
description: Voltage reference buffer ready
|
||||||
|
name: VRR
|
||||||
|
- bit_offset: 4
|
||||||
|
bit_size: 3
|
||||||
|
description: 'Voltage reference scale These bits select the value generated by
|
||||||
|
the voltage reference buffer. Other: Reserved'
|
||||||
|
name: VRS
|
||||||
32
parse.py
32
parse.py
@ -48,7 +48,7 @@ def removeprefix(value: str, prefix: str, /) -> str:
|
|||||||
|
|
||||||
|
|
||||||
def corename(d):
|
def corename(d):
|
||||||
#print("CHECKING CORENAME", d)
|
# print("CHECKING CORENAME", d)
|
||||||
if m := re.match('.*Cortex-M(\d+)(\+?)\s*(.*)', d):
|
if m := re.match('.*Cortex-M(\d+)(\+?)\s*(.*)', d):
|
||||||
name = "cm" + str(m.group(1))
|
name = "cm" + str(m.group(1))
|
||||||
if m.group(2) == "+":
|
if m.group(2) == "+":
|
||||||
@ -347,6 +347,7 @@ perimap = [
|
|||||||
('STM32L4.*:SYS:.*', 'syscfg_l4/SYSCFG'),
|
('STM32L4.*:SYS:.*', 'syscfg_l4/SYSCFG'),
|
||||||
('STM32L0.*:SYS:.*', 'syscfg_l0/SYSCFG'),
|
('STM32L0.*:SYS:.*', 'syscfg_l0/SYSCFG'),
|
||||||
('STM32H7.*:SYS:.*', 'syscfg_h7/SYSCFG'),
|
('STM32H7.*:SYS:.*', 'syscfg_h7/SYSCFG'),
|
||||||
|
('STM32G0.*:SYS:.*', 'syscfg_g0/SYSCFG'),
|
||||||
('STM32WB55.*:SYS:.*', 'syscfg_wb55/SYSCFG'),
|
('STM32WB55.*:SYS:.*', 'syscfg_wb55/SYSCFG'),
|
||||||
('STM32WL.*:SYS:.*', 'syscfg_wl5x/SYSCFG'),
|
('STM32WL.*:SYS:.*', 'syscfg_wl5x/SYSCFG'),
|
||||||
('STM32L0.*:RCC:.*', 'rcc_l0/RCC'),
|
('STM32L0.*:RCC:.*', 'rcc_l0/RCC'),
|
||||||
@ -409,6 +410,7 @@ address_overrides = {
|
|||||||
'STM32F412VG:GPIOG_BASE': 0x40021800,
|
'STM32F412VG:GPIOG_BASE': 0x40021800,
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
def lookup_address(defines, name, d):
|
def lookup_address(defines, name, d):
|
||||||
if addr := defines.get(d):
|
if addr := defines.get(d):
|
||||||
return addr
|
return addr
|
||||||
@ -661,6 +663,8 @@ def parse_chips():
|
|||||||
pname = 'SYSCFG'
|
pname = 'SYSCFG'
|
||||||
if pname == 'SUBGHZ':
|
if pname == 'SUBGHZ':
|
||||||
pname = 'SUBGHZSPI'
|
pname = 'SUBGHZSPI'
|
||||||
|
if pname == 'SYSCFG_VREFBUF':
|
||||||
|
pname = 'SYSCFG'
|
||||||
if pname in FAKE_PERIPHERALS:
|
if pname in FAKE_PERIPHERALS:
|
||||||
continue
|
continue
|
||||||
if pname.startswith('ADC'):
|
if pname.startswith('ADC'):
|
||||||
@ -749,9 +753,9 @@ def parse_chips():
|
|||||||
|
|
||||||
found.append(key)
|
found.append(key)
|
||||||
|
|
||||||
chip['flash']['regions'][key] = OrderedDict( {
|
chip['flash']['regions'][key] = OrderedDict({
|
||||||
'base': HexInt(h['defines']['all'][each + '_BASE'])
|
'base': HexInt(h['defines']['all'][each + '_BASE'])
|
||||||
} )
|
})
|
||||||
|
|
||||||
if key == 'BANK_1' or key == 'BANK_2':
|
if key == 'BANK_1' or key == 'BANK_2':
|
||||||
flash_size = determine_flash_size(chip_name)
|
flash_size = determine_flash_size(chip_name)
|
||||||
@ -776,9 +780,9 @@ def parse_chips():
|
|||||||
|
|
||||||
found.append(key)
|
found.append(key)
|
||||||
|
|
||||||
chip['ram']['regions'][key] = OrderedDict( {
|
chip['ram']['regions'][key] = OrderedDict({
|
||||||
'base': HexInt(h['defines']['all'][each + '_BASE'])
|
'base': HexInt(h['defines']['all'][each + '_BASE'])
|
||||||
} )
|
})
|
||||||
|
|
||||||
if key == 'SRAM':
|
if key == 'SRAM':
|
||||||
ram_size = determine_ram_size(chip_name)
|
ram_size = determine_ram_size(chip_name)
|
||||||
@ -896,6 +900,8 @@ def parse_chips():
|
|||||||
block = 'exti_wl5x/EXTI'
|
block = 'exti_wl5x/EXTI'
|
||||||
elif chip_name.startswith("STM32H7"):
|
elif chip_name.startswith("STM32H7"):
|
||||||
block = 'exti_h7/EXTI'
|
block = 'exti_h7/EXTI'
|
||||||
|
elif chip_name.startswith("STM32G0"):
|
||||||
|
block = 'exti_g0/EXTI'
|
||||||
else:
|
else:
|
||||||
block = 'exti_v1/EXTI'
|
block = 'exti_v1/EXTI'
|
||||||
|
|
||||||
@ -957,7 +963,15 @@ def parse_chips():
|
|||||||
|
|
||||||
for (name, body) in core['peripherals'].items():
|
for (name, body) in core['peripherals'].items():
|
||||||
if 'clock' not in body:
|
if 'clock' not in body:
|
||||||
if (peri_clock := match_peri_clock(rcc_block, name)) is not None:
|
peri_clock = None
|
||||||
|
if chip_name.startswith('STM32G0') and name.startswith('TIM'):
|
||||||
|
peri_clock = 'APB'
|
||||||
|
if chip_name.startswith('STM32G0') and name.startswith('SYSCFG'):
|
||||||
|
peri_clock = 'APB'
|
||||||
|
else:
|
||||||
|
peri_clock = match_peri_clock(rcc_block, name)
|
||||||
|
|
||||||
|
if peri_clock is not None:
|
||||||
core['peripherals'][name]['clock'] = peri_clock
|
core['peripherals'][name]['clock'] = peri_clock
|
||||||
|
|
||||||
# Process DMA channels
|
# Process DMA channels
|
||||||
@ -1359,8 +1373,10 @@ def filter_interrupts(peri_irqs, all_irqs):
|
|||||||
|
|
||||||
return filtered
|
return filtered
|
||||||
|
|
||||||
|
|
||||||
memories = []
|
memories = []
|
||||||
|
|
||||||
|
|
||||||
def parse_memories():
|
def parse_memories():
|
||||||
with open('data/memories.yaml', 'r') as yaml_file:
|
with open('data/memories.yaml', 'r') as yaml_file:
|
||||||
m = yaml.load(yaml_file, Loader=SafeLoader)
|
m = yaml.load(yaml_file, Loader=SafeLoader)
|
||||||
@ -1376,6 +1392,7 @@ def determine_ram_size(chip_name):
|
|||||||
|
|
||||||
return None
|
return None
|
||||||
|
|
||||||
|
|
||||||
def determine_flash_size(chip_name):
|
def determine_flash_size(chip_name):
|
||||||
for each in memories:
|
for each in memories:
|
||||||
for name in each['names']:
|
for name in each['names']:
|
||||||
@ -1384,6 +1401,7 @@ def determine_flash_size(chip_name):
|
|||||||
|
|
||||||
return None
|
return None
|
||||||
|
|
||||||
|
|
||||||
def determine_device_id(chip_name):
|
def determine_device_id(chip_name):
|
||||||
for each in memories:
|
for each in memories:
|
||||||
for name in each['names']:
|
for name in each['names']:
|
||||||
@ -1391,12 +1409,12 @@ def determine_device_id(chip_name):
|
|||||||
return each['device-id']
|
return each['device-id']
|
||||||
return None
|
return None
|
||||||
|
|
||||||
|
|
||||||
def is_chip_name_match(pattern, chip_name):
|
def is_chip_name_match(pattern, chip_name):
|
||||||
pattern = pattern.replace('x', '.')
|
pattern = pattern.replace('x', '.')
|
||||||
return re.match(pattern + ".*", chip_name)
|
return re.match(pattern + ".*", chip_name)
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
parse_memories()
|
parse_memories()
|
||||||
parse_interrupts()
|
parse_interrupts()
|
||||||
parse_rcc_regs()
|
parse_rcc_regs()
|
||||||
|
|||||||
Loading…
x
Reference in New Issue
Block a user