branch from pka_v1b to pka_v1c

data/registers/pka_v1c.yaml

@@ -0,0 +1,92 @@
+block/PKA:
+  description: Private key accelerator.
+  items:
+  - name: CR
+    description: PKA control register.
+    byte_offset: 0
+    fieldset: CR
+  - name: SR
+    description: PKA status register.
+    byte_offset: 4
+    fieldset: SR
+  - name: CLRFR
+    description: PKA clear flag register.
+    byte_offset: 8
+    fieldset: CLRFR
+fieldset/CLRFR:
+  description: PKA clear flag register.
+  fields:
+  - name: PROCENDFC
+    description: Clear PKA End of Operation flag.
+    bit_offset: 17
+    bit_size: 1
+  - name: RAMERRFC
+    description: Clear PKA RAM error flag.
+    bit_offset: 19
+    bit_size: 1
+  - name: ADDRERRFC
+    description: Clear address error flag.
+    bit_offset: 20
+    bit_size: 1
+  - name: OPERRFC
+    description: Clear operation error flag.
+    bit_offset: 21
+    bit_size: 1
+fieldset/CR:
+  description: PKA control register.
+  fields:
+  - name: EN
+    description: PKA enable. When an illegal operation is selected while EN=1 OPERRF bit is set in PKA_SR. See PKA_CR.MODE bitfield for details. When EN=0 PKA RAM can still be accessed by the application.
+    bit_offset: 0
+    bit_size: 1
+  - name: START
+    description: start the operation Writing 1 to this bit starts the operation which is selected by MODE[5:0], using the operands and data already written to the PKA RAM. This bit is always read as 0. When an illegal operation is selected while START bit is set no operation is started, and OPERRF bit is set in PKA_SR. START is ignored if PKA is busy.
+    bit_offset: 1
+    bit_size: 1
+  - name: MODE
+    description: PKA operation code When an operation not listed here is written by the application with EN bit set, OPERRF bit is set in PKA_SR register, and the write to MODE bitfield is ignored. When PKA is configured in limited mode (LMF = 1 in PKA_SR), writing a MODE different from 0x26 with EN bit to 1 triggers OPERRF bit to be set and write to MODE bit is ignored.
+    bit_offset: 8
+    bit_size: 6
+  - name: PROCENDIE
+    description: End of operation interrupt enable.
+    bit_offset: 17
+    bit_size: 1
+  - name: RAMERRIE
+    description: RAM error interrupt enable.
+    bit_offset: 19
+    bit_size: 1
+  - name: ADDRERRIE
+    description: Address error interrupt enable.
+    bit_offset: 20
+    bit_size: 1
+  - name: OPERRIE
+    description: Operation error interrupt enable.
+    bit_offset: 21
+    bit_size: 1
+fieldset/SR:
+  description: PKA status register.
+  fields:
+  - name: INITOK
+    description: PKA initialization OK This bit is asserted when PKA initialization is complete. When RNG is not able to output proper random numbers INITOK stays at 0.
+    bit_offset: 0
+    bit_size: 1
+  - name: BUSY
+    description: PKA operation is in progress This bit is set to 1 whenever START bit in the PKA_CR is set. It is automatically cleared when the computation is complete, meaning that PKA RAM can be safely accessed and a new operation can be started. If PKA is started with a wrong opcode, it is busy for a couple of cycles, then it aborts automatically the operation and go back to ready (BUSY bit is set to 0).
+    bit_offset: 16
+    bit_size: 1
+  - name: PROCENDF
+    description: PKA End of Operation flag.
+    bit_offset: 17
+    bit_size: 1
+  - name: RAMERRF
+    description: PKA RAM error flag This bit is cleared using RAMERRFC bit in PKA_CLRFR.
+    bit_offset: 19
+    bit_size: 1
+  - name: ADDRERRF
+    description: Address error flag This bit is cleared using ADDRERRFC bit in PKA_CLRFR.
+    bit_offset: 20
+    bit_size: 1
+  - name: OPERRF
+    description: Operation error flag This bit is cleared using OPERRFC bit in PKA_CLRFR.
+    bit_offset: 21
+    bit_size: 1