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Not all L0s have HSI48/CRS.

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This commit is contained in:
Dario Nieuwenhuis 2023-10-11 01:21:26 +02:00
parent 71f81b44e3
commit f40f5a40c1
3 changed files with 1263 additions and 41 deletions
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43
data/registers/rcc_l0.yaml
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@ -9,10 +9,6 @@ block/RCC:
description: Internal clock sources calibration register description: Internal clock sources calibration register
byte_offset: 4 byte_offset: 4
fieldset: ICSCR fieldset: ICSCR
- name: CRRCR
description: Clock recovery RC register
byte_offset: 8
fieldset: CRRCR
- name: CFGR - name: CFGR
description: Clock configuration register description: Clock configuration register
byte_offset: 12 byte_offset: 12
@ -528,10 +524,6 @@ fieldset/CCIPR:
bit_offset: 18 bit_offset: 18
bit_size: 2 bit_size: 2
enum: LPTIMSEL enum: LPTIMSEL
- name: HSI48MSEL
description: 48 MHz HSI48 clock source selection
bit_offset: 26
bit_size: 1
fieldset/CFGR: fieldset/CFGR:
description: Clock configuration register description: Clock configuration register
fields: fields:
@ -583,7 +575,7 @@ fieldset/CFGR:
- name: MCOSEL - name: MCOSEL
description: Microcontroller clock output selection description: Microcontroller clock output selection
bit_offset: 24 bit_offset: 24
bit_size: 3 bit_size: 4
enum: MCOSEL enum: MCOSEL
- name: MCOPRE - name: MCOPRE
description: Microcontroller clock output prescaler description: Microcontroller clock output prescaler
@ -617,10 +609,6 @@ fieldset/CICR:
description: MSI ready Interrupt clear description: MSI ready Interrupt clear
bit_offset: 5 bit_offset: 5
bit_size: 1 bit_size: 1
- name: HSI48RDYC
description: HSI48 ready Interrupt clear
bit_offset: 6
bit_size: 1
- name: CSSLSEC - name: CSSLSEC
description: LSE Clock Security System Interrupt clear description: LSE Clock Security System Interrupt clear
bit_offset: 7 bit_offset: 7
@ -656,10 +644,6 @@ fieldset/CIER:
description: MSI ready interrupt flag description: MSI ready interrupt flag
bit_offset: 5 bit_offset: 5
bit_size: 1 bit_size: 1
- name: HSI48RDYIE
description: HSI48 ready interrupt flag
bit_offset: 6
bit_size: 1
- name: CSSLSE - name: CSSLSE
description: LSE CSS interrupt flag description: LSE CSS interrupt flag
bit_offset: 7 bit_offset: 7
@ -691,10 +675,6 @@ fieldset/CIFR:
description: MSI ready interrupt flag description: MSI ready interrupt flag
bit_offset: 5 bit_offset: 5
bit_size: 1 bit_size: 1
- name: HSI48RDYF
description: HSI48 ready interrupt flag
bit_offset: 6
bit_size: 1
- name: CSSLSEF - name: CSSLSEF
description: LSE Clock Security System Interrupt flag description: LSE Clock Security System Interrupt flag
bit_offset: 7 bit_offset: 7
@ -714,7 +694,7 @@ fieldset/CR:
description: High-speed internal clock enable bit for some IP kernels description: High-speed internal clock enable bit for some IP kernels
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
- name: HSI16RDYF - name: HSI16RDY
description: Internal high-speed clock ready flag description: Internal high-speed clock ready flag
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
@ -767,25 +747,6 @@ fieldset/CR:
description: PLL clock ready flag description: PLL clock ready flag
bit_offset: 25 bit_offset: 25
bit_size: 1 bit_size: 1
fieldset/CRRCR:
description: Clock recovery RC register
fields:
- name: HSI48ON
description: 48MHz HSI clock enable
bit_offset: 0
bit_size: 1
- name: HSI48RDY
description: 48MHz HSI clock ready flag
bit_offset: 1
bit_size: 1
- name: HSI48DIV6EN
description: 48 MHz HSI clock divided by 6 output enable
bit_offset: 2
bit_size: 1
- name: HSI48CAL
description: 48 MHz HSI clock calibration
bit_offset: 8
bit_size: 8
fieldset/CSR: fieldset/CSR:
description: Control and status register description: Control and status register
fields: fields:

1260
data/registers/rcc_l0_v2.yaml Normal file
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1
stm32-data-gen/src/chips.rs
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@ -299,6 +299,7 @@ impl PeriMatcher {
("STM32H7[AB].*:RCC:.*", ("rcc", "h7ab", "RCC")), ("STM32H7[AB].*:RCC:.*", ("rcc", "h7ab", "RCC")),
("STM32H7(42|43|53|50).*:RCC:.*", ("rcc", "h7rm0433", "RCC")), ("STM32H7(42|43|53|50).*:RCC:.*", ("rcc", "h7rm0433", "RCC")),
("STM32H7.*:RCC:.*", ("rcc", "h7", "RCC")), ("STM32H7.*:RCC:.*", ("rcc", "h7", "RCC")),
("STM32L0.[23].*:RCC:.*", ("rcc", "l0_v2", "RCC")),
("STM32L0.*:RCC:.*", ("rcc", "l0", "RCC")), ("STM32L0.*:RCC:.*", ("rcc", "l0", "RCC")),
("STM32L1.*:RCC:.*", ("rcc", "l1", "RCC")), ("STM32L1.*:RCC:.*", ("rcc", "l1", "RCC")),
("STM32L4.*:RCC:.*", ("rcc", "l4", "RCC")), ("STM32L4.*:RCC:.*", ("rcc", "l4", "RCC")),