Separate block for H7AB

data/registers/rcc_h7.yaml

@@ -303,94 +303,6 @@ block/RCC:
     description: RCC APB4 Sleep Clock Register
     fieldset: C1_APB4LPENR
     name: C1_APB4LPENR
-  - byte_offset: 76
-    description: RCC Domain 1 Kernel Clock Configuration Register
-    fieldset: CDCCIPR
-    name: CDCCIPR
-  - byte_offset: 80
-    description: RCC Domain 2 Kernel Clock Configuration Register
-    fieldset: CDCCIP1R
-    name: CDCCIP1R
-  - byte_offset: 84
-    description: RCC Domain 2 Kernel Clock Configuration Register
-    fieldset: CDCCIP2R
-    name: CDCCIP2R
-  - byte_offset: 88
-    description: RCC Domain 3 Kernel Clock Configuration Register
-    fieldset: SRDCCIPR
-    name: SRDCCIPR
-  - byte_offset: 308
-    description: RCC AHB3 Clock Register
-    fieldset: AHB3ENR
-    name: AHB3ENR
-  - byte_offset: 312
-    description: RCC AHB1 Clock Register
-    fieldset: AHB1ENR
-    name: AHB1ENR
-  - byte_offset: 316
-    description: RCC AHB2 Clock Register
-    fieldset: AHB2ENR
-    name: AHB2ENR
-  - byte_offset: 320
-    description: RCC AHB4 Clock Register
-    fieldset: AHB4ENR
-    name: AHB4ENR
-  - byte_offset: 324
-    description: RCC APB3 Clock Register
-    fieldset: APB3ENR
-    name: APB3ENR
-  - byte_offset: 328
-    description: RCC APB1 Clock Register
-    fieldset: APB1LENR
-    name: APB1LENR
-  - byte_offset: 332
-    description: RCC APB1 Clock Register
-    fieldset: APB1HENR
-    name: APB1HENR
-  - byte_offset: 336
-    description: RCC APB2 Clock Register
-    fieldset: APB2ENR
-    name: APB2ENR
-  - byte_offset: 340
-    description: RCC APB4 Clock Register
-    fieldset: APB4ENR
-    name: APB4ENR
-  - byte_offset: 348
-    description: RCC AHB3 Sleep Clock Register
-    fieldset: AHB3LPENR
-    name: AHB3LPENR
-  - byte_offset: 352
-    description: RCC AHB1 Sleep Clock Register
-    fieldset: AHB1LPENR
-    name: AHB1LPENR
-  - byte_offset: 356
-    description: RCC AHB2 Sleep Clock Register
-    fieldset: AHB2LPENR
-    name: AHB2LPENR
-  - byte_offset: 360
-    description: RCC AHB4 Sleep Clock Register
-    fieldset: AHB4LPENR
-    name: AHB4LPENR
-  - byte_offset: 364
-    description: RCC APB3 Sleep Clock Register
-    fieldset: APB3LPENR
-    name: APB3LPENR
-  - byte_offset: 368
-    description: RCC APB1 Low Sleep Clock Register
-    fieldset: APB1LLPENR
-    name: APB1LLPENR
-  - byte_offset: 372
-    description: RCC APB1 High Sleep Clock Register
-    fieldset: APB1HLPENR
-    name: APB1HLPENR
-  - byte_offset: 376
-    description: RCC APB2 Sleep Clock Register
-    fieldset: APB2LPENR
-    name: APB2LPENR
-  - byte_offset: 380
-    description: RCC APB4 Sleep Clock Register
-    fieldset: APB4LPENR
-    name: APB4LPENR
 enum/ADCSEL:
   bit_size: 2
   variants:
@@ -427,15 +339,6 @@ enum/CKPERSEL:
   - description: HSE selected as peripheral clock
     name: HSE
     value: 2
-enum/CPURSTFR:
-  bit_size: 1
-  variants:
-  - description: No reset occoured for block
-    name: NoResetOccoured
-    value: 0
-  - description: Reset occoured for block
-    name: ResetOccourred
-    value: 1
 enum/C_RSR_CPURSTFR:
   bit_size: 1
   variants:
@@ -1024,15 +927,6 @@ enum/PLLVCOSEL:
   - description: VCO frequency range 150 to 420 MHz
     name: MediumVCO
     value: 1
-enum/RMVF:
-  bit_size: 1
-  variants:
-  - description: Not clearing the the reset flags
-    name: NotActive
-    value: 0
-  - description: Clear the reset flags
-    name: Clear
-    value: 1
 enum/RNGSEL:
   bit_size: 2
   variants:
@@ -1126,21 +1020,6 @@ enum/SDMMCSEL:
   - description: pll2_r selected as peripheral clock
     name: PLL2_R
     value: 1
-enum/SPDIFRXSEL:
-  bit_size: 2
-  variants:
-  - description: pll1_q selected as peripheral clock
-    name: PLL1_Q
-    value: 0
-  - description: pll2_r selected as peripheral clock
-    name: PLL2_R
-    value: 1
-  - description: pll3_r selected as peripheral clock
-    name: PLL3_R
-    value: 2
-  - description: hsi_ker selected as peripheral clock
-    name: HSI_KER
-    value: 3
 enum/SPDIFSEL:
   bit_size: 2
   variants:
@@ -1255,27 +1134,6 @@ enum/TIMPRE:
   - description: Timer kernel clock equal to 4x pclk by default
     name: DefaultX4
     value: 1
-enum/USART16910SEL:
-  bit_size: 3
-  variants:
-  - description: rcc_pclk2 selected as peripheral clock
-    name: RCC_PCLK2
-    value: 0
-  - description: pll2_q selected as peripheral clock
-    name: PLL2_Q
-    value: 1
-  - description: pll3_q selected as peripheral clock
-    name: PLL3_Q
-    value: 2
-  - description: hsi_ker selected as peripheral clock
-    name: HSI_KER
-    value: 3
-  - description: csi_ker selected as peripheral clock
-    name: CSI_KER
-    value: 4
-  - description: LSE selected as peripheral clock
-    name: LSE
-    value: 5
 enum/USART16SEL:
   bit_size: 3
   variants:
@@ -1666,10 +1524,6 @@ fieldset/AHB3LPENR:
     bit_size: 1
     description: FLITF Clock Enable During CSleep Mode
     name: FLITFLPEN
-  - bit_offset: 8
-    bit_size: 1
-    description: Flash interface clock enable during csleep mode
-    name: FLASHPREN
 fieldset/AHB3RSTR:
   description: RCC AHB3 Reset Register
   fields:
@@ -2070,10 +1924,6 @@ fieldset/APB1LENR:
     bit_size: 1
     description: WWDG2 peripheral clock enable
     name: WWDG2EN
-  - bit_offset: 29
-    bit_size: 1
-    description: DAC1 (containing two converters) peripheral clock enable
-    name: DAC1EN
 fieldset/APB1LLPENR:
   description: RCC APB1 Low Sleep Clock Register
   fields:
@@ -2177,11 +2027,6 @@ fieldset/APB1LLPENR:
     bit_size: 1
     description: WWDG2 peripheral Clocks Enable During CSleep Mode
     name: WWDG2LPEN
-  - bit_offset: 29
-    bit_size: 1
-    description: DAC1 (containing two converters) peripheral clock enable during CSleep
-      mode
-    name: DAC1LPEN
 fieldset/APB1LRSTR:
   description: RCC APB1 Peripheral Reset Register
   fields:
@@ -2281,10 +2126,6 @@ fieldset/APB1LRSTR:
     bit_size: 1
     description: UART8 block reset
     name: UART8RST
-  - bit_offset: 29
-    bit_size: 1
-    description: DAC1 (containing two converters) reset
-    name: DAC1RST
 fieldset/APB2ENR:
   description: RCC APB2 Clock Register
   fields:
@@ -2566,10 +2407,6 @@ fieldset/APB4ENR:
     bit_size: 1
     description: SAI4 Peripheral Clocks Enable
     name: SAI4EN
-  - bit_offset: 13
-    bit_size: 1
-    description: DAC2 (containing one converter) peripheral clock enable
-    name: DAC2EN
 fieldset/APB4LPENR:
   description: RCC APB4 Sleep Clock Register
   fields:
@@ -2621,11 +2458,6 @@ fieldset/APB4LPENR:
     bit_size: 1
     description: SAI4 Peripheral Clocks Enable During CSleep Mode
     name: SAI4LPEN
-  - bit_offset: 13
-    bit_size: 1
-    description: DAC2 (containing one converter) peripheral clock enable during CSleep
-      mode
-    name: DAC2LPEN
 fieldset/APB4RSTR:
   description: RCC APB4 Peripheral Reset Register
   fields:
@@ -2673,10 +2505,6 @@ fieldset/APB4RSTR:
     bit_size: 1
     description: SAI4 block reset
     name: SAI4RST
-  - bit_offset: 13
-    bit_size: 1
-    description: DAC2 (containing one converter) reset
-    name: DAC2RST
 fieldset/BDCR:
   description: RCC Backup Domain Control Register
   fields:
@@ -3661,115 +3489,6 @@ fieldset/C1_RSR:
     description: Reset due to illegal D1 DStandby or CPU CStop flag
     enum_read: C_RSR_CPURSTFR
     name: LPWRRSTF
-fieldset/CDCCIP1R:
-  description: RCC Domain 2 Kernel Clock Configuration Register
-  fields:
-  - bit_offset: 0
-    bit_size: 3
-    description: SAI1 and DFSDM1 kernel Aclk clock source selection
-    enum: SAISEL
-    name: SAI1SEL
-  - bit_offset: 6
-    bit_size: 3
-    description: SAI2 kernel clock source A source selection
-    enum: SAIASEL
-    name: SAI2ASEL
-  - bit_offset: 9
-    bit_size: 3
-    description: SAI2 kernel clock source B source selection
-    enum: SAIASEL
-    name: SAI2BSEL
-  - bit_offset: 12
-    bit_size: 3
-    description: SPI/I2S1,2 and 3 kernel clock source selection
-    enum: SAISEL
-    name: SPI123SEL
-  - bit_offset: 16
-    bit_size: 3
-    description: SPI4 and 5 kernel clock source selection
-    enum: SPI45SEL
-    name: SPI45SEL
-  - bit_offset: 20
-    bit_size: 2
-    description: SPDIFRX kernel clock source selection
-    enum: SPDIFRXSEL
-    name: SPDIFRXSEL
-  - bit_offset: 24
-    bit_size: 1
-    description: DFSDM1 kernel Clk clock source selection
-    enum: DFSDMSEL
-    name: DFSDM1SEL
-  - bit_offset: 28
-    bit_size: 2
-    description: FDCAN kernel clock source selection
-    enum: FDCANSEL
-    name: FDCANSEL
-  - bit_offset: 31
-    bit_size: 1
-    description: SWPMI kernel clock source selection
-    enum: SWPSEL
-    name: SWPSEL
-fieldset/CDCCIP2R:
-  description: RCC Domain 2 Kernel Clock Configuration Register
-  fields:
-  - bit_offset: 0
-    bit_size: 3
-    description: USART2/3, UART4,5, 7/8 (APB1) kernel clock source selection
-    enum: USART234578SEL
-    name: USART234578SEL
-  - bit_offset: 3
-    bit_size: 3
-    description: USART1, 6, 9 and 10 kernel clock source selection
-    enum: USART16910SEL
-    name: USART16910SEL
-  - bit_offset: 8
-    bit_size: 2
-    description: RNG kernel clock source selection
-    enum: RNGSEL
-    name: RNGSEL
-  - bit_offset: 12
-    bit_size: 2
-    description: I2C1,2,3 kernel clock source selection
-    enum: I2C123SEL
-    name: I2C123SEL
-  - bit_offset: 20
-    bit_size: 2
-    description: USBOTG 1 and 2 kernel clock source selection
-    enum: USBSEL
-    name: USBSEL
-  - bit_offset: 22
-    bit_size: 2
-    description: HDMI-CEC kernel clock source selection
-    enum: CECSEL
-    name: CECSEL
-  - bit_offset: 28
-    bit_size: 3
-    description: LPTIM1 kernel clock source selection
-    enum: LPTIM1SEL
-    name: LPTIM1SEL
-fieldset/CDCCIPR:
-  description: RCC Domain 1 Kernel Clock Configuration Register
-  fields:
-  - bit_offset: 0
-    bit_size: 2
-    description: FMC kernel clock source selection
-    enum: FMCSEL
-    name: FMCSEL
-  - bit_offset: 4
-    bit_size: 2
-    description: OCTOSPI kernel clock source selection
-    enum: FMCSEL
-    name: OCTOSPISEL
-  - bit_offset: 16
-    bit_size: 1
-    description: SDMMC kernel clock source selection
-    enum: SDMMCSEL
-    name: SDMMCSEL
-  - bit_offset: 28
-    bit_size: 2
-    description: per_ck clock source selection
-    enum: CKPERSEL
-    name: CKPERSEL
 fieldset/CFGR:
   description: RCC Clock Configuration Register
   fields:
@@ -4323,10 +4042,6 @@ fieldset/D3AMR:
     bit_size: 1
     description: Backup RAM Autonomous mode enable
     name: BKPSRAMAMEN
-  - bit_offset: 13
-    bit_size: 1
-    description: DAC2 (containing one converter) Autonomous mode enable
-    name: DAC2AMEN
 fieldset/D3CCIPR:
   description: RCC Domain 3 Kernel Clock Configuration Register
   fields:
@@ -4379,7 +4094,7 @@ fieldset/D3CFGR:
     enum: DPPRE
     name: D3PPRE
 fieldset/GCR:
-  description: Global Control Register
+  description: RCC Global Control Register
   fields:
   - bit_offset: 0
     bit_size: 1
@@ -4706,39 +4421,3 @@ fieldset/RSR:
     description: Reset due to illegal D1 DStandby or CPU CStop flag
     enum_read: RSR_CPURSTFR
     name: LPWRRSTF
-fieldset/SRDCCIPR:
-  description: RCC Domain 3 Kernel Clock Configuration Register
-  fields:
-  - bit_offset: 0
-    bit_size: 3
-    description: LPUART1 kernel clock source selection
-    enum: LPUARTSEL
-    name: LPUART1SEL
-  - bit_offset: 8
-    bit_size: 2
-    description: I2C4 kernel clock source selection
-    enum: I2C4SEL
-    name: I2C4SEL
-  - bit_offset: 10
-    bit_size: 3
-    description: LPTIM2 kernel clock source selection
-    enum: LPTIM2SEL
-    name: LPTIM2SEL
-  - bit_offset: 13
-    bit_size: 3
-    description: LPTIM3,4,5 kernel clock source selection
-    name: LPTIM3SEL
-  - bit_offset: 16
-    bit_size: 2
-    description: SAR ADC kernel clock source selection
-    enum: ADCSEL
-    name: ADCSEL
-  - bit_offset: 27
-    bit_size: 1
-    description: DFSDM2 kernel clock source selection
-    name: DFSDM2SEL
-  - bit_offset: 28
-    bit_size: 3
-    description: SPI6 kernel clock source selection
-    enum: SPI6SEL
-    name: SPI6SEL

parse.py

@@ -244,10 +244,11 @@ perimap = [
     ('STM32L0.*:RCC:.*', 'rcc_l0/RCC'),
     ('STM32L4.*:RCC:.*', 'rcc_l4/RCC'),
     ('STM32F4.*:RCC:.*', 'rcc_f4/RCC'),
+    ('.*:STM32H7AB_rcc_v1_0', 'rcc_h7ab/RCC'),
+    ('.*:STM32H7_rcc_v1_0', 'rcc_h7/RCC'),
     ('.*:STM32L0_dbgmcu_v1_0', 'dbg_l0/DBG'),
     ('.*:STM32L0_crs_v1_0', 'crs_l0/CRS'),
     ('.*SDMMC:sdmmc2_v1_0', 'sdmmc_v2/SDMMC'),
-    ('.*:STM32H7_rcc_v1_0', 'rcc_h7/RCC'),
     ('.*:STM32H7_pwr_v1_0', 'pwr_h7/PWR'),
     ('.*:STM32H7_flash_v1_0', 'flash_h7/FLASH'),
     ('.*:STM32H7_dbgmcu_v1_0', 'dbgmcu_h7/DBGMCU'),