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update RNG registers and mapping

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This commit is contained in:
Jan Christoph Bernack 2023-06-27 02:58:23 +02:00
parent 9f043c5eab
commit f1b05d243d
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GPG Key ID: BD807E5761329D0A
4 changed files with 304 additions and 15 deletions
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4
data/registers/rng_v1.yaml
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@ -25,6 +25,10 @@ fieldset/CR:
description: Interrupt enable description: Interrupt enable
bit_offset: 3 bit_offset: 3
bit_size: 1 bit_size: 1
- name: CED
description: Clock error detection
bit_offset: 5
bit_size: 1
fieldset/SR: fieldset/SR:
description: status register description: status register
fields: fields:

110
data/registers/rng_v2.yaml
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@ -17,15 +17,16 @@ block/RNG:
- name: HTCR - name: HTCR
description: health test control register description: health test control register
byte_offset: 16 byte_offset: 16
fieldset: HTCR
fieldset/CR: fieldset/CR:
description: control register description: control register
fields: fields:
- name: RNGEN - name: RNGEN
description: True random number generator enable description: Random number generator enable
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
- name: IE - name: IE
description: Interrupt Enable description: Interrupt enable
bit_offset: 3 bit_offset: 3
bit_size: 1 bit_size: 1
- name: CED - name: CED
@ -36,6 +37,7 @@ fieldset/CR:
description: RNG configuration 3 description: RNG configuration 3
bit_offset: 8 bit_offset: 8
bit_size: 4 bit_size: 4
enum: RNG_CONFIG3
- name: NISTC - name: NISTC
description: Non NIST compliant description: Non NIST compliant
bit_offset: 12 bit_offset: 12
@ -45,14 +47,17 @@ fieldset/CR:
description: RNG configuration 2 description: RNG configuration 2
bit_offset: 13 bit_offset: 13
bit_size: 3 bit_size: 3
enum: RNG_CONFIG2
- name: CLKDIV - name: CLKDIV
description: Clock divider factor description: Clock divider factor
bit_offset: 16 bit_offset: 16
bit_size: 4 bit_size: 4
enum: CLKDIV
- name: RNG_CONFIG1 - name: RNG_CONFIG1
description: RNG configuration 1 description: RNG configuration 1
bit_offset: 20 bit_offset: 20
bit_size: 6 bit_size: 6
enum: RNG_CONFIG1
- name: CONDRST - name: CONDRST
description: Conditioning soft reset description: Conditioning soft reset
bit_offset: 30 bit_offset: 30
@ -61,18 +66,11 @@ fieldset/CR:
description: Config Lock description: Config Lock
bit_offset: 31 bit_offset: 31
bit_size: 1 bit_size: 1
fieldset/HTCR:
description: health test control register
fields:
- name: HTCFG
description: health test configuration
bit_offset: 0
bit_size: 32
fieldset/SR: fieldset/SR:
description: status register description: status register
fields: fields:
- name: DRDY - name: DRDY
description: Data Ready description: Data ready
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: CECS - name: CECS
@ -91,6 +89,74 @@ fieldset/SR:
description: Seed error interrupt status description: Seed error interrupt status
bit_offset: 6 bit_offset: 6
bit_size: 1 bit_size: 1
fieldset/HTCR:
description: Health test control register
fields:
- name: HTCFG
description: Health test configuration
bit_offset: 0
bit_size: 32
enum: HTCFG
enum/CLKDIV:
bit_size: 4
variants:
- name: NoDiv
description: Internal RNG clock after divider is similar to incoming RNG clock
value: 0
- name: Div_2_1
description: Divide RNG clock by 2^1
value: 1
- name: Div_2_2
description: Divide RNG clock by 2^2
value: 2
- name: Div_2_3
description: Divide RNG clock by 2^3
value: 3
- name: Div_2_4
description: Divide RNG clock by 2^4
value: 4
- name: Div_2_5
description: Divide RNG clock by 2^5
value: 5
- name: Div_2_6
description: Divide RNG clock by 2^6
value: 6
- name: Div_2_7
description: Divide RNG clock by 2^7
value: 7
- name: Div_2_8
description: Divide RNG clock by 2^8
value: 8
- name: Div_2_9
description: Divide RNG clock by 2^9
value: 9
- name: Div_2_10
description: Divide RNG clock by 2^10
value: 10
- name: Div_2_11
description: Divide RNG clock by 2^11
value: 11
- name: Div_2_12
description: Divide RNG clock by 2^12
value: 12
- name: Div_2_13
description: Divide RNG clock by 2^13
value: 13
- name: Div_2_14
description: Divide RNG clock by 2^14
value: 14
- name: Div_2_15
description: Divide RNG clock by 2^15
value: 15
enum/HTCFG:
bit_size: 32
variants:
- name: Recommended
description: Recommended value for RNG certification (0x0000_AA74)
value: 43636
- name: Magic
description: Magic number to be written before any write (0x1759_0ABC)
value: 391711420
enum/NISTC: enum/NISTC:
bit_size: 1 bit_size: 1
variants: variants:
@ -100,3 +166,27 @@ enum/NISTC:
- name: Custom - name: Custom
description: Custom values for NIST compliant RNG description: Custom values for NIST compliant RNG
value: 1 value: 1
enum/RNG_CONFIG1:
bit_size: 6
variants:
- name: ConfigA
description: Recommended value for config A (NIST certifiable)
value: 15
- name: ConfigB
description: Recommended value for config B (not NIST certifiable)
value: 24
enum/RNG_CONFIG2:
bit_size: 3
variants:
- name: ConfigA_B
description: Recommended value for config A and B
value: 0
enum/RNG_CONFIG3:
bit_size: 4
variants:
- name: ConfigB
description: Recommended value for config B (not NIST certifiable)
value: 0
- name: ConfigA
description: Recommended value for config A (NIST certifiable)
value: 13

196
data/registers/rng_v3.yaml Normal file
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@ -0,0 +1,196 @@
---
block/RNG:
description: Random number generator
items:
- name: CR
description: control register
byte_offset: 0
fieldset: CR
- name: SR
description: status register
byte_offset: 4
fieldset: SR
- name: DR
description: data register
byte_offset: 8
access: Read
- name: HTCR
description: health test control register
byte_offset: 16
fieldset: HTCR
fieldset/CR:
description: control register
fields:
- name: RNGEN
description: Random number generator enable
bit_offset: 2
bit_size: 1
- name: IE
description: Interrupt enable
bit_offset: 3
bit_size: 1
- name: CED
description: Clock error detection
bit_offset: 5
bit_size: 1
- name: ARDIS
description: Auto reset disable
bit_offset: 7
bit_size: 1
- name: RNG_CONFIG3
description: RNG configuration 3
bit_offset: 8
bit_size: 4
enum: RNG_CONFIG3
- name: NISTC
description: Non NIST compliant
bit_offset: 12
bit_size: 1
enum: NISTC
- name: RNG_CONFIG2
description: RNG configuration 2
bit_offset: 13
bit_size: 3
enum: RNG_CONFIG2
- name: CLKDIV
description: Clock divider factor
bit_offset: 16
bit_size: 4
enum: CLKDIV
- name: RNG_CONFIG1
description: RNG configuration 1
bit_offset: 20
bit_size: 6
enum: RNG_CONFIG1
- name: CONDRST
description: Conditioning soft reset
bit_offset: 30
bit_size: 1
- name: CONFIGLOCK
description: Config Lock
bit_offset: 31
bit_size: 1
fieldset/SR:
description: status register
fields:
- name: DRDY
description: Data ready
bit_offset: 0
bit_size: 1
- name: CECS
description: Clock error current status
bit_offset: 1
bit_size: 1
- name: SECS
description: Seed error current status
bit_offset: 2
bit_size: 1
- name: CEIS
description: Clock error interrupt status
bit_offset: 5
bit_size: 1
- name: SEIS
description: Seed error interrupt status
bit_offset: 6
bit_size: 1
fieldset/HTCR:
description: Health test control register
fields:
- name: HTCFG
description: Health test configuration
bit_offset: 0
bit_size: 32
enum: HTCFG
enum/CLKDIV:
bit_size: 4
variants:
- name: NoDiv
description: Internal RNG clock after divider is similar to incoming RNG clock
value: 0
- name: Div_2_1
description: Divide RNG clock by 2^1
value: 1
- name: Div_2_2
description: Divide RNG clock by 2^2
value: 2
- name: Div_2_3
description: Divide RNG clock by 2^3
value: 3
- name: Div_2_4
description: Divide RNG clock by 2^4
value: 4
- name: Div_2_5
description: Divide RNG clock by 2^5
value: 5
- name: Div_2_6
description: Divide RNG clock by 2^6
value: 6
- name: Div_2_7
description: Divide RNG clock by 2^7
value: 7
- name: Div_2_8
description: Divide RNG clock by 2^8
value: 8
- name: Div_2_9
description: Divide RNG clock by 2^9
value: 9
- name: Div_2_10
description: Divide RNG clock by 2^10
value: 10
- name: Div_2_11
description: Divide RNG clock by 2^11
value: 11
- name: Div_2_12
description: Divide RNG clock by 2^12
value: 12
- name: Div_2_13
description: Divide RNG clock by 2^13
value: 13
- name: Div_2_14
description: Divide RNG clock by 2^14
value: 14
- name: Div_2_15
description: Divide RNG clock by 2^15
value: 15
enum/HTCFG:
bit_size: 32
variants:
- name: Recommended
description: Recommended value for RNG certification (0x0000_AA74)
value: 43636
- name: Magic
description: Magic number to be written before any write (0x1759_0ABC)
value: 391711420
enum/NISTC:
bit_size: 1
variants:
- name: Default
description: Hardware default values for NIST compliant RNG. In this configuration per 128-bit output two conditioning loops are performed and 256 bits of noise source are used
value: 0
- name: Custom
description: Custom values for NIST compliant RNG
value: 1
enum/RNG_CONFIG1:
bit_size: 6
variants:
- name: ConfigA
description: Recommended value for config A (NIST certifiable)
value: 15
- name: ConfigB
description: Recommended value for config B (not NIST certifiable)
value: 24
enum/RNG_CONFIG2:
bit_size: 3
variants:
- name: ConfigA_B
description: Recommended value for config A and B
value: 0
enum/RNG_CONFIG3:
bit_size: 4
variants:
- name: ConfigB
description: Recommended value for config B (not NIST certifiable)
value: 0
- name: ConfigA
description: Recommended value for config A (NIST certifiable)
value: 13

9
stm32-data-gen/src/chips.rs
View File

@ -130,12 +130,11 @@ impl PeriMatcher {
(".*:LPUART:sci3_v1_2", ("usart", "v4", "LPUART")), (".*:LPUART:sci3_v1_2", ("usart", "v4", "LPUART")),
(".*:LPUART:sci3_v1_3", ("usart", "v4", "LPUART")), (".*:LPUART:sci3_v1_3", ("usart", "v4", "LPUART")),
(".*:LPUART:sci3_v1_4", ("usart", "v4", "LPUART")), (".*:LPUART:sci3_v1_4", ("usart", "v4", "LPUART")),
("STM32[HU]5.*:RNG:.*", ("rng", "v3", "RNG")), // adds auto-reset bit ARDIS
("STM32L5.*:RNG:.*", ("rng", "v2", "RNG")), ("STM32L5.*:RNG:.*", ("rng", "v2", "RNG")),
(".*:RNG:rng1_v1_1", ("rng", "v1", "RNG")), ("STM32L4[PQ]5.*:RNG:.*", ("rng", "v2", "RNG")),
(".*:RNG:rng1_v2_0", ("rng", "v1", "RNG")), ("STM32WL.*:RNG:.*", ("rng", "v2", "RNG")),
(".*:RNG:rng1_v2_1", ("rng", "v1", "RNG")), (".*:RNG:.*", ("rng", "v1", "RNG")), // use rng_v1 for everything else
(".*:RNG:rng1_v3_1", ("rng", "v2", "RNG")),
(".*:RNG:rng1_v4_1", ("rng", "v2", "RNG")),
(".*:SPI:spi2_v1_4", ("spi", "f1", "SPI")), (".*:SPI:spi2_v1_4", ("spi", "f1", "SPI")),
(".*:SPI:spi2s1_v2_1", ("spi", "v1", "SPI")), (".*:SPI:spi2s1_v2_1", ("spi", "v1", "SPI")),
(".*:SPI:spi2s1_v2_2", ("spi", "v1", "SPI")), (".*:SPI:spi2s1_v2_2", ("spi", "v1", "SPI")),